CN205302268U - Computer motherboard switching on and shutting down and test card that resets - Google Patents
Computer motherboard switching on and shutting down and test card that resets Download PDFInfo
- Publication number
- CN205302268U CN205302268U CN201521128454.3U CN201521128454U CN205302268U CN 205302268 U CN205302268 U CN 205302268U CN 201521128454 U CN201521128454 U CN 201521128454U CN 205302268 U CN205302268 U CN 205302268U
- Authority
- CN
- China
- Prior art keywords
- test
- cpld chip
- test card
- reset circuit
- mainboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The utility creatively provides a computer motherboard switching on and shutting down and test card that resets, including the test card body, be equipped with CPLD chip, LED pilot lamp, RS232 serial ports, reset circuit interface and power source on the test card body, RS232 serial ports, LED pilot lamp, reset circuit interface and power source are connected to the CPLD chip, and the CPLD chip passes through the RS232 serial port connection mainboard, the CPLD chip passes through power source connection and mainboard connection's ATX power, the CPLD chip passes through the reset circuit interface. Compared with the prior art, the utility model discloses the creation has following advantage: realize automatic test, saved the human cost, can test by long continuous time, improved efficiency of software testing, shortened test time, time number of times that can the automatic recording mistake produces test report, has reduced because the mistake that the human factor caused.
Description
Technical field
The invention belongs to computer motherboard technical field of measurement and test, especially relates to a kind of computer main-board on-off and reset test card.
Background technology
For the computer motherboard designed, long switching on and shutting down test and reset test will be carried out, verify the stability of main-board on-off and reset, with or without can not the situation of normal boot-strap, whether reset circuit can reset computer every time reliably; Generally through the test of up to ten thousand times, to add up fault rate, high application to be required for some, it is desirable to fault rate is 0. Traditional main-board on-off test be all by motherboard accessed ATX power supply (or AT power supply) manually powering on, power-off realizes switching on and shutting down test, this method not only wastes manpower but also when switching on and shutting down number of times reaches certain value, tester also is difficult to accurate recording.
Summary of the invention
In view of this, the invention is directed to a kind of computer main-board on-off and reset test card, to save switching on and shutting down and reset test time and manpower.
For reaching above-mentioned purpose, the technical scheme of the invention is achieved in that
A kind of computer main-board on-off and reset test card, including test card body, described test card body be provided with CPLD chip, LED light, for connecting the RS232 serial ports of mainboard, for connecting the reset circuit interface of mainboard reset circuit and for connecting the power interface of mainboard ATX power supply, described CPLD chip connects RS232 serial ports, LED light, reset circuit interface and power interface.
Further, described CPLD chip selects model to be EPM1270CPLD chip.
Relative to prior art, the invention has the advantage that
Realize automatic test, save human cost; Can follow-on test for a long time, improve testing efficiency, shorten the testing time; Can the time number of times of misregistration automatically, produce test report, decrease because the mistake that causes of anthropic factor.
Accompanying drawing explanation
The accompanying drawing constituting the part of the invention is used for providing being further appreciated by the invention, and the schematic description and description of the invention is used for explaining the invention, is not intended that the improper restriction to the invention. In the accompanying drawings:
Fig. 1 is the theory diagram of computer main-board on-off and reset test card described in the invention embodiment.
Detailed description of the invention
It should be noted that when not conflicting, the embodiment in the invention and the feature in embodiment can be mutually combined.
Describe the invention below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
A kind of computer main-board on-off and reset test card, as shown in Figure 1, including test card body, described test card body is provided with CPLD chip, LED light, RS232 serial ports, reset circuit interface and power interface, described CPLD chip connects RS232 serial ports, LED light, reset circuit interface and power interface, and CPLD chip connects mainboard by RS232 serial ports; Described CPLD chip connects the ATX power supply being connected with mainboard by power interface, and described CPLD chip passes through reset circuit interface.
Described CPLD chip selects model to be EPM1270CPLD chip.
Mainboard guides internal BIOS after the power-up automatically, BIOS is used for initializing the various hardware resources of mainboard, RS232 is exactly the one of hardware resource, BIOS can send data " AA55 " by the TXD signal of RS232 after mainboard is started shooting smoothly, now the CPLD chip on test card body captures this data, LED light accumulates once, the DOS program record switching on and shutting down number of times of host computer also accumulates once simultaneously, the high level of CPLD chip output simultaneously realizes cutting off the PS_ON signal of ATX power supply, mainboard power-off, CPLD chip time delay controls the PS_ON signal of ATX power supply and becomes low level after 10 seconds, such mainboard switches on power, repeat above step, realize switching on and shutting down.
This process not only achieves switch and test, and upper computer software realizes the functional test to motherboard inside real-time clock (RTC) (RTC) also by the switching on and shutting down moment recorded each time.
After test switching on and shutting down terminate, tester can open host computer procedure and check switching on and shutting down time each time and switching on and shutting down total degree, it is achieved the purpose of record, display, control motherboard switching on and shutting down automatically.
The foregoing is only the preferred embodiment of the invention; not in order to limit the invention; within all spirit in the invention and principle, any amendment of making, equivalent replacement, improvement etc., should be included within the protection domain of the invention.
Claims (2)
1. a computer main-board on-off and reset test card, it is characterized in that: include test card body, described test card body be provided with CPLD chip, LED light, for connecting the RS232 serial ports of mainboard, for connecting the reset circuit interface of mainboard reset circuit and for connecting the power interface of mainboard ATX power supply, described CPLD chip connects RS232 serial ports, LED light, reset circuit interface and power interface.
2. computer main-board on-off according to claim 1 and reset test card, it is characterised in that: described CPLD chip selects model to be EPM1270CPLD chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521128454.3U CN205302268U (en) | 2015-12-28 | 2015-12-28 | Computer motherboard switching on and shutting down and test card that resets |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521128454.3U CN205302268U (en) | 2015-12-28 | 2015-12-28 | Computer motherboard switching on and shutting down and test card that resets |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205302268U true CN205302268U (en) | 2016-06-08 |
Family
ID=56468816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521128454.3U Active CN205302268U (en) | 2015-12-28 | 2015-12-28 | Computer motherboard switching on and shutting down and test card that resets |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205302268U (en) |
-
2015
- 2015-12-28 CN CN201521128454.3U patent/CN205302268U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8832615B2 (en) | Method for detecting and debugging design errors in low power IC design | |
| CN102023912B (en) | Dormancy wake-up testing system and method | |
| CN106055440B (en) | A kind of test method and system for realizing server exception power-off by BMC | |
| CN107368636B (en) | Single-machine application verification system compatible with spark V8 architecture SOC | |
| CN104572371A (en) | Abnormal power-down testing system for hard disk | |
| CN104572226A (en) | Method and device for detecting mainboard starting abnormity | |
| CN102520272A (en) | Test system of power down protection function of smart card and method | |
| CN109462495A (en) | A kind of ship hardware and communication system detection system and method | |
| CN104572442A (en) | In-chip program checking system for programmable logic chip | |
| CN103699112A (en) | Aviation electronic self-detection verification equipment based on IO (Input/Output) signal failure simulation, and verification method of equipment | |
| CN105791497A (en) | Automatic testing system of power consumption of mobile terminal and working method of automatic testing system | |
| CN104239176A (en) | Multi-user multi-target remote JTAG debugging system based on Internet | |
| CN101908878A (en) | Time sequence improving circuit | |
| CN205302268U (en) | Computer motherboard switching on and shutting down and test card that resets | |
| Hazra et al. | Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent | |
| CN201638219U (en) | Real-time FPGA verification system | |
| CN109271009A (en) | A kind of method, apparatus that control server backboard powers on and CPLD | |
| CN204790996U (en) | CPU and FPGA combinatorial circuit of multiplex bus | |
| CN105511994A (en) | Startup/shutdown and reset test card for computer motherboard | |
| CN205263730U (en) | Novel IO riser integrated circuit board based on POWER platform | |
| CN104932993A (en) | Stable hot plug driving method and apparatus as well as hot plugging supporting device | |
| CN105204999A (en) | Method for realizing automatic test of CPU VR Static LL test | |
| CN207021988U (en) | A kind of control circuit of express delivery cabinet | |
| CN102722232B (en) | Control system that a kind of ATCA blade powers on and method | |
| CN106200353B (en) | A method of the clock for testing twin-core electric energy meter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |