CN105448992A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN105448992A CN105448992A CN201410480137.1A CN201410480137A CN105448992A CN 105448992 A CN105448992 A CN 105448992A CN 201410480137 A CN201410480137 A CN 201410480137A CN 105448992 A CN105448992 A CN 105448992A
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- substrate
- layer
- semiconductor
- etched hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a manufacturing method of a semiconductor device. The manufacturing method comprises the steps of: providing a semiconductor substrate; forming a first semiconductor layer on part of the substrate, forming a second semiconductor layer on the substrate and the first semiconductor layer, and forming a first isolation member on the substrate; forming a device structure by taking the second semiconductor layer on the first semiconductor layer as an active region; forming through etching holes in the second semiconductor layer on the first semiconductor layer; removing the first semiconductor layer by corrosion through the etching holes to form an empty cavity; filling dielectric materials in the empty cavity to form a buried layer, and filling dielectric materials in the etching holes to form insulation holes; and forming a second isolation member of the device structure on the substrate at two sides of a grid and between the first isolation member and the buried layer. The manufacturing method of the semiconductor device can implement an SOI device through the integrated substrate, the thickness of the buried layer can be adjusted through the thickness of the formed first semiconductor layer, requirements of different devices are satisfied, and the process is simple and practicable.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of semiconductor device and manufacture method thereof.
Background technology
Along with the characteristic size of device constantly reduces, entering nanoscale especially after below 22nm size, the Limits properties closing on Semiconductor Physics device is comed one after another, as capacity loss, leakage current increase, noise and increasing, latch-up and short-channel effect etc., in order to overcome these problems, SOI (silicon-on-insulator, Silicon-On-Insulator) technology is arisen at the historic moment.
SOI substrate divides thick-layer and thin layer SOI, the width of maximum depletion layer under the thickness of the top layer silicon of thin layer SOI device is less than grid, when the lower thickness of top layer silicon, device changes from part depletion (PartiallyDepletion) to all exhausting (FullyDepletion), when top layer silicon is less than 50nm, for ultra-thin SOI (UltrathinSOI, UTSOI), SOI device all exhausts, the device all exhausted has larger current driving force, steep sub-threshold slope, less short channel, the advantages such as narrow-channel effect and completely elimination Kink effect, be specially adapted at a high speed, low pressure, the application of low consumption circuit, ultra-thin SOI becomes the ideal solution of below 22nm dimension process.
But the cost of current SOI substrate is higher, and the specification of the SOI substrate provided is comparatively single, cannot need the thickness adjusting each layer according to device.
Summary of the invention
The object of the invention is to overcome deficiency of the prior art, a kind of semiconductor device and manufacture method thereof are provided, body substrate can be utilized to realize SOI device and buried regions thickness is adjustable.
For achieving the above object, technical scheme of the present invention is:
A manufacture method for semiconductor device, comprises step:
Semiconductor substrate is provided;
Section substrate is formed the first semiconductor layer, substrate and the first semiconductor layer forms the second semiconductor layer, substrate is formed with the first isolation;
With the second semiconductor layer of the first semiconductor layer for active area forms device architecture;
Through etched hole is formed in the second semiconductor layer of the first semiconductor layer;
By etched hole erosion removal first semiconductor layer, to form cavity;
Filled media material in cavity and etched hole, to form buried regions and insulated hole respectively;
Substrate between grid both sides, buried regions is formed the second isolation of device architecture.
Optionally, the step forming the first semiconductor layer and the second semiconductor layer specifically comprises:
Substrate is formed the first mask layer, and the substrate of etched portions thickness;
Carry out selective epitaxial growth, form the first semiconductor layer;
Remove the first mask layer;
Carry out epitaxial growth, form the second semiconductor layer;
Etch the second semiconductor layer and substrate, to form the first groove;
Fill the first groove, to form the first isolation.
Optionally, described substrate is silicon substrate, and described first semiconductor layer is Ge
xsi
1-x, wherein 0<x<1, described second semiconductor layer is silicon.
Optionally, by etched hole erosion removal first semiconductor layer, specifically comprise with the step forming cavity:
Adopt HF, H
2o
2, CH
3cOOH and H
2the etching agent of O carries out erosion removal first semiconductor layer, to form cavity.
Optionally, in cavity and etched hole, the step of filled media material specifically comprises:
Adopt ALD technique or CVD technique, fill up first medium layer in the cavities and form first medium layer on the inwall of etched hole; Second dielectric layer is filled up in etched hole.
Optionally, described first medium layer is high K medium material, and second dielectric layer is silica.
Optionally, the step substrate between grid both sides, buried regions being formed the second isolation of device architecture specifically comprises:
Etching buried regions between substrate and part connect with substrate buried regions and on structure, form the second groove;
Carry out the filling of the second groove, to form the second isolation.
In addition, present invention also offers the semiconductor device that said method is formed, comprising:
Semiconductor substrate;
Buried regions in Semiconductor substrate and the second semiconductor layer on it;
First isolation 110 of interval second semiconductor layer on substrate;
Device architecture on second semiconductor layer;
Second isolating of device architecture on grid both sides, substrate between the first isolation with buried regions;
Run through the etched hole of the second semiconductor layer, be positioned at the both sides of the grid of device architecture, in etched hole, be filled with dielectric material.
Optionally, buried regions is first medium layer, and the dielectric material in described etched hole comprises the first medium layer on etched hole inwall and fills the second dielectric layer of etched hole.
Optionally, described first medium layer is high K medium material, and second dielectric layer is silica.
The manufacture method of semiconductor device of the present invention, first roughly determine active area by the first semiconductor layer, and the second semiconductor layer thereon forms device, then, remove the first semiconductor layer by etching etched hole in the second semiconductor layer, and filled media layer again, can realize SOI device by body substrate, meanwhile, the thickness of buried regions can be regulated by the thickness of the first semiconductor layer formed, meet the demand of different components, simple for process.
Accompanying drawing explanation
In order to be illustrated more clearly in technical scheme of the invention process, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 shows the flow chart of the manufacture method of semiconductor device of the present invention;
Fig. 2-Figure 14 A be according to the embodiment of the present invention manufacture semiconductor device each manufacture process in vertical view and AA to cross section structure schematic diagram.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Shown in figure 1, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided; Section substrate is formed the first semiconductor layer, substrate and the first semiconductor layer forms the second semiconductor layer, described substrate is formed with the first isolation; With the second semiconductor layer of the first semiconductor layer for active area forms device architecture; Through etched hole is formed in the second semiconductor layer of the first semiconductor layer; By etched hole erosion removal first semiconductor layer, to form cavity; Filled media material in cavity and etched hole, to form buried regions and insulated hole respectively; Grid both sides, substrate between the first isolation with buried regions form second of device architecture and isolate.
In manufacture method of the present invention, first roughly determine active area by the first semiconductor layer, and the second semiconductor layer thereon forms device, then, remove the first semiconductor layer by etching etched hole in the second semiconductor layer, and filled media layer again, can realize SOI device by body substrate, meanwhile, the thickness of buried regions can be regulated by the thickness of the first semiconductor layer formed, meet the demand of different components, simple for process.
Technical scheme for a better understanding of the present invention and technique effect, be described in detail below with reference to flow chart Fig. 1 of the manufacture method of semiconductor device of the present invention and specific embodiment.
First, in step S01, provide Semiconductor substrate 100, shown in figure 2, Fig. 2 A (AA of Fig. 2 is to schematic cross-section).
In embodiments of the present invention, described Semiconductor substrate 100 can be Si substrate, Ge substrate etc.In other embodiments, can also be the substrate comprising other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., can also be laminated construction, such as Si/SiGe etc.In the present embodiment, described Semiconductor substrate 100 is body silicon substrate.
Then, in step S02, section substrate 100 forms the first semiconductor layer 106, substrate and the first semiconductor layer 106 form the second semiconductor layer 108, substrate is formed with the first isolation 110, shown in figure 5, Fig. 5 A (AA of Fig. 5 is to schematic cross-section) and Fig. 6.
In the present embodiment, selective epitaxial can be adopted to form the first semiconductor layer, then form the second semiconductor layer by epitaxial growth technology, to form the semiconductor layer of crystal structure.Concrete, first, deposit first mask layer 102, first mask can be silica, silicon nitride, silicon oxynitride or their lamination etc. on the substrate 100, and forms photosensitive etching agent 104 on the first mask layer 102, as best seen in figs. 2 and 2, then, the etching of the first mask layer 102 is carried out under the covering of photosensitive etching agent 104, to form the first mask layer of patterning, and remove photosensitive etching agent 104, under the covering of the first mask layer 102, the certain thickness substrate 100 of further etching, substrate defines the forming region of follow-up formation first semiconductor layer, as shown in Fig. 3 and Fig. 3 A (AA of Fig. 3 is to schematic cross-section), then, carry out selective epitaxial growth (EPI), the region after substrate etching is formed the first semiconductor layer, as shown in Fig. 4 and Fig. 4 A (AA of Fig. 4 is to schematic cross-section), this first semiconductor layer can be Ge
xsi
1-x, wherein 0<x<1, thickness can be 1-200nm, typically can 10nm or 20nm, then, first mask layer 102 is removed, and carry out epitaxial growth second semiconductor layer, like this, all define the second semiconductor layer 108 at substrate 100 and the first semiconductor layer 106, as shown in figs. 5 and 5 (AA of Fig. 5 is to schematic cross-section), this second semiconductor layer 108 can be Si, thickness can be 3-200nm, can be typically 10nm or 15nm, then, shown in figure 6, substrate is formed the first isolation 110, concrete, on the second semiconductor layer 108, first form second mask (scheming not shown) of patterning, and carry out etching second semiconductor layer and substrate, until etch into the substrate of certain depth, form the first isolated groove, and carry out the filling of isolated groove, then remove the second mask, thus form the first isolation 110, so far, first roughly define the active area of device, in this active area, define the region of the first semiconductor layer, this first semiconductor layer is covered completely by the second semiconductor layer, remove completely so that follow-up and form buried regions under the second semiconductor layer.
Epitaxy technique can form the semiconductor layer of crystal, and it is the higher semiconductor layer of quality, to improve the performance of follow-up formed device.Certainly, can, according to the concrete needs of device, other method be adopted to form the first and second semiconductor layers.
The first semiconductor layer formed in this step roughly defines the scope of the active region forming device, and the region of the second corresponding semiconductor layer on it is active area roughly, is used for forming device architecture.
Then, in step S03, with the second semiconductor layer of the first semiconductor layer for active area forms device architecture 200, shown in figure 6 and Fig. 6 A (AA of Fig. 6 is to schematic cross-section).
Technique traditionally can form device architecture 200, front grid or rear grid technique can be adopted.In the present embodiment, after adopting, grid technique forms device architecture, first, second semiconductor layer 108 is formed gate dielectric layer and pseudo-grid (scheming not shown) and side wall thereof, gate dielectric layer can be thermal oxide layer or other suitable dielectric material, such as silica, silicon nitride etc., in one embodiment, can be silicon dioxide, can be formed by the method for thermal oxidation.Pseudo-grid can be amorphous silicon, polysilicon or silica etc., in one embodiment, can be amorphous silicon.Side wall 114 can have single or multiple lift structure, can by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low k dielectric material and combination thereof, and/or other suitable materials are formed, side wall 114 can be the double-layer structure of silicon nitride and silica in one embodiment.
Then, form source-drain area in pseudo-grid both sides, in one embodiment, on the second semiconductor layer 108, formed the source-drain area 116 of silicon by epi dopant, and form metal silicide layer 118 on source-drain area 116.Certainly, also source-drain area can be formed by ion implantation in the second semiconductor layer.
Then, cover interlayer dielectric layer in pseudo-grid both sides and pass through wet etching, remove pseudo-grid and gate dielectric layer, and again form gate dielectric layer and grid 112, this gate dielectric layer can be high K medium material (such as, compare with silica, there is the material of high-k) or other suitable dielectric materials, high K medium material is hafnium base oxide such as, this grid can be able to be one or more layers structure for metal gate electrode, can comprise metal material or polysilicon or their combination, metal material is Ti, TiAl such as
x, TiN, TaN
x, HfN, TiC
x, TaC
xetc..
Thus define device architecture on the second semiconductor layer, as shown in Figure 6A, the embodiment forming device architecture is herein only example, device architecture required arbitrarily can be formed as required.
Then, in the second semiconductor layer 108 of the first semiconductor layer, form through etched hole 124, shown in figure 7 and Fig. 7 A (AA of Fig. 7 is to schematic cross-section).
After formation device architecture, continue dielectric layer 120 between device upper caldding layer, shown in figure 7A.In the present invention, before the step forming contact hole, first form etched hole 124.In the present embodiment, this etched hole is formed in the second semiconductor layer 108 on the first semiconductor layer 106, through whole second semiconductor layer, so that this through etched hole of later use removes the first semiconductor layer.Concrete, the 3rd mask layer (scheming not shown) is formed on interlayer dielectric layer 120, as photosensitive etching agent, under the covering of the 3rd mask layer, etching interlayer dielectric layer 120, source-drain area 116, second semiconductor layer 108 and the first semiconductor layer 106, also can the substrate 100 of over etching part further, thus formation etched hole 124, and remove the 3rd mask, as shown in Figure 7 A.In other embodiments, when forming etched hole, also can etch from interlayer dielectric layer 120, until expose the first semiconductor layer, namely do not carry out the etching of the first semiconductor layer 106, but remove in the lump in the step of follow-up removal first semiconductor layer formation cavity.
Then, in step S05, by etched hole erosion removal first semiconductor layer, to form cavity 130, with reference to (AA to schematic cross-section, overlook map omitting) figure 8A Suo Shi.
In the present embodiment, wet etching can be adopted to remove the first semiconductor layer, and etching agent can adopt HF, H
2o
2, CH
3cOOH and H
2the mixed solution of O, in one embodiment, adopts HF (49%): H
2o
2(30%): CH
3cOOH (99.8%): H
2the etching agent of O=1:18:27:8, until remove the first all semiconductor layers, thus below device architecture, defines cavity 130 between the second semiconductor layer 108 and substrate 100, as shown in Figure 8 A.
Then, in step S06, filled media material in cavity 130 and etched hole 124, to form buried regions 131 and insulated hole respectively, with reference to (AA to schematic cross-section, overlook map omitting) figure 10A Suo Shi.
In the present embodiment, first, ALD (ald) or CVD (chemical vapour deposition (CVD)) technique can be passed through, carry out the filling of first medium material, this first medium material can be the dielectric material of oxide material or high K medium material or other insulation, when filling up cavity and forming first medium layer 131, the inwall of etched hole 124 also deposits this first medium layer, as shown in Figure 9 A (AA to schematic cross-section, overlook map omitting); Then, etched hole 124 is filled with second medium material, second medium material can be the dielectric materials such as silica, and carry out planarization, until expose interlayer dielectric layer 120, in etched hole, form second dielectric layer 132, thus define buried regions 131 with first medium material cavity filling and define insulated hole with the first and second dielectric materials filling etched holes 124, as shown in Figure 10 A.
In other embodiments, additive method also can be adopted to carry out the filling of cavity, such as, thermal oxidation method can be adopted to be oxidized, make the oxide material of substrate and the second semiconductor layer fill up cavity, then, carry out the filling of etched hole.
Then, in step S07, grid 112 both sides, substrate 100 between the first isolation with buried regions 131 form second of device architecture and isolates 136, shown in reference Figure 13 and Figure 13 A (AA of Figure 13 is to schematic cross-section).
In the present embodiment, concrete, interlayer dielectric layer forms the 4th mask layer 134, as shown in Figure 11 and Figure 11 A (AA of Figure 11 is to schematic cross-section); Etching interlayer dielectric layer 120, metal silicide layer 118, source-drain area 116, second semiconductor layer 108 and the buried regions 131 of part that connects with substrate under the covering of the 4th mask layer 134, to form the second isolated groove 135, as shown in Figure 12 A (AA to schematic cross-section, overlook map omitting); Then, this second isolated groove is filled up with the dielectric material of oxide, as silica etc., and the 4th mask layer 134 is removed, thus form the second isolation 136, as shown in Figure 13 and Figure 13 A (AA of Figure 13 is to schematic cross-section).This second is isolated into the isolation structure being positioned at grid both sides, namely along the area of isolation of the device architecture both sides in grid width direction.
Then, the technique of other necessity can be carried out.
Can conveniently technique, interlayer dielectric layer 120 forms the 5th mask layer (scheming not shown), under the sheltering of the 5th mask layer, carries out the etching etching interlayer dielectric layer, form contact hole (scheming not shown); Then, carry out the filling of metal material, and carry out planarization, until expose interlayer dielectric layer 120, to form source and drain contact 142 and gate contact (scheming not shown), shown in Figure 14 and Figure 14 A (AA of Figure 14 is to schematic cross-section).
To the semiconductor device which form method constructed in accordance.Shown in Figure 14 and Figure 14 A, this semiconductor device comprises: Semiconductor substrate 100; Buried regions 131 in Semiconductor substrate and the second semiconductor layer 108 on it; First isolation 110 of interval second semiconductor layer 108 on substrate; Device architecture 200 on second semiconductor layer 108; Device architecture on grid both sides, substrate between the first isolation 110 and buried regions 131 second isolate 136; Run through the etched hole of the second semiconductor layer 108, be positioned at the both sides of the grid 112 of device architecture, in etched hole, be filled with dielectric material 131,132.
In semiconductor device of the present invention, source and drain contact 142 is formed on the source-drain area 116 with etched hole side.
In an embodiment of the present invention, buried regions 131 is first medium layer, dielectric material in described etched hole 124 comprises the first medium layer 131 on etched hole inwall and fills the second dielectric layer 132 of etched hole, and such as first medium layer can be high K medium material, and second dielectric layer can be silica.
In an embodiment of the present invention, area of isolation is made up of the first isolation and the second isolation, first isolation is formed between the second semiconductor layer, for the isolation of active region, between second isolation is formed in the both sides of grid, buried regions and first isolates, running through the structure of device architecture both sides, is the isolation of device architecture, in the present embodiment, run through interlayer dielectric layer 120, source-drain area 116, second semiconductor layer 104 and first medium layer 131.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. a manufacture method for semiconductor device, is characterized in that, comprises step:
Semiconductor substrate is provided;
Section substrate is formed the first semiconductor layer, substrate and the first semiconductor layer forms the second semiconductor layer, substrate is formed with the first isolation;
With the second semiconductor layer of the first semiconductor layer for active area forms device architecture;
Through etched hole is formed in the second semiconductor layer of the first semiconductor layer;
By etched hole erosion removal first semiconductor layer, to form cavity;
Filled media material in cavity and etched hole, to form buried regions and insulated hole respectively;
Grid both sides, substrate between the first isolation with buried regions form second of device architecture and isolate.
2. manufacture method according to claim 1, is characterized in that, the step forming the first semiconductor layer and the second semiconductor layer specifically comprises:
Substrate is formed the first mask layer, and the substrate of etched portions thickness;
Carry out selective epitaxial growth, form the first semiconductor layer;
Remove the first mask layer;
Carry out epitaxial growth, form the second semiconductor layer;
Etch the second semiconductor layer and substrate, to form the first groove;
Fill the first groove, to form the first isolation.
3. manufacture method according to claim 2, is characterized in that, described substrate is silicon substrate, and described first semiconductor layer is Ge
xsi
1-x, wherein 0<x<1, described second semiconductor layer is silicon.
4. manufacture method according to claim 3, is characterized in that, by etched hole erosion removal first semiconductor layer, specifically comprises with the step forming cavity:
Adopt HF, H
2o
2, CH
3cOOH and H
2the etching agent of O carries out erosion removal first semiconductor layer, to form cavity.
5. manufacture method according to claim 1, is characterized in that, in cavity and etched hole, the step of filled media material specifically comprises:
Adopt ALD technique or CVD technique, fill up first medium layer in the cavities and form first medium layer on the inwall of etched hole; Second dielectric layer is filled up in etched hole.
6. manufacture method according to claim 5, is characterized in that, described first medium layer is high K medium material, and second dielectric layer is silica.
7. manufacture method according to claim 1, is characterized in that, the second step of isolating that grid both sides, substrate between the first isolation with buried regions form device architecture specifically comprises:
Etching first isolation and the buried regions that connects with substrate of the substrate between buried regions and part and on structure, form the second groove;
Carry out the filling of the second groove, to form the second isolation.
8. a semiconductor device, is characterized in that, comprising:
Semiconductor substrate;
Buried regions in Semiconductor substrate and the second semiconductor layer on it;
First isolation of interval second semiconductor layer on substrate;
Device architecture on second semiconductor layer;
Second isolating of device architecture on grid both sides, substrate between the first isolation with buried regions;
Run through the etched hole of the second semiconductor layer, be positioned at the both sides of the grid of device architecture, in etched hole, be filled with dielectric material.
9. semiconductor device according to claim 8, is characterized in that, buried regions is first medium layer, and the dielectric material in described etched hole comprises the first medium layer on etched hole inwall and fills the second dielectric layer of etched hole.
10. semiconductor device according to claim 9, is characterized in that, described first medium layer is high K medium material, and second dielectric layer is silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410480137.1A CN105448992A (en) | 2014-09-18 | 2014-09-18 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410480137.1A CN105448992A (en) | 2014-09-18 | 2014-09-18 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105448992A true CN105448992A (en) | 2016-03-30 |
Family
ID=55558982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410480137.1A Pending CN105448992A (en) | 2014-09-18 | 2014-09-18 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105448992A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006210683A (en) * | 2005-01-28 | 2006-08-10 | Seiko Epson Corp | Semiconductor device and its fabrication process |
| US20060189057A1 (en) * | 2003-05-20 | 2006-08-24 | Stmicroelectronics Sa | Integrated electronic circuit comprising superposed components |
| CN101258590A (en) * | 2005-09-06 | 2008-09-03 | Nxp股份有限公司 | Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method |
-
2014
- 2014-09-18 CN CN201410480137.1A patent/CN105448992A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060189057A1 (en) * | 2003-05-20 | 2006-08-24 | Stmicroelectronics Sa | Integrated electronic circuit comprising superposed components |
| JP2006210683A (en) * | 2005-01-28 | 2006-08-10 | Seiko Epson Corp | Semiconductor device and its fabrication process |
| CN101258590A (en) * | 2005-09-06 | 2008-09-03 | Nxp股份有限公司 | Method of manufacturing a semiconductor device with an isolation region and a device manufactured by the method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9947773B2 (en) | Semiconductor arrangement with substrate isolation | |
| CN108231888A (en) | Semiconductor devices and its manufacturing method | |
| US9117907B2 (en) | Semiconductor device | |
| US20150155353A1 (en) | Borderless contact for ultra-thin body devices | |
| CN105225951A (en) | The formation method of fin formula field effect transistor | |
| CN103165459B (en) | Fin formula field effect transistor and preparation method thereof | |
| US11038039B2 (en) | Method of forming a semiconductor device | |
| CN105225950A (en) | The formation method of fin formula field effect transistor, the formation method of MOS transistor | |
| CN104733311A (en) | Fin-type field effect transistor forming method | |
| CN107481933B (en) | Semiconductor structure and manufacturing method thereof | |
| CN105336624B (en) | The manufacturing method of fin formula field effect transistor and its false grid | |
| CN104425275A (en) | Forming method of semiconductor structure | |
| CN104217948B (en) | Semiconductor making method | |
| CN105702680B (en) | A kind of semiconductor devices and its manufacturing method | |
| KR102463339B1 (en) | How to Make Gap Spacers for N7/N5 FINFETs and Beyond | |
| CN105702618B (en) | A kind of semiconductor devices and its manufacturing method | |
| CN105489647A (en) | Semiconductor device and method for manufacturing same | |
| CN105575804B (en) | Fin formula field effect transistor and its manufacturing method | |
| CN105789050A (en) | Semiconductor device and manufacturing method therefor | |
| CN105448992A (en) | Semiconductor device and manufacturing method thereof | |
| CN105575806A (en) | Fin field-effect transistor and manufacturing method thereof | |
| CN105489491A (en) | Semiconductor device and method for manufacturing same | |
| CN105489650A (en) | Semiconductor device and method for manufacturing same | |
| CN105428303A (en) | Semiconductor device and manufacturing method thereof | |
| CN105489477A (en) | Semiconductor device and manufacturing method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160330 |
|
| RJ01 | Rejection of invention patent application after publication |