CN105448821A - Preparation method for obtaining large-area ferroelectric film transistor array - Google Patents
Preparation method for obtaining large-area ferroelectric film transistor array Download PDFInfo
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- CN105448821A CN105448821A CN201510332231.7A CN201510332231A CN105448821A CN 105448821 A CN105448821 A CN 105448821A CN 201510332231 A CN201510332231 A CN 201510332231A CN 105448821 A CN105448821 A CN 105448821A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000005516 engineering process Methods 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 239000010409 thin film Substances 0.000 claims description 86
- 238000010606 normalization Methods 0.000 claims description 14
- 229910002367 SrTiO Inorganic materials 0.000 claims description 10
- 229910004121 SrRuO Inorganic materials 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 7
- 241000877463 Lanio Species 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 230000003064 anti-oxidating effect Effects 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000002474 experimental method Methods 0.000 abstract description 4
- 238000012360 testing method Methods 0.000 abstract description 2
- 238000005240 physical vapour deposition Methods 0.000 abstract 2
- 238000003491 array Methods 0.000 description 19
- 239000000463 material Substances 0.000 description 11
- 238000009826 distribution Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 239000013049 sediment Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 229910001055 inconels 600 Inorganic materials 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a preparation method for obtaining a large-area ferroelectric film transistor array. The method mainly comprises the following steps of: (1) placing a small-area substrate on a hollow grid substrate position of a large-area substrate frame; (2) arranging a silicon wafer baffle plate identical with the substrate frame in size on the back side of the substrate; (3) utilizing a physical vapor deposition method to successively prepare a ferroelectric film insulating layer and an oxide semiconductor film channel layer on the substrate; (4) utilizing the physical vapor deposition method and a mask technology to prepare a source electrode and a drain electrode on the channel layer, and forming the large-area ferroelectric film transistor array; and (5) testing the performance of the large-area ferroelectric film transistor array, optimizing the technology parameters in the preparation process of the large-area ferroelectric film transistor array according to the consistency between the transistor unit performance and the array performance, and obtaining the large-area ferroelectric film transistor array meeting the performance requirements and having good consistency and the preparation technology thereof. The method is simple and easy, high in efficiency and low in experiment cost.
Description
Technical field
The present invention relates to the research method of large area ferroelectrical thin film transistor array, especially relate to the research method for liquid crystal display and the large-area transistors array for high density nonvolatile memory.
Background technology
Ferroelectrical thin film transistor utilizes ferroelectric thin-flim materials to substitute a kind of novel TFT of traditional insulating layer material as gate medium.Because ferroelectric thin film has non-volatile characteristic, therefore ferroelectrical thin film transistor not only can be used as switching device and is applied to liquid crystal display, also can be used as logical block and is applied to nonvolatile memory.Ferroelectrical thin film transistor has the advantage such as NDRW non-destructive read write and super fast response, is the very promising Novel electronic devices of one.Along with the progress of semicon industry, more and more higher to the requirement of electronic device integrated level, also need constantly to save raw materials for production, control cost and raise the efficiency, therefore required chip area also increases thereupon simultaneously.Obviously, the large area array technology of preparing of ferroelectrical thin film transistor becomes the key determining its future development, and it will directly decide the reliability and stability of product.Obtain performance to meet the demands and the good large area ferroelectrical thin film transistor array of consistency and technology of preparing thereof, first need to carry out great many of experiments prepared by ferroelectrical thin film transistor array on large area substrates and grope and optimize.Electrode is the important component part of ferroelectrical thin film transistor.Current electronic device electrode preparation means mainly contains two kinds, and one is mask lithography means, and another kind is mask sputtering means.In the preparation process of ferroelectrical thin film transistor array electrode, cause the photoetching process of current ferroelectric thin film still immature because ferroelectric material element is more, be applied to ferro-electric device preparation and also there is certain difficulty; And utilize mask lithography means to prepare the complex procedures of electrode, cost is high.The method of the mask Slag coating electrode that technique is relatively simple and cost is low, compares in the experiment being suitable for use in small size ferroelectric thin film and device, easily causes unit crosstalk phenomenon when being applied in large area ferroelectric thin film and device.On the other hand, the large area substrates for the preparation of large area ferroelectric thin film and device thereof is usual costly, and ferroelectric thin film and the main dependence on import of device substrate thereof that diameter is greater than 5 inches, causes experimental cost very high.Ferroelectrical thin film transistor array area is larger, and the problems referred to above are more outstanding.Therefore, need to develop a kind of simple, efficiency is high, experimental cost is low method especially and to obtain large area ferroelectrical thin film transistor array preparation, and then instruct the preparation of large area ferroelectrical thin film transistor array device.
Summary of the invention
The present invention is directed to Problems existing in the research of existing large area ferroelectrical thin film transistor array, a kind of method of simple, efficiency is high, experimental cost is low acquisition large area ferroelectrical thin film transistor array preparation is provided.
Concrete technical scheme.
Obtain a method for large area ferroelectrical thin film transistor array preparation, described the method comprises the following steps: small size substrate is placed on the hollow out grid substrate position of large area substrates frame by (1); (2) substrate back place one piece with the silicon wafer baffle plate of substrate frame same size; (3) adopt physical gas-phase deposite method on substrate, prepare ferroelectric thin film insulating barrier and oxide semiconductor thin-film channel layer successively; (4) adopt physical gas-phase deposite method on channel layer, to prepare source electrode and drain electrode in conjunction with mask technique, form large area ferroelectrical thin film transistor array; (5) performance of large area ferroelectrical thin film transistor array is tested, according to the consistency of transistor unit performance and array performance, optimize the technological parameter in large area ferroelectrical thin film transistor array preparation process, obtain performance and meet the demands and the good ferroelectrical thin film transistor array of consistency and preparation technology thereof.
Described large area substrates frame profile is circular, and its diameter is 2 inches ~ 8 inches.Substrate frame material is the alloy of high temperature resistant anti-oxidation, under 500 DEG C ~ 1000 DEG C hot environments, deformation and oxidation does not occur.Have m (1≤m≤22) to go in substrate frame,
n(1≤
n≤ 22) row hollow out grid substrate position, it is of a size of 5 ~ 10mm × 5 ~ 10mm.
Described small size substrate material is Pt/Ti/SiO
2/ Si or heavily doped Si or LaAlO
3or LaNiO
3/ SrTiO
3or SrRuO
3/ SrTiO
3in one, there is good conductivity.
Described ferroelectric thin film insulating layer material is Bi
4ti
3o
12, SrBi
2ta
2o
9, PbTiO
3, BaTiO
3or BiFeO
3in one, or be in La, Nd, Ce, Sr, Zr, Mn, W, Na one or more doping above-mentioned ferroelectric thin films in any one.
Described oxide semiconductor thin-film channel layer materials is ZnO, SnO
2or In
2o
3in one, or to adulterate any one in above-mentioned semiconductive thin film for one or more of Al, Li, Sn, Sb, Ga.
Described source electrode and drain material are Pt, Au, Cu, Ag, Ir or Ti metal level, or are two or more complex metal layer formed in above metal, or are LaNiO
3, SrRuO
3or IrO
2in any one.
Described performance meets the demands and refers to that each cell threshold voltage of transistor array is all less than 2.5V, and channel mobility is all greater than 1.5cm
2/ Vs, memory window value is all greater than 3.5V, and current on/off ratio is all greater than 10
3.
Described consistency refers to that well the normalization numerical bias of the performance parameters such as each cell threshold voltage of transistor array, channel mobility, memory window, current on/off ratio is within ± 10%.
Beneficial effect of the present invention.
The present invention adopts the large area substrates frame of many substrates position, by some small size substrate combination, prepares large area ferroelectrical thin film transistor array in conjunction with physical vaporous deposition and mask technique.On the one hand, do not need to carry out photoetching treatment to sample, reduce experiment difficulty; On the other hand, avoid large area mask and sputter the unit cross-interference issue caused.Meanwhile, this technical scheme does not need directly to use expensive large area ferroelectric thin film and device substrate thereof, has saved experimental cost.In addition, this cover technical scheme is simple, efficiency is high.
Accompanying drawing explanation
Fig. 1 is large area substrates frame of the present invention.
Fig. 2 is embodiment 1, the distribution mode schematic diagram of embodiment 3 small areas substrate on large area substrates frame.
Fig. 3 is the output characteristic curve of ferroelectrical thin film transistor unit in embodiment 1.
Fig. 4 is the transfer characteristic curve of ferroelectrical thin film transistor unit in embodiment 1.
Fig. 5 is Pt/Ti/SiO in embodiment 1
2the normalized threshold voltage of/Si base 5 inches of large area ferroelectrical thin film transistor arrays.
Fig. 6 is Pt/Ti/SiO in embodiment 1
2the normalization channel mobility of/Si base 5 inches of large area ferroelectrical thin film transistor arrays.Fig. 7 is Pt/Ti/SiO in embodiment 1
2the normalization memory window of/Si base 5 inches of large area ferroelectrical thin film transistor arrays.
Fig. 8 is Pt/Ti/SiO in embodiment 1
2the normallized current on-off ratio of/Si base 5 inches of large area ferroelectrical thin film transistor arrays.
Fig. 9 is the distribution mode schematic diagram of embodiment 2 small areas substrate on large area substrates frame.
Figure 10 is Pt/Ti/SiO in embodiment 2
2the normalized threshold voltage of/Si base 2 inches of large area ferroelectrical thin film transistor arrays.
Figure 11 is Pt/Ti/SiO in embodiment 2
2the normalization channel mobility of/Si base 2 inches of large area ferroelectrical thin film transistor arrays.
Figure 12 is Pt/Ti/SiO in embodiment 2
2the normalization memory window of/Si base 2 inches of large area ferroelectrical thin film transistor arrays.
Figure 13 is Pt/Ti/SiO in embodiment 2
2the normallized current on-off ratio of/Si base 2 inches of large area ferroelectrical thin film transistor arrays.
Figure 14 is SrRuO in embodiment 3
3/ SrTiO
3the normalized threshold voltage of base 5 inches of large area ferroelectrical thin film transistor arrays.
Figure 15 is SrRuO in embodiment 3
3/ SrTiO
3the normalization channel mobility of base 5 inches of large area ferroelectrical thin film transistor arrays.
Figure 16 is SrRuO in embodiment 3
3/ SrTiO
3the normalization memory window of base 5 inches of large area ferroelectrical thin film transistor arrays.
Figure 17 is SrRuO in embodiment 3
3/ SrTiO
3the normallized current on-off ratio of base 5 inches of large area ferroelectrical thin film transistor arrays.
Embodiment
Following examples are intended to the present invention is described, instead of limitation of the invention further.
Embodiment 1
The present embodiment is at Pt/Ti/SiO
25 inches of large area ZnO/Bi prepared by/Si substrate
3.15nd
0.85ti
3o
12ferroelectrical thin film transistor array.
First, 6 are of a size of the small size Pt/Ti/SiO of 10mm × 10mm
2/ Si substrate is positioned in 5 inches of large area substrates framves according to the distribution situation shown in Fig. 2, places silicon wafer baffle plate at the substrate frame back side.Large area substrates frame material used is Inconel600 nickel-base alloy, and main component is 73Ni-15Cr-Ti, Al.Then, large area Bi is prepared successively by scan-type pulse laser sediment method
3.15nd
0.85ti
3o
12ferroelectric thin film insulating barrier and large area ZnO semiconductive thin-film channel layer, the target used is 6 inches of large area Bi
3.15nd
0.85ti
3o
12target and 6 inches of large area ZnO targets.Prepare Pt source electrode and drain electrode in conjunction with sputtering method and mask technique again, form 5 inches of large area ferroelectrical thin film transistor arrays.Finally, by testing the performance of large area ferroelectrical thin film transistor array, according to the consistency of transistor unit performance and array performance, Optimizing Process Parameters, obtain performance to meet the demands and the good 5 inches of large area ferroelectrical thin film transistor arrays of consistency, its performance and consistency result thereof are as shown in figures 3-8.Fig. 3 and Fig. 4 is respectively output characteristic curve and the transfer characteristic curve of transistor unit, and present N-shaped enhancement transistor characteristic by the known prepared transistor unit of result in figure, threshold voltage is 1.5V, and channel mobility is 2.4cm
2/ Vs, memory window is 3.9V, and current on/off ratio is 1.2 × 10
5.Fig. 5, Fig. 6, Fig. 7 and Fig. 8 are respectively zones of different ferroelectrical thin film transistor cell threshold voltage, channel mobility, memory window and current on/off ratio normalized curve, the normalized threshold voltage deviation of gained 5 inches of large area ferroelectrical thin film transistor arrays within ± 5%, normalization channel mobility deviation within ± 10%, normalization memory window deviation within ± 10%, normallized current on-off ratio deviation is within ± 8%.The preparation technology that this large area ferroelectrical thin film transistor array is corresponding is as follows: the preparation technology parameter of (1) 5 inch of large area BNT film is: laser energy 420mJ, laser repetition rate 10Hz, oxygen pressure 200mTorr, underlayer temperature 800 DEG C, laser are at target center 5 inch section sweep speed 0.313mm/s, marginal portion sweep speed 62.5mm/s; The preparation technology parameter of (2) 5 inches of large area ZnO films is: laser energy 400mJ, laser repetition rate 10Hz, oxygen pressure 8mTorr, underlayer temperature 500 DEG C, laser are at target center 5 inch section sweep speed 0.313mm/s, marginal portion sweep speed 62.5mm/s; (3) source-drain electrode breadth length ratio is W:L=1500 μm: 200 μm.
Embodiment 2
The present embodiment is at Pt/Ti/SiO
22 inches of large area ZnO/Bi prepared by/Si substrate
3.15nd
0.85ti
3o
12ferroelectrical thin film transistor array.
4 are of a size of the small size Pt/Ti/SiO of 10mm × 10mm
2/ Si substrate is positioned in 5 inches of large area substrates framves according to the distribution situation shown in Fig. 9, and place silicon wafer baffle plate at the substrate frame back side, large area substrates frame material used is with embodiment 1.Then, large area Bi is prepared successively by scan-type pulse laser sediment method
3.15nd
0.85ti
3o
12ferroelectric thin film insulating barrier and large area ZnO semiconductive thin-film channel layer, the target used is 3 inches of large area Bi
3.15nd
0.85ti
3o
12target and 3 inches of large area ZnO targets.Based on the preparation technology that embodiment 1 obtains, preparation parameter is slightly made improvements, prepare large area Bi respectively
3.15nd
0.85ti
3o
12ferroelectric thin film insulating barrier, large area ZnO semiconductive thin-film channel layer, Pt source electrode and drain electrode, forming property meets the demands and the good 2 inches of large area ferroelectrical thin film transistor arrays of consistency.Transistor unit threshold voltage is 1.2V, and channel mobility is 2.6cm
2/ Vs, memory window is 4V, and current on/off ratio is 1.8 × 10
5.Figure 10, Figure 11, Figure 12 and Figure 13 are respectively zones of different ferroelectrical thin film transistor cell threshold voltage, channel mobility, memory window, current on/off ratio normalized curve, the normalized threshold voltage deviation of gained 2 inches of large area ferroelectrical thin film transistor arrays within ± 5%, normalization channel mobility deviation within ± 5%, normalization memory window deviation within ± 5%, normallized current on-off ratio deviation is within ± 5%.
Embodiment 3
The present embodiment is at SrRuO
3/ SrTiO
35 inches of large area ZnO/Bi prepared by substrate
3.15nd
0.85ti
3o
12ferroelectrical thin film transistor array.
6 are of a size of the small size SrRuO of 10mm × 10mm
3/ SrTiO
3substrate is positioned in 5 inches of large area substrates framves according to distribution situation shown in Fig. 2, places silicon wafer baffle plate at the substrate frame back side.Large area substrates frame material used is with embodiment 1.Then, large area Bi is prepared successively by scan-type pulse laser sediment method
3.15nd
0.85ti
3o
12ferroelectric thin film insulating barrier and large area ZnO semiconductive thin-film channel layer, the target used is 6 inches of large area Bi
3.15nd
0.85ti
3o
12target and 6 inches of large area ZnO targets.Based on the preparation technology that embodiment 1 obtains, preparation parameter is slightly made improvements, prepare large area Bi respectively
3.15nd
0.85ti
3o
12ferroelectric thin film insulating barrier, large area ZnO semiconductive thin-film channel layer, Pt source electrode and drain electrode, forming property meets the demands and the good 5 inches of large area ferroelectrical thin film transistor arrays of consistency.Transistor unit threshold voltage is 1V, and channel mobility is 3.5cm
2/ Vs, memory window is 4.2V, and current on/off ratio is 2.6 × 10
5.Figure 14, Figure 15, Figure 16 and Figure 17 are respectively zones of different ferroelectrical thin film transistor cell threshold voltage, channel mobility, memory window, current on/off ratio normalized curve, the normalized threshold voltage deviation of gained 5 inches of large area ferroelectrical thin film transistor arrays within ± 4%, normalization channel mobility deviation within ± 7%, normalization memory window deviation within ± 9%, normallized current on-off ratio deviation is within ± 9%.
Claims (7)
1. obtain a method for large area ferroelectrical thin film transistor array preparation, it is characterized in that, comprise following steps: small size substrate is placed on the hollow out grid substrate position of large area substrates frame by (1); (2) substrate back place one piece with the silicon wafer baffle plate of substrate frame same size; (3) adopt physical gas-phase deposite method on substrate, prepare ferroelectric thin film insulating barrier and oxide semiconductor thin-film channel layer successively; (4) adopt physical gas-phase deposite method on channel layer, to prepare source electrode and drain electrode in conjunction with mask technique, form large area ferroelectrical thin film transistor array; (5) performance of large area ferroelectrical thin film transistor array is tested, according to the consistency of transistor unit performance and array performance, optimize the technological parameter in large area ferroelectrical thin film transistor array preparation process, obtain performance and meet the demands and the good large area ferroelectrical thin film transistor array of consistency and preparation technology thereof.
2. the method for acquisition large area ferroelectrical thin film transistor array preparation according to claim 1, is characterized in that, the large area substrates frame profile described in step (1) is circular, and its diameter is 2 inches ~ 8 inches.
3. the method for acquisition large area ferroelectrical thin film transistor array preparation according to claim 1, it is characterized in that, large area substrates frame described in step (1) uses the alloy material of high temperature resistant anti-oxidation, under 500 DEG C ~ 1000 DEG C hot environments, deformation and oxidation does not occur.
4. the method for acquisition large area ferroelectrical thin film transistor array preparation according to claim 1, is characterized in that, in the large area substrates frame described in step (1), have m (1≤m≤22) to go,
n(1≤
n≤ 22) row hollow out grid substrate position, it is of a size of 5 ~ 10mm × 5 ~ 10mm.
5. the method for acquisition large area ferroelectrical thin film transistor array preparation according to claim 1, it is characterized in that, the small size substrate described in step (1) is the Pt/Ti/SiO with satisfactory electrical conductivity
2/ Si or heavy doping Si or LaAlO
3or LaNiO
3/ SrTiO
3or SrRuO
3/ SrTiO
3.
6. the method for acquisition large area ferroelectrical thin film transistor array preparation according to claim 1, it is characterized in that, the performance described in step (5) meet the demands refer to each unit of transistor array threshold voltage is all less than 2.5V, channel mobility is all greater than 1.5cm
2/ Vs, memory window value is all greater than 3.5V, current on/off ratio is all greater than 10
3.
7. the method for acquisition large area ferroelectrical thin film transistor array preparation according to claim 1, it is characterized in that, the consistency described in step (5) refers to that well the normalization numerical bias of the threshold voltage of each unit of transistor array, channel mobility, memory window, current on/off ratio is within ± 10%.
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|---|---|---|---|
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130014896A1 (en) * | 2011-07-15 | 2013-01-17 | Asm Japan K.K. | Wafer-Supporting Device and Method for Producing Same |
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|---|---|---|---|---|
| US20130014896A1 (en) * | 2011-07-15 | 2013-01-17 | Asm Japan K.K. | Wafer-Supporting Device and Method for Producing Same |
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| Title |
|---|
| 丁涛: "ZnO/BNT/LNO/Si铁电薄膜晶体管的制备及表征", 《中国优秀硕士学位论文全文数据库（电子期刊）信息科技辑》 * |
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