CN103996718A - Silicon-based ferroelectric grid thin film transistor and preparation method thereof - Google Patents
Silicon-based ferroelectric grid thin film transistor and preparation method thereof Download PDFInfo
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- CN103996718A CN103996718A CN201410246523.4A CN201410246523A CN103996718A CN 103996718 A CN103996718 A CN 103996718A CN 201410246523 A CN201410246523 A CN 201410246523A CN 103996718 A CN103996718 A CN 103996718A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 44
- 239000010703 silicon Substances 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title claims abstract description 33
- 239000010409 thin film Substances 0.000 title abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 5
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 86
- 239000010408 film Substances 0.000 claims description 56
- 230000004888 barrier function Effects 0.000 claims description 31
- 241000877463 Lanio Species 0.000 claims description 19
- 235000014692 zinc oxide Nutrition 0.000 claims description 16
- 238000005520 cutting process Methods 0.000 claims description 14
- 229910004121 SrRuO Inorganic materials 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 8
- 238000004549 pulsed laser deposition Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 229910019606 La0.5Sr0.5CoO3 Inorganic materials 0.000 claims description 5
- 229910003369 La0.67Sr0.33MnO3 Inorganic materials 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910006404 SnO 2 Inorganic materials 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 229910003410 La0.7Ca0.3MnO3 Inorganic materials 0.000 claims description 2
- 229910052779 Neodymium Inorganic materials 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 229910052746 lanthanum Inorganic materials 0.000 claims description 2
- 229910052748 manganese Inorganic materials 0.000 claims description 2
- 239000002905 metal composite material Substances 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 229910052708 sodium Inorganic materials 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 10
- 238000003860 storage Methods 0.000 abstract description 3
- 230000005855 radiation Effects 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 24
- 229910052760 oxygen Inorganic materials 0.000 description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 17
- 239000001301 oxygen Substances 0.000 description 17
- 230000000052 comparative effect Effects 0.000 description 13
- 230000010287 polarization Effects 0.000 description 9
- 230000008021 deposition Effects 0.000 description 8
- 238000009434 installation Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000013077 target material Substances 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000002441 X-ray diffraction Methods 0.000 description 3
- 230000005260 alpha ray Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 210000004877 mucosa Anatomy 0.000 description 2
- 230000010415 tropism Effects 0.000 description 2
- 241000931526 Acer campestre Species 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 230000005621 ferroelectricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000028161 membrane depolarization Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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Abstract
The invention discloses a silicon-based ferroelectric grid thin film transistor and a preparation method thereof. A beveled mono-crystalline silicon substrate (1) serves as the bottom layer of the transistor, a perovskite conductive oxide bottom grid electrode (2), a ferroelectric insulating layer (3) and an oxide semiconductor active layer (4) are sequentially formed on the middle layer from bottom to top and a transistor source electrode (5) and a drain electrode (6) are arranged on the top layer of the transistor, wherein the beveled mono-crystalline silicon substrate (1) is intrinsic silicon with a step in the size of that of an atom. The ferroelectric grid thin film transistor is a non-volatile storage device, has the advantages of high radiation resistance, high reading and writing speed, low power consumption and the like of a ferroelectric random access memory, and further has the advantages that the starting voltage is low, the switch ratio is high, the device structure is simple, the preparation technology is simpler, low in cost and prone to being compatible with an existing silicon technology, and an all-epitaxial structure can be realized.
Description
Technical field
The invention belongs to microelectronic industry nonvolatile memory technical field, be specially a kind of silicon-based ferroelectric gate thin-film transistors and preparation method thereof.
Background technology
The advantages such as that ferroelectric memory has is non-volatile, low-power consumption, high read or write speed, high storage density, strong radioresistance, have boundless application prospect in electronic information and national defence field.Current business-like ferroelectric random memory is mainly the 1T1C structural iron electrical storage based on ferroelectric capacitor, and this memory has the problems such as destructiveness is read, cell size is large, integrated level is low.
Ferroelectric gate thin-film transistors is to adopt ferroelectric layer to substitute insulating barrier in general thin transistor (as SiO
2, HfO
2) and the non-volatile ferroelectric memory of 1T structure that is prepared into.Thin-film transistor can be divided into bottom gate and two kinds of structures of top grid according to the difference of gate electrode position, and bottom grating structure is subject to people's favor because preparation technology is more simple.The ferroelectric gate thin-film transistors of bottom grating structure is compared with commercial ferroelectric random memory, there is non-Destructive readout, the advantage that cellular construction and preparation technology are more simple, good, the easy large area of interfacial characteristics of ferroelectric thin film layer and oxide semiconductor active layer is integrated, can realize full epitaxial structure.
The performance of ferroelectric gate thin-film transistors depends on the quality of ferroelectric insulating barrier performance.Yet ferroelectric has the anisotropy of height, thereby make its ferroelectricity, dielectricity and piezoelectricity etc. strongly depend on the oriented growth of film crystal.As Bi
4ti
3o
12along a direction of principal axis, there are 50 μ C/cm
2polarization value, and only have 4 μ C/cm along the polarization value of c-axis direction
2; In addition, a axle Bi
4ti
3o
12the dielectric constant of film will be much larger than c-axis film.Conventionally at the upper Bi growing of metal electrode (as Pt electrode)
4ti
3o
12ferroelectric thin film is easily along the growth of c-axis or random orientation, and its dielectric constant and polarization value are less, causes that transistorized cut-in voltage is large, on-off ratio is little, is unfavorable for the application of ferroelectric gate thin-film transistors.
In order to obtain good performance, the ferroelectric thin film layer in current ferroelectric gate thin-film transistors is generally (as SrTiO in special monocrystalline oxide substrate
3) upper epitaxial growth and obtaining.But these special oxide monocrystal substrates are not only expensive, and with current main flow integrated circuit technology be that silicon technology is incompatible.Obviously, expensive substrate and can limit the application and development of the ferroelectric gate thin-film transistors of this class with the incompatibility of current ripe silicon technology.
Summary of the invention
The present invention is directed to the problem that existing ferroelectric gate thin-film transistors exists, provide that a kind of cut-in voltage is low, on-off ratio is large, the simple silicon-based ferroelectric gate thin-film transistors of device architecture.
Another object of the present invention is to provide that a kind of preparation process is simple, cost is low, be easy to the preparation method of the silicon-based ferroelectric gate thin-film transistors of suitability for industrialized production.
Concrete technical scheme is:
A kind of silicon-based ferroelectric gate thin-film transistors, this transistor bottom is the monocrystalline substrate 1 of cutting sth. askew, intermediate layer is followed successively by perovskite conductive oxide bottom gate thin film 2, ferroelectric insulating barrier 3 and oxide semiconductor active layer 4 from top to bottom, and top layer is transistor source 5 and drain electrode 6; Wherein, the monocrystalline substrate of cutting sth. askew described in 1 is for having the intrinsic silicon of atomic size step.
Inventor considers that the excessive backward step width of angle is narrow, so cut sth. askew described in the preferably scope of mis-cut angle θ of silicon substrate 1 of inventor is 0 ° of < θ≤20 °.
The mis-cut angle θ of the described silicon substrate 1 of cutting sth. askew is more preferably 3 °≤θ≤10 °.
By mis-cut angle being controlled to the width of the monocrystalline silicon step of can further guaranteeing in above-mentioned scope to cut sth. askew, make to be applicable on it growth perovskite conductive oxide bottom gate thin film.
At the bottom of changing the angle of chamfer of substrate, height and width that can Effective Regulation step.
Described perovskite conductive oxide bottom gate thin film 2 is LaNiO
3, SrRuO
3, La
0.7ca
0.3mnO
3, La
0.67sr
0.33mnO
3or La
0.5sr
0.5coO
3film.
Described ferroelectric insulating barrier (3) material is Bi
4ti
3o
12, SrBi
2ta
2o
9, PbTiO
3, BaTiO
3or BiFeO
3, or be one or several doping Bi of La, Nd, Ce, Sr, Zr, Mn, W, Na
4ti
3o
12, SrBi
2ta
2o
9, PbTiO
3, BaTiO
3or BiFeO
3in any one.
Described oxide semiconductor active layer 4 is ZnO, SnO
2or In
2o
3in any one, or be Al, Li, Sn, Sb, one or several doping ZnOs of Ga, SnO
2, In
2o
3in any one.
Described source electrode 5 and drain electrode 6 are Pt, Au, Ag, Ir or Ti metal level, or are two or more the formed metal composite layer in above metal, or are LaNiO
3, SrRuO
3, IrO
2any one in metal oxide.
Described perovskite conductive oxide bottom gate thin film 2 thickness are 10～200nm;
Described ferroelectric insulating barrier 3 thickness are 50～600nm;
Described oxide semiconductor active layer 4 thickness are 10～100nm;
Described source electrode 5 and drain electrode 6 thickness are respectively 10～200nm.
The preparation method of the silicon-based ferroelectric gate thin-film transistors described in the present invention also provides, concrete preparation process is: [1] cleans the monocrystalline silicon substrate of cutting sth. askew, to be used as substrate; [2] the perovskite conductive oxide bottom gate thin film of growing in the monocrystalline substrate of cutting sth. askew; [3] the ferroelectric insulating barrier of growing in perovskite conductive oxide bottom gate thin film; [4] grow oxide semiconductor active layer on ferroelectric insulating barrier; [5] source electrode of grown transistor and drain electrode on oxide semiconductor active layer.
Grow by pulsed laser deposition or magnetron sputtering method in described step [2] and [3].
Described step [2] is specially: by controlling sedimentary condition and the cut sth. askew orientation of silicon substrate and crystal orientation and the lattice constant that angle regulates and controls perovskite conductive oxide film, the perovskite conductive oxide film of the oriented growth of gained is as the template layer of transistorized bottom gate thin film layer and the ferroelectric insulating barrier of growth.
Described step [3] is specially: by perovskite conductive oxide gate electrode 2 as the grow ferroelectric insulating barrier of specific preferred orientation of template layer.
Beneficial effect of the present invention
Ferroelectric gate thin-film transistors of the present invention using cut sth. askew monocrystalline intrinsic silicon as substrate, perovskite conductive oxide film as bottom electrode layer, ferroelectric thin film as insulating barrier, oxide semiconductor thin-film as active layer.By the preferred orientation of selecting the acting in conjunction of cut sth. askew silicon substrate and the perovskite conductive oxide film electrode with atomic steps to regulate and control ferroelectric thin film, grow; First there is the perovskite conductive oxide film electrode of preparing high orientation on the silicon substrate of cutting sth. askew of atomic steps, then take the perovskite oxide film of high orientation and as template layer prepares, there is the ferroelectric insulating barrier of specific preferred orientation.Compare with other ferroelectric thin film, ferroelectric insulating barrier of the present invention has larger residual polarization and dielectric constant, thereby make ferroelectric gate thin-film transistors have large on-off ratio, lower cut-in voltage, this is very beneficial for improving the service behaviour of ferroelectric gate thin-film transistors, and reduces power consumption; In addition, what the substrate of ferroelectric gate thin-film transistors of the present invention adopted is the monocrystalline intrinsic silicon substrate of cutting sth. askew, and does not need to be doping to P type silicon or N-type silicon, is easy to existing silicon technology is compatible, cost is low, be easy to suitability for industrialized production; And ferroelectric gate thin-film transistors of the present invention is to adopt bottom gate thin film transistor structure, and device architecture and preparation technology are simpler, do not need to introduce buffer insulation layer, and depolarization problem is little, and can realize full epitaxial structure.
Accompanying drawing explanation
Fig. 1 is the structural representation of silicon-based ferroelectric gate thin-film transistors of the present invention;
Fig. 2 is the step-like substrate surface 50 * 50nm that cuts sth. askew
2aFM shape appearance figure;
Fig. 3 is Bi in the prepared silicon-based ferroelectric gate thin-film transistors of embodiment 1 and comparative example 1,2
3.15nd
0.85ti
3o
12the XRD collection of illustrative plates comparison diagram of ferroelectric thin film layer;
As can be seen from the figure, the prepared Bi of comparative example 1
3.15nd
0.85ti
3o
12ferroelectric thin film layer is mainly grown along c-axis; Bi in comparative example 2
3.15nd
0.85ti
3o
12the growth of ferroelectric thin film random orientation; And the prepared Bi of embodiment 1
3.15nd
0.85ti
3o
12ferroelectric thin film layer is main along (200) oriented growth, has an obvious a axle preferrel orientation.
Fig. 4 is Bi in the prepared silicon-based ferroelectric gate thin-film transistors of embodiment 1 and comparative example 1,2
3.15nd
0.85ti
3o
12the electric hysteresis loop comparison diagram of ferroelectric thin film layer;
As can be seen from the figure, the prepared Bi of embodiment 1
3.15nd
0.85ti
3o
12ferroelectric thin film layer is than comparative example 1 and the prepared Bi of comparative example 2
3.15nd
0.85ti
3o
12ferroelectric thin film layer has larger polarization value, and this is mainly because Bi
3.15nd
0.85ti
3o
12polarization mainly along a direction of principal axis, and the prepared Bi of embodiment 1
3.15nd
0.85ti
3o
12ferroelectric thin film layer has an obvious a axle preferrel orientation.
Fig. 5 be embodiment 1 and comparative example 1,2 prepared silicon-based ferroelectric gate thin-film transistors in Bi
3.15nd
0.85ti
3o
12the dielectric spectral contrast figure of ferroelectric thin film layer;
As can be seen from the figure, the prepared Bi of embodiment 1
3.15nd
0.85ti
3o
12the dielectric constant of ferroelectric thin film layer will obviously be greater than comparative example 1 and the prepared Bi of comparative example 2
3.15nd
0.85ti
3o
12ferroelectric thin film layer.
Fig. 6 is the output characteristic curve of the prepared silicon-based ferroelectric gate thin-film transistors of embodiment 1;
As can be seen from the figure, the silicon-based ferroelectric gate thin-film transistors of embodiment 1 preparation presents typical N type enhancement transistor characteristic.
Fig. 7 is linear transfer characteristic curve and the matched curve thereof of the prepared silicon-based ferroelectric gate thin-film transistors of embodiment 1.
As can be seen from the figure, the cut-in voltage of the silicon-based ferroelectric gate thin-film transistors of embodiment 1 preparation is little, is 1.1V.
Fig. 8 is the logarithm transfer characteristic curve of the prepared silicon-based ferroelectric gate thin-film transistors of embodiment 1.
As can be seen from the figure, the current on/off ratio of the silicon-based ferroelectric gate thin-film transistors of embodiment 1 preparation is large, reaches 1.8 * 10
6.
Embodiment
Following instance is intended to illustrate the present invention, rather than limitation of the invention further.
Embodiment 1
The present embodiment be adopt pulsed laser deposition at [100] direction mis-cut angle θ, be on Si (100) substrate of 6 ° preparation with LaNiO
3film is as bottom gate thin film, Bi
3.15nd
0.85ti
3o
12ferroelectric thin film is the ferroelectric gate thin-film transistors as active layer as insulating barrier, ZnO film, comprises the following steps:
(1) installation of substrate and target
In vacuum chamber, by LaNiO
3, Bi
3.15nd
0.85ti
3o
12be installed on many targets frame with ZnO target, after the Si substrate of cutting sth. askew cleans up, be arranged on substrate holder, make the direction of laser beam aim at LaNiO
3target, regulates the distance of substrate and target to 87mm.
(2) vacuumize
Open successively mechanical pump and molecular pump, the pressure in vacuum chamber is evacuated to 5 * 10
-8torr.
(3) laser coating
Open KrF excimer laser (optical maser wavelength is 248nm), adjust the single pulse energy of laser to 320mJ, the energy density that makes single laser pulse is 2J/cm
2, laser repetition rate is 10Hz; In vacuum chamber, pass into oxygen again, oxygen pressure is fixed on 200mTorr, opens lining heat, and substrate is warmed up to 600 ℃; By the laser beam irradiation LaNiO of laser transmitting
3on target, start plated film on substrate; After plated film 20min, obtain the LaNiO of height (110) orientation
3conductive film, its thickness is 50nm; After treating that afterwards sample is cooled to room temperature, at LaNiO
3mask film covering plate on film, to reserve bottom gate thin film, and by Bi
3.15nd
0.85ti
3o
12target forwards the target position of Ear Mucosa Treated by He Ne Laser Irradiation to, and underlayer temperature is warmed up to after 700 ℃, at LaNiO
3on conductive film, carry out Bi
3.15nd
0.85ti
3o
12the deposition of ferroelectric thin film layer; After plated film 60min, obtain having the Bi of a axle preferrel orientation
3.15nd
0.85ti
3o
12ferroelectric thin film layer, its thickness is 550nm; Finally ZnO target is forwarded to the target position of Ear Mucosa Treated by He Ne Laser Irradiation, and underlayer temperature and oxygen are pressed and dropped to respectively 400 ℃ and 10mTorr at Bi
3.15nd
0.85ti
3o
12on ferroelectric layer, deposit ZnO semiconductor active layer, the plated film time is 10min, and its thickness is 60nm; Close successively laser, oxygen valve, substrate heating controller, molecular pump and mechanical pump, after sample is cooled to room temperature, take out sample.
(4) prepare transistor source and drain electrode
In conjunction with mask technique and DC sputtering, in semiconductor active layer ZnO film plated surface Pt source electrode and drain electrode, its thickness is 150nm, obtains ferroelectric gate thin-film transistors.
Ferroelectric layer in the transistor of preparation is carried out to XRD analysis, and the light source of XRD is Cu K
αray, sweep limits is 10～60 °, velocity scanning is 4 °/min.Result as shown in Figure 3, Bi
3.15nd
0.85ti
3o
12ferroelectric thin film presents an obvious a axle preferrel orientation.
Adopt ferroelectric analyzer to test the electric hysteresis loop of ferroelectric layer, as shown in Figure 4, it has a larger residual polarization value to its result, is 20 μ C/cm
2.
Adopt B1500A semiconductor device analyzer to test the dielectric frequency spectrum (as Fig. 5) of ferroelectric layer and the output characteristic (as Fig. 6) of ferroelectric gate thin-film transistors, transfer characteristic (as Fig. 7 and Fig. 8), when obtaining frequency and being 1MHz, the dielectric constant of ferroelectric layer is 248, transistorized cut-in voltage is 1.1V, and current on/off ratio is 1.8 * 10
6.
Embodiment 2
The present embodiment be adopt pulsed laser deposition at [100] direction mis-cut angle θ, be on Si (001) substrate of 6 ° preparation with LaNiO
3film is as bottom gate thin film, Pb (Zr
0.53ti
0.47) O
3ferroelectric thin film is the ferroelectric gate thin-film transistors as active layer as insulating barrier, ZnO film, comprises the following steps:
(1) installation of substrate and target
Selected ferroelectric material target is Pb (Zr
0.53ti
0.47) O
3target, all the other are with embodiment 1.
(2) vacuumize
With embodiment 1
(3) laser coating
LaNiO
3deposition oxygen press as 50mTorr, obtain the LaNiO of high c-axis orientation
3film, its thickness is 50nm; Pb (Zr
0.53ti
0.47) O
3the deposition oxygen of ferroelectric thin film is pressed as 100mTorr, and depositing temperature is 600 ℃, obtains having the Pb (Zr of c-axis preferred orientation
0.53ti
0.47) O
3ferroelectric layer film, its thickness is 320nm; All the other are with embodiment 1.
(4) prepare transistor source and drain electrode
With embodiment 1, obtain ferroelectric gate thin-film transistors
Embodiment 3
The present embodiment be adopt pulsed laser deposition at [110] direction mis-cut angle θ, be on Si (100) substrate of 5 ° preparation with LaNiO
3film is as bottom gate thin film, Bi
3.25la
0.75ti
3o
12ferroelectric thin film is as insulating barrier, In
2o
3: Sn film, as the ferroelectric gate thin-film transistors of active layer, comprises the following steps:
(1) installation of substrate and target
Selected ferroelectric material target and oxide semiconductor target material are respectively Bi
3.25la
0.75ti
3o
12target and In
2o
3: Sn target, all the other are with embodiment 1.
(2) vacuumize
With embodiment 1
(3) laser coating
Bi
3.25la
0.75ti
3o
12the deposition oxygen of ferroelectric thin film is pressed as 250mTorr, and depositing temperature is 750 ℃, obtains having the Bi of a axle preferrel orientation
3.25la
0.75ti
3o
12ferroelectric layer film, its thickness is 500nm; In
2o
3: the deposition oxygen of Sn film is pressed as 10mTorr, and depositing temperature is 300 ℃, and its thickness is 20nm; All the other are with embodiment 1.
(4) prepare transistor source and drain electrode
With embodiment 1, obtain ferroelectric gate thin-film transistors.
Embodiment 4
The present embodiment be adopt pulsed laser deposition at [100] direction mis-cut angle θ, be on Si (001) substrate of 5 ° preparation with LaNiO
3film is as bottom gate thin film, Pb (Zr
0.53ti
0.47) O
3ferroelectric thin film is as insulating barrier, In
2o
3: Sn film, as the ferroelectric gate thin-film transistors of active layer, comprises the following steps:
(1) installation of substrate and target
Selected ferroelectric material target and oxide semiconductor target material are respectively Pb (Zr
0.53ti
0.47) O
3target and In
2o
3: Sn target, all the other are with embodiment 1.
(2) vacuumize
With embodiment 1
(3) laser coating
LaNiO
3deposition oxygen press as 50mTorr, obtain the LaNiO of high c-axis orientation
3film, its thickness is 100nm; Pb (Zr
0.53ti
0.47) O
3deposition oxygen press as 100mTorr, depositing temperature is 600 ℃, obtains having the Pb (Zr of c-axis preferred orientation
0.53ti
0.47) O
3ferroelectric layer film, its thickness is 280nm; In
2o
3: the deposition oxygen of Sn is pressed as 10mTorr, and base reservoir temperature is 300 ℃; Its thickness is 20nm, and all the other are with embodiment 1.
(4) prepare transistor source and drain electrode
With embodiment 1, obtain ferroelectric gate thin-film transistors.
Embodiment 5
The present embodiment be adopt pulsed laser deposition at [100] direction mis-cut angle θ, be on Si (001) substrate of 3 ° preparation with La
0.67sr
0.33mnO
3film is as bottom gate thin film, Pb (Zr
0.52ti
0.48) O
3ferroelectric thin film is as insulating barrier, In
2o
3: Sn film, as the ferroelectric gate thin-film transistors of active layer, comprises the following steps:
(1) installation of substrate and target
Selected conductive oxide target, ferroelectric material target and oxide semiconductor target material are respectively La
0.67sr
0.33mnO
3target, Pb (Zr
0.52ti
0.48) O
3target and In
2o
3: Sn target, all the other are with embodiment 1.
(2) vacuumize
With embodiment 1
(3) laser coating
La
0.67sr
0.33mnO
3deposition oxygen press as 20mTorr, depositing temperature is 700 ℃, obtains the La of high c-axis orientation
0.67sr
0.33mnO
3film, its thickness is 100nm; Pb (Zr
0.53ti
0.47) O
3deposition oxygen press as 100mTorr, depositing temperature is 600 ℃, obtains having the Pb (Zr of high c-axis preferred orientation
0.53ti
0.47) O
3ferroelectric layer film, its thickness is 280nm; In
2o
3: the deposition oxygen of Sn is pressed as 10mTorr, and base reservoir temperature is 300 ℃; Its thickness is 20nm, and all the other are with embodiment 1.
(4) prepare transistor source and drain electrode
With embodiment 1, obtain ferroelectric gate thin-film transistors.
Embodiment 6
The present embodiment be adopt pulsed laser deposition at [100] direction mis-cut angle θ, be on Si (001) substrate of 20 ° preparation with La
0.5sr
0.5coO
3film is as bottom gate thin film, Pb (Zr
0.52ti
0.48) O
3ferroelectric thin film is as insulating barrier, In
2o
3: Sn film, as the ferroelectric gate thin-film transistors of active layer, comprises the following steps:
(1) installation of substrate and target
Selected conductive oxide target, ferroelectric material target and oxide semiconductor target material are respectively La
0.5sr
0.5coO
3target, Pb (Zr
0.52ti
0.48) O
3target and In
2o
3: Sn target, all the other are with embodiment 1.
(2) vacuumize
With embodiment 1
(3) laser coating
La
0.5sr
0.5coO
3deposition oxygen press as 50mTorr, depositing temperature is 750 ℃, obtains the La of high c-axis orientation
0.5sr
0.5coO
3film, its thickness is 80nm; Pb (Zr
0.53ti
0.47) O
3deposition oxygen press as 100mTorr, depositing temperature is 600 ℃, obtains having the Pb (Zr of c-axis preferred orientation
0.53ti
0.47) O
3ferroelectric layer film, its thickness is 200nm; In
2o
3: the deposition oxygen of Sn is pressed as 10mTorr, and base reservoir temperature is 300 ℃; Its thickness is 10nm, and all the other are with embodiment 1.
(4) prepare transistor source and drain electrode
In conjunction with mask technique and magnetron sputtering method at semiconductor active layer ZnO film plated surface SrRuO
3source electrode and drain electrode, its thickness is 100nm, obtains ferroelectric gate thin-film transistors.With embodiment 1, obtain ferroelectric gate thin-film transistors.
Embodiment 7
The present embodiment be adopt magnetron sputtering method at [100] direction mis-cut angle θ, be on Si (001) substrate of 4 ° preparation with SrRuO
3film is as bottom gate thin film, BiFeO
3ferroelectric thin film is as insulating barrier, In
2o
3: Sn film, as the ferroelectric gate thin-film transistors of active layer, comprises the following steps:
(1) installation of substrate and target
In vacuum chamber, by SrRuO
3, BiFeO
3and In
2o
3: Sn target is installed on many targets frame, after the Si substrate of cutting sth. askew cleans up, is arranged on substrate holder, regulates the distance of substrate and target to 45mm.
(2) vacuumize
Open successively mechanical pump and molecular pump, the pressure in vacuum chamber is evacuated to 4 * 10
-4p
a.
(3) magnetron sputtering plating
Operating pressure is made as 4Pa, by flowmeter, in vacuum chamber, passes into Ar and O
2mist (Ar:O
2=3:1), open heating furnace, base reservoir temperature is risen to 650 ℃, sputtering power is made as 70W, prepares the SrRuO of high c-axis orientation
3film bottom electrode layer, its thickness is 100nm; After treating that afterwards sample is cooled to Room, at SrRuO
3mask film covering plate on film, to reserve bottom gate thin film, base reservoir temperature is risen to 550 ℃ after at SrRuO
3biFeO grows on hearth electrode
3ferroelectric thin film, obtains the BiFeO of high c-axis orientation
3ferroelectric thin film insulating barrier, its thickness is 280nm; Operating pressure is adjusted into 0.6Pa (Ar:O
2=10:1), base reservoir temperature is down to 300 ℃ at BiFeO
3in grows on ferroelectric insulating barrier
2o
3: Sn oxide semiconductor thin-film, its thickness is 20nm; Close successively substrate heating controller, molecular pump and mechanical pump, after sample is cooled to room temperature, take out sample.
(4) prepare transistor source and drain electrode
In conjunction with mask technique and DC sputtering at semiconductor active layer In
2o
3: Sn film surface plating Pt source electrode and drain electrode, its thickness is 100nm, obtains ferroelectric gate thin-film transistors.
Embodiment 8
The present embodiment be adopt magnetron sputtering method at [110] direction mis-cut angle θ, be on Si (001) substrate of 4 ° preparation with SrRuO
3film is as bottom gate thin film, BiFeO
3ferroelectric thin film is the ferroelectric gate thin-film transistors as active layer as insulating barrier, ZnO film, comprises the following steps:
(1) installation of substrate and target
Selected oxide semiconductor target material is ZnO target, and all the other are with embodiment 5.
(2) vacuumize
With embodiment 5
(3) magnetron sputtering plating
ZnO deposition pressure is 1Pa (Ar:O wherein
2=2:1), depositing temperature is 300 ℃, and its thickness is 30nm; All the other are with embodiment 5.
(4) prepare transistor source and drain electrode
With embodiment 1, obtain ferroelectric gate thin-film transistors.
Comparative example 1
In order to adopt cut sth. askew substrate and perovskite bottom gate thin film to regulate and control the beneficial effect of ferroelectric layer Thin Films Tropism Growing as template layer in comparative example 1, according to the preparation method of embodiment 1, at mis-cut angle θ, be to have prepared and usingd precious metals pt as bottom gate thin film, Bi on Si (100) substrate of 0 °
3.15nd
0.85ti
3o
12ferroelectric thin film is the ferroelectric gate thin-film transistors as active layer as insulating barrier, ZnO film, and except substrate and bottom gate thin film, other are consistent with embodiment 1.
The preparation method of Pt bottom gate thin film layer is DC magnetron sputtering method.Sputtering power is 80W, and sputtering atmosphere is Ar, and air pressure is 1.5Pa, and growth temperature is 200 ℃, and its thickness is 200nm.
Ferroelectric layer in the transistor of preparation is carried out to XRD analysis, and the light source of XRD is Cu K
αray, sweep limits is 10～60 °, velocity scanning is 4 °/min.Result as shown in Figure 3, Bi
3.15nd
0.85ti
3o
12ferroelectric thin film is mainly c-axis growth.
Adopt ferroelectric analyzer to test the electric hysteresis loop of ferroelectric layer, as shown in Figure 4, it has residual polarization value is 10 μ C/cm to its result
2, be less than the polarization value in experimental example 1.
Adopt B1500A semiconductor device analyzer to test the dielectric frequency spectrum of ferroelectric layer, when frequency is 1MHz, its dielectric constant is 128, is less than the dielectric constant in embodiment 1.
Comparative example 2
In order to adopt the substrate of cutting sth. askew to regulate and control the beneficial effect of ferroelectric layer Thin Films Tropism Growing in comparative example 1, according to the preparation method of embodiment 1, at mis-cut angle θ, be to have prepared with LaNiO on Si (100) substrate of 0 °
3film is as bottom gate thin film, Bi
3.15nd
0.85ti
3o
12ferroelectric thin film is the ferroelectric gate thin-film transistors as active layer as insulating barrier, ZnO film, except substrate with, other are consistent with embodiment 1.
Ferroelectric layer in the transistor of preparation is carried out to XRD analysis, and the light source of XRD is Cu K
αray, sweep limits is 10～60 °, velocity scanning is 4 °/min.Result as shown in Figure 3, Bi
3.15nd
0.85ti
3o
12ferroelectric thin film presents random orientation growth.
Adopt ferroelectric analyzer to test the electric hysteresis loop of ferroelectric layer, as shown in Figure 4, it has residual polarization value is 8 μ C/cm to its result
2, be less than the polarization value in experimental example 1.
Adopt B1500A semiconductor device analyzer to test the dielectric frequency spectrum of ferroelectric layer, when frequency is 1MHz, its dielectric constant is 154, is less than the dielectric constant in embodiment 1.
Claims (10)
1. a silicon-based ferroelectric gate thin-film transistors, it is characterized in that, this transistor bottom is the monocrystalline substrate of cutting sth. askew (1), intermediate layer is followed successively by perovskite conductive oxide bottom gate thin film (2), ferroelectric insulating barrier (3) and oxide semiconductor active layer (4) from top to bottom, and top layer is transistor source (5) and drain electrode (6); Wherein, the monocrystalline substrate of cutting sth. askew described in (1) is for having the intrinsic silicon of atomic size step.
2. silicon-based ferroelectric gate thin-film transistors according to claim 1, is characterized in that, described in the cut sth. askew scope of mis-cut angle θ of silicon substrate (1) be 0 ° of < θ≤20 °.
3. silicon-based ferroelectric gate thin-film transistors according to claim 1, is characterized in that, described in the cut sth. askew mis-cut angle θ of silicon substrate (1) be 3 °≤θ≤10 °.
4. silicon-based ferroelectric gate thin-film transistors according to claim 1, is characterized in that, described perovskite conductive oxide bottom gate thin film (2) is LaNiO
3, SrRuO
3, La
0.7ca
0.3mnO
3, La
0.67sr
0.33mnO
3or La
0.5sr
0.5coO
3film.
5. silicon-based ferroelectric gate thin-film transistors according to claim 1, is characterized in that, described ferroelectric insulating barrier (3) material is Bi
4ti
3o
12, SrBi
2ta
2o
9, PbTiO
3, BaTiO
3or BiFeO
3, or be one or several doping Bi of La, Nd, Ce, Sr, Zr, Mn, W, Na
4ti
3o
12, SrBi
2ta
2o
9, PbTiO
3, BaTiO
3or BiFeO
3in any one;
Described oxide semiconductor active layer (4) is ZnO, SnO
2or In
2o
3in any one, or be Al, Li, Sn, Sb, one or several doping ZnOs of Ga, SnO
2or In
2o
3in any one;
Described source electrode (5) and drain electrode (6) are Pt, Au, Ag, Ir or Ti metal level, or are two or more the formed metal composite layer in above metal, or are LaNiO
3, SrRuO
3, IrO
2any one in metal oxide.
6. silicon-based ferroelectric gate thin-film transistors according to claim 1, is characterized in that, described perovskite conductive oxide bottom gate thin film (2) thickness is 10～200nm;
Described ferroelectric insulating barrier (3) thickness is 50～600nm;
Described oxide semiconductor active layer (4) thickness is 10～100nm;
Described source electrode (5) and drain electrode (6) thickness are respectively 10～200nm.
7. the preparation method of the silicon-based ferroelectric gate thin-film transistors described in claim 1-6 any one, is characterized in that, comprises the steps: that [1] clean the monocrystalline silicon substrate of cutting sth. askew, with as substrate; [2] the perovskite conductive oxide bottom gate thin film of growing in the monocrystalline substrate of cutting sth. askew; [3] the ferroelectric insulating barrier of growing in perovskite conductive oxide bottom gate thin film; [4] grow oxide semiconductor active layer on ferroelectric insulating barrier; [5] source electrode of grown transistor and drain electrode on oxide semiconductor active layer.
8. preparation method according to claim 7, is characterized in that, grows by pulsed laser deposition or magnetron sputtering method in described step [2] and [3].
9. preparation method according to claim 7, it is characterized in that, in described step [2], by controlling sedimentary condition and the cut sth. askew orientation of silicon substrate and crystal orientation and the lattice constant that angle regulates and controls perovskite conductive oxide film, the perovskite conductive oxide film of the oriented growth of gained is as the template layer of transistorized bottom gate thin film layer and the ferroelectric insulating barrier of growth.
10. preparation method according to claim 7, is characterized in that, described step [3] is specially: the ferroelectric insulating barrier by perovskite conductive oxide gate electrode (2) as template layer growth preferred orientation.
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