CN105448734A - 一种改善器件双峰效应的方法和半导体器件 - Google Patents

一种改善器件双峰效应的方法和半导体器件 Download PDF

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CN105448734A
CN105448734A CN201410444255.7A CN201410444255A CN105448734A CN 105448734 A CN105448734 A CN 105448734A CN 201410444255 A CN201410444255 A CN 201410444255A CN 105448734 A CN105448734 A CN 105448734A
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polycrystalline silicon
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郝龙
金炎
李伟
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CSMC Technologies Corp
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Wuxi CSMC Semiconductor Co Ltd
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Priority to PCT/CN2015/088836 priority patent/WO2016034123A1/zh
Priority to US15/328,623 priority patent/US20170222012A1/en
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Abstract

本发明提供一种改善器件双峰效应的方法，将所述器件有源区的位于所述器件栅极多晶硅下方的区域沿着所述栅极多晶硅的长度方向拉宽，使所述有源区的边缘远离所述器件的导电沟道。本发明还提供一种半导体器件，所述半导体器件包括有源区和部分覆盖于所述有源区上的栅极区，位于所述栅极区下方的有源区的宽度大于其余有源区的宽度。根据本发明，在不需要增加新的工艺步骤进而不会增加制造成本的情况下，能够完全消除器件的双峰效应，不受到有源区的边缘形貌的限制，器件的可靠性也会有相应的提升。

Description

一种改善器件双峰效应的方法和半导体器件
技术领域
本发明涉及半导体制造工艺，具体而言涉及一种改善器件双峰效应的方法和半导体器件。
背景技术
随着集成电路的不断发展，人们对器件的性能要求越来越高，器件的双峰效应对电路的影响也就凸显出来。双峰效应可能会导致电路的输出错误，进而产生终端失效，电路无法正常工作，影响整个电路的可靠性。
双峰效应就是在测量器件的阈值电压时，跨导出现两个最大的峰值，由于这两个峰值的存在，阈值电压曲线会有波动，在计算阈值电压时出现错误。通常情况下，产生双峰效应的原因是器件边缘效应，由于位于器件边缘的栅极氧化层的厚度和位于器件中心的主器件区域的栅极氧化层的厚度存在差异，如图1(a)所示，且该差异会随着栅极氧化层的厚度的增加而增大，这就相当于在器件边缘存在两个寄生器件101，如图1(b)所示，这两个寄生器件的阈值电压和器件中心的主器件区域102的阈值电压存在差异，上述两个差异就是双峰效应的主要来源。
因此，需要提出一种方法，以解决上述问题。
发明内容
针对现有技术的不足，本发明提供一种改善器件双峰效应的方法，将所述器件有源区的位于所述器件栅极多晶硅下方的区域沿着所述栅极多晶硅的长度方向拉宽，使所述有源区的边缘远离所述器件的导电沟道。
在一个示例中，所述将所述器件有源区的位于所述器件栅极多晶硅下方的区域沿着所述栅极多晶硅的长度方向拉宽，具体为：
利用有源区掩膜版，定义所述器件有源区，使所述器件有源区的位于所述器件栅极多晶硅下方的区域向两侧沿着所述栅极多晶硅的长度方向各拉宽0.1微米～0.4微米。
在一个示例中，所述将所述器件有源区的位于所述器件栅极多晶硅下方的区域沿着所述栅极多晶硅的长度方向拉宽后，还包括：
将所述器件有源区的所述沿着所述栅极多晶硅的长度方向拉宽的部分向两侧沿着所述栅极多晶硅的宽度方向各拉宽0微米～0.4微米。
本发明还提供一种半导体器件，所述半导体器件包括有源区和部分覆盖所述有源区的栅极区，位于所述栅极区下方的有源区的宽度大于其余有源区的宽度。
在一个示例中，位于所述栅极区下方的有源区的宽度比所述其余有源区的宽度宽0.1微米～0.4微米。
在一个示例中，所述栅极区为栅极多晶硅。
根据本发明，在不需要增加新的工艺步骤进而不会增加制造成本的情况下，能够完全消除器件的双峰效应，不受到有源区的边缘形貌的限制，器件的可靠性也会有相应的提升。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1为产生双峰效应的器件边缘效应的示意图；
图2A-图2F为现有技术中通过调节有源区的制程来降低位于器件边缘的栅极氧化层的厚度与位于器件中心的主器件区域的栅极氧化层的厚度之间的差异而依次实施的步骤所分别获得的器件的示意性剖面图；
图3为现有技术中提高器件的场氧与有源区的台阶高度的示意图；
图4为根据本发明将器件有源区的位于栅极多晶硅下方的区域沿着栅极多晶硅的长度方向和宽度方向拉宽后的器件结构的示意图；
图5为根据本发明将器件有源区的位于栅极多晶硅下方的区域沿着栅极多晶硅的长度方向和宽度方向拉宽前后的器件的双峰效应对比图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
为了彻底理解本发明，将在下列的描述中提出详细的步骤，以便阐释本发明提出的改善器件双峰效应的方法和半导体器件。显然，本发明的施行并不限定于半导体领域的技术人员所熟习的特殊细节。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。
为了抑制器件双峰效应的发生，现有的方法是通过各种技术手段使位于器件边缘的栅极氧化层的厚度与位于器件中心的主器件区域的栅极氧化层的厚度保持一致或者使二者的差异减小。
这些技术大致分为两种，一种是调节器件有源区的制程，使有源区的拐角部分更为圆滑，进而使栅极氧化层的生长更为均匀，从而降低位于器件边缘的栅极氧化层的厚度与位于器件中心的主器件区域的栅极氧化层的厚度之间的差异。举例说来，首先，如图2A所示，提供半导体衬底200，其构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)等，在半导体衬底200上依次形成薄层氧化物层201和氮化硅层202，薄层氧化物层201作为缓冲层可以释放氮化硅层202和半导体衬底200之间的应力；接着，如图2B所示，对氮化硅层202进行退火之后，利用氮化硅层202作为掩膜进行有源区蚀刻，以在半导体衬底200中蚀刻出用于填充隔离材料(作为场氧)的沟槽203；接着，如图2C所示，回蚀刻氮化硅层202，并在沟槽203的侧壁和底部形成衬里氧化层204；接着，如图2D所示，沉积隔离材料层205，以填充沟槽203；接着，如图2E所示，研磨隔离材料层205，直至露出氮化硅层202的顶部；最后，如图2F所示，蚀刻去除氮化硅层202。在此示例中，通过回蚀刻氮化硅层202，在沟槽203的侧壁和底部形成衬里氧化层204之后，有源区的拐角处会更圆滑，后续在半导体衬底200上升长栅极氧化层的时候，位于器件边缘的栅极氧化层的厚度和位于主器件区域的栅极氧化层的厚度之间的差异就会减小。另外，如果不回蚀刻氮化硅层202，通过在沟槽203的侧壁和底部两次生长衬里氧化层204，也可以使有源区的拐角处更加圆滑，后续在半导体衬底200上升长栅极氧化层的时候，位于器件边缘的栅极氧化层的厚度和位于主器件区域的栅极氧化层的厚度之间的差异也会减小。
另外一种是提高器件的场氧与有源区的台阶300的高度，如图3所示，以防止生长栅极氧化层时位于有源区的拐角的露出，事实上是用场氧来弥补栅极氧化层在有源区的拐角处生长不足的缺陷，从而降低位于器件边缘的栅极氧化层的厚度与位于器件中心的主器件区域的栅极氧化层的厚度之间的差异。
但是，以上方法都没有也不可能完全消除器件的边缘效应，也就无法从根本上消除器件的双峰效应，因为它们无论怎样实施都无法使器件边缘和主器件区域完全一致，这主要是由于器件的结构所决定的，只要器件工作时，器件边缘有电流，就存在两个寄生器件，这两个寄生器件永远无法与主器件区域一致。
为此，本发明提出一种改善器件双峰效应的方法和半导体器件，如图4所示，将器件有源区401的位于栅极多晶硅402下方的区域沿着栅极多晶硅402的长度方向拉宽，即器件有源区401的位于栅极多晶硅402下方的区域的宽度大于有源区401的其余部分的宽度，从而使有源区401的位于栅极多晶硅402下方的区域的边缘远离器件的导电沟道。其中，导电沟道为有源区401与栅极多晶硅402的重叠部分，在导电沟道两侧的有源区401中分别形成有器件的源/漏区。由于在原有的有源区的基础上把有源区的位于栅极多晶硅下方的区域拉宽，使得有源区边缘远离导电沟道，这样就消除了如图1(b)所示的寄生器件，从而从根本上解决了器件的边缘效应，得以完全消除器件的双峰效应。作为示例，利用有源区掩膜版，定义器件有源区401，使器件有源区401的位于栅极多晶硅402下方的区域向两侧沿着栅极多晶硅402的长度方向各拉宽的宽度D1可以为0.1微米～0.4微米，优选0.2微米。将器件有源区401的位于栅极多晶硅402下方的区域沿着栅极多晶硅402的长度方向拉宽后，还包括将上述器件有源区401的沿着栅极多晶硅402的长度方向拉宽的部分向两侧沿着栅极多晶硅402的宽度方向拉宽，拉宽的宽度D2可以为0微米～0.4微米，优选0.2微米。
如图5所示，在相同的有源区边缘形貌的情况下，本发明提出的器件完全没有双峰效应，如图5中的两对曲线中的右侧曲线，而标准结构的器件双峰效应很严重，如图5中的两对曲线中的左侧曲线。根据本发明，在不需要增加新的工艺步骤进而不会增加制造成本的情况下，能够完全消除器件的双峰效应，不受到有源区的边缘形貌的限制，器件的可靠性也会有相应的提升。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (6)

1.一种改善器件双峰效应的方法，其特征在于，将所述器件有源区的位于所述器件栅极多晶硅下方的区域沿着所述栅极多晶硅的长度方向拉宽，使所述有源区的边缘远离所述器件的导电沟道。
2.根据权利要求1所述的改善器件双峰效应的方法，其特征在于，所述将所述器件有源区的位于所述器件栅极多晶硅下方的区域沿着所述栅极多晶硅的长度方向拉宽，具体为：
利用有源区掩膜版，定义所述器件有源区，使所述器件有源区的位于所述器件栅极多晶硅下方的区域向两侧沿着所述栅极多晶硅的长度方向各拉宽0.1微米～0.4微米。
3.根据权利要求1所述的改善器件双峰效应的方法，其特征在于，所述将所述器件有源区的位于所述器件栅极多晶硅下方的区域沿着所述栅极多晶硅的长度方向拉宽后，还包括：
将所述器件有源区的所述沿着所述栅极多晶硅的长度方向拉宽的部分向两侧沿着所述栅极多晶硅的宽度方向各拉宽0微米～0.4微米。
4.一种半导体器件，其特征在于，所述半导体器件包括有源区和部分覆盖所述有源区的栅极区，位于所述栅极区下方的有源区的宽度大于其余有源区的宽度。
5.根据权利要求4所述的半导体器件，其特征在于，位于所述栅极区下方的有源区的宽度比所述其余有源区的宽度宽0.1微米～0.4微米。
6.根据权利要求4所述的半导体器件，其特征在于，所述栅极区为栅极多晶硅。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786436A (zh) * 2017-11-14 2019-05-21 台湾积体电路制造股份有限公司 集成芯片及其形成方法
CN111490049A (zh) * 2019-02-27 2020-08-04 长江存储科技有限责任公司 位线驱动器装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018114750A1 (de) 2017-11-14 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor-layout zum reduzieren des kink-effekts

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005259745A (ja) * 2004-03-09 2005-09-22 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
CN101083285A (zh) * 2006-05-31 2007-12-05 松下电器产业株式会社 半导体器件
CN101197287A (zh) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 高压mos晶体管的制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4054894A (en) * 1975-05-27 1977-10-18 Rca Corporation Edgeless transistor
US4053916A (en) * 1975-09-04 1977-10-11 Westinghouse Electric Corporation Silicon on sapphire MOS transistor
JP2008010830A (ja) * 2006-05-31 2008-01-17 Matsushita Electric Ind Co Ltd 半導体装置
JP2009146999A (ja) * 2007-12-12 2009-07-02 Seiko Instruments Inc 半導体装置
CN101587908B (zh) * 2008-05-23 2010-11-17 南亚科技股份有限公司 凹入式沟道晶体管结构
JP2011009695A (ja) * 2009-05-29 2011-01-13 Toshiba Corp 不揮発性半導体記憶装置及びディプレッション型ｍｏｓトランジスタ
CN103094253B (zh) * 2011-11-07 2015-08-19 无锡华润上华科技有限公司 一种栅极氧化层测试结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005259745A (ja) * 2004-03-09 2005-09-22 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
CN101083285A (zh) * 2006-05-31 2007-12-05 松下电器产业株式会社 半导体器件
CN101197287A (zh) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 高压mos晶体管的制作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786436A (zh) * 2017-11-14 2019-05-21 台湾积体电路制造股份有限公司 集成芯片及其形成方法
CN111490049A (zh) * 2019-02-27 2020-08-04 长江存储科技有限责任公司 位线驱动器装置
US10937507B2 (en) 2019-02-27 2021-03-02 Yangtze Memory Technologies Co., Ltd. Bit line driver device including active region
CN111490049B (zh) * 2019-02-27 2021-09-10 长江存储科技有限责任公司 位线驱动器装置

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