CN105428363B - A kind of electric erasable programming non-volatility memorizer and operating method - Google Patents
A kind of electric erasable programming non-volatility memorizer and operating method Download PDFInfo
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- CN105428363B CN105428363B CN201510755892.0A CN201510755892A CN105428363B CN 105428363 B CN105428363 B CN 105428363B CN 201510755892 A CN201510755892 A CN 201510755892A CN 105428363 B CN105428363 B CN 105428363B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention belongs to field of semiconductor devices, a kind of electric erasable programming non-volatility memorizer and operating method are specifically disclosed；A kind of electric erasable programming non-volatility memorizer, including control pipe Mc0 and Mc1, tunneling tube Mt0 and Mt1, read pipe Mr0 and Mr1, selecting pipe Ms0 and Ms1, in addition to a high-voltage tube Mhv；Non-volatility memorizer operating method is programmed present invention also offers a kind of electric erasable, non-volatility memorizer is programmed using the electric erasable, applies different voltages respectively in each control port, is finally completed the read-write operation of memory.Structure of the present invention can be eliminated to be exhausted deeply, while preventing hole from discharging, is reduced depletion width, is increased electric field across oxide, improves the efficiency of erasing of non-volatility memorizer, reduction erasing time.
Description
Technical field
The invention belongs to field of semiconductor devices, and in particular to a kind of electric erasable programming non-volatility memorizer and operation
Method
Background technology
Semiconductor memory can be divided into two classes, i.e. volatile storage and non-volatility memorizer；Volatile storage
After referring to that power supply disconnects, it is impossible to keep its state, even and if non-volatility memorizer encounters power interruptions, its internal state
Remain to be kept for a very long time.
Traditional single polycrystalline non-volatility memorizer tunneling tube or use N traps electric capacity use p type field effect transistor, but
Both structures have deficiency, and the efficiency of erasing of traditional single polycrystalline non-volatility memorizer is low.
Tunneling tube is circuit theory diagrams such as Fig. 1 (a) of traditional single polycrystalline memory unit of the differential configuration of N trap electric capacity
Shown, Mc0 and Mc1 are control pipe, and Mt0 and Mt1 are tunneling tube, and Mr0 and Mr1 manage to read, and Ms0 and Ms1 are selecting pipe, tunnelling
Pipe diagrammatic cross-section such as Fig. 1 (b), when on trap connecing malleation and being wiped, channel surface transoid is carried by heat generation in a short time
For not enough inversion layer hole, thus can produce it is deep exhaust, such as Fig. 1 (b) is exhausted due to deep, can be produced on depletion layer
Larger pressure drop, so that the electric field in oxide layer reduces, F-N tunnelling currents are small, the electronics hair that tunnelling is got off from floating boom
Raw ionization by collision, produces electron hole pair, and depletion layer is gradually reduced, tunnelling current increase, because the hole of generation cannot be discharged,
The generation rate in hole is more than recombination rate during beginning, and hole can be accumulated in N traps, until generation rate is equal to recombination rate, now reaches
Balance, depletion layer such as Fig. 1 (c) during balance.
Tunneling tube is such as schemed for the circuit theory diagrams of the unit of single polycrystalline non-volatility memorizer of the field-effect transistor of p-type
Shown in 2 (a), shown in tunneling tube profile such as Fig. 2 (b), when negative voltage is coupled on floating boom or positive voltage is connect on trap and source, by
In hole can be injected from source, it will not produce and exhaust deeply, the final layer depth that exhausts is descended shown in Fig. 2 (b).Because hole can be with
Discharged, will not accumulated by source, under identical voltage, final depletion width of the depletion width than Fig. 1 (c) is wide, oxygen
The electric field changed in layer is smaller than Fig. 1 (c), and therefore, final tunnelling current is also small, and efficiency of erasing is relatively low.
The content of the invention
In order to improve the efficiency of erasing of non-volatility memorizer, the erasing time is reduced, the knot of the present invention in the prior art
A high-voltage tube is added on structure.Concrete technical scheme is as follows：
A kind of electric erasable programs non-volatility memorizer, including control pipe Mc0 and Mc1, and tunneling tube Mt0 and Mt1 are read
Pipe Mr0 and Mr1, selecting pipe Ms0 and Ms1, in addition to a high-voltage tube Mhv；The source electrode of the tunneling tube Mt0 and Mt1 and drain electrode
It is connected, and is connected with the source electrode of the high-voltage tube Mhv；The grid of the control pipe Mc1, the grid and tunnelling for reading pipe Mr1
Pipe Mt1 grid is connected；Grid, the reading pipe Mt0 grid of the control pipe Mc0 is connected with tunneling tube Mc0 grid；It is described
The drain electrode for reading pipe Mr1 is connected to selecting pipe Ms1 source electrode, and the drain electrode of the reading pipe Mr0 is connected to selecting pipe Ms0 source
Pole；Source electrode, the substrate for reading pipe Mr1 is connected with selecting pipe Ms1 substrate, and is connected to control port RD；It is described to read
Take pipe Mr0 source electrode, substrate to be connected with selecting pipe Ms0 substrate, and be connected to control port RD；The selecting pipe Ms0 and
Ms1 grid is respectively connecting to control port SEL；The substrate of tunneling tube Mt0, Mt1 connects out control port TUN；It is described
Selecting pipe Ms1 drain electrode is connected to port BL1, and selecting pipe Ms0 drain electrode is connected to port BL0；The source of the control pipe Mc0
Pole, drain electrode are connected with substrate, and are connected to control port CG0；The source electrode of the control pipe Mc1, drain electrode are connected with substrate, and even
It is connected to control port CG1；The Substrate ground end of the high-voltage tube Mhv, is connected after drain and gate connection with control port TUN；
The control pipe is P-type transistor, and the reading pipe is P-type transistor, and selecting pipe is P-type transistor, the height
Pressure pipe is N-type transistor.
Non-volatility memorizer operating method is programmed present invention also offers a kind of electric erasable, using the electric erasable
Non-volatility memorizer is programmed, when performing read operation, the unit of selection, the voltage of each control port is respectively TUN=0, RD=
VDD, SEL=0, CG1=0, CG0=0；Nonoptional unit, the voltage of each control port be respectively TUN=0, RD=0,
SEL=VDD, CG1=0, CG0=0；The unit of selection is performed when writing " 0 " operation, the voltage of each control port is respectively TUN
=VPP, RD=0, SEL=VMID, CG1=0, CG0=VPP；When one writing operation is performed to the unit of selection, each control port
Voltage be respectively TUN=VPP, RD=0, SEL=VMID, CG1=VPP, CG0=0；When performing write operation, it is not chosen
Unit, the voltage of each control port is respectively TUN=VMID, RD=VMID, SEL=VMID, CG1=0 or VPP, CG0=0
Or VPP.
Wherein, VPP represents to program the voltage added by erasing operation, and VMID is medium voltage, and VMID values are the one of VPP
Half, VDD represents operating voltage.
The beneficial effect obtained using the present invention：The present invention proposes a kind of eliminate and exhausted deeply, while prevent hole from discharging,
Reduce depletion width, increase the memory construction and operating method of electric field across oxide；With traditional single polycrystalline is non-volatile deposits
Reservoir is compared, and improves efficiency of erasing, reduces the erasing time.
Brief description of the drawings
Fig. 1 is the single polycrystalline memory unit figure for the differential configuration that tunneling tube is N trap electric capacity；
Fig. 2 is single polycrystalline nonvolatile storage location figure that tunneling tube is p type field effect transistor；
Fig. 3 is schematic structural view of the invention.
Embodiment
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings.
As shown in figure 3, being schematic structural view of the invention.Fig. 3 (a) figures are a kind of electric erasable programming non-volatile holographic storage
Device, including control pipe Mc0 and Mc1, tunneling tube Mt0 and Mt1 read pipe Mr0 and Mr1, selecting pipe Ms0 and Ms1, in addition to one
High-voltage tube Mhv；The tunneling tube Mt0 is connected with Mt1 source electrode with drain electrode, and is connected with the source electrode of the high-voltage tube Mhv；Institute
The grid for stating control pipe Mc1, the grid for reading pipe Mr1 are connected with tunneling tube Mt1 grid；The grid of the control pipe Mc0, reading
Pipe Mt0 grid is taken to be connected with tunneling tube Mc0 grid；The drain electrode for reading pipe Mr1 is connected to selecting pipe Ms1 source electrode,
The drain electrode for reading pipe Mr0 is connected to selecting pipe Ms0 source electrode；Source electrode, substrate and the selecting pipe Ms1 for reading pipe Mr1
Substrate be connected, and be connected to control port RD；Source electrode, the substrate for reading pipe Mr0 is connected with selecting pipe Ms0 substrate
Connect, and be connected to control port RD；The grid of the selecting pipe Ms0 and Ms1 is respectively connecting to control port SEL；The tunnelling
Pipe Mt0, Mt1 substrate connect out control port TUN；The drain electrode of the selecting pipe Ms1 is connected to port BL1, selecting pipe Ms0's
Drain electrode is connected to port BL0；
The source electrode of the control pipe Mc0, drain electrode are connected with substrate, and are connected to control port CG0；The control pipe Mc1
Source electrode, drain electrode is connected with substrate, and is connected to control port CG1；The Substrate ground end of the high-voltage tube Mhv, drain electrode and grid
It is connected after the connection of pole with control port TUN.
The control pipe is P-type transistor, and the reading pipe is P-type transistor, and selecting pipe is P-type transistor, the height
Pressure pipe is N-type transistor.
Non-volatility memorizer operating method is programmed present invention also offers a kind of electric erasable, using the electric erasable
Program non-volatility memorizer, when performing read operation, the voltage of each control port be respectively TUN=0, RD=VDD, SEL=0,
CG1=0, CG0=0；When performing not read operation, the voltage of each control port is respectively TUN=0, RD=0, SEL=VDD, CG1
=0, CG0=0；When " 0 " operation is write in execution, the voltage of each control port is respectively TUN=VPP, RD=0, SEL=VMID, CG1
=0, CG0=VPP；When performing one writing operation, the voltage of each control port be respectively TUN=VPP, RD=0, SEL=VMID,
CG1=VPP, CG0=0；When performing not write operation, the voltage of each control port is respectively TUN=VMID, RD=VMID, SEL=
VMID, CG1=0 or VPP, CG0=0 or VPP.
Wherein, VPP represents to program the voltage added by erasing operation, and VMID is medium voltage, and VMID values are the one of VPP
Half.
As shown in figure following table the memory perform read-write operation when each port voltage value, voltage unit is volt.
| Operation | TUN | RD | SEL | CG1 | CG0 |
| Read | 0 | VDD | 0 | 0 | 0 |
| Do not read | 0 | 0 | VDD | 0 | 0 |
| Write 0 | VPP | 0 | VMID | 0 | VPP |
| Write 1 | VPP | 0 | VMID | VDD | 0 |
| Do not write | VMID | VMID | VMID | 0 or VPP | 0 or VPP |
When performing erasing operation, add high pressure on the substrate of tunneling tube, the grid of high-voltage tube and miss high pressure, Substrate ground,
Grid are grounded, and the source of tunneling tube, drain electrode connect high pressure by high-voltage tube, due to tunneling tube source, hole can be provided by draining, therefore,
It will not produce and exhaust deeply, shown in depletion width such as Fig. 3 (b), meanwhile, after high pressure rises to maximum, the grid source of high-voltage tube
Voltage can be less than threshold voltage, and now high-voltage tube can be closed automatically, and the electronics that tunnelling is got off on floating boom, which collides, ionizes production
Raw hole can not be discharged, hole accumulation, when the generation rate in hole is equal to recombination rate, depletion width such as Fig. 3 (c) at this moment
It is shown, depletion width is reduced, electric field across oxide is improved, tunnelling current is improved, therefore improve efficiency of erasing.
As shown in table 2, it is the operation completed that each control port in memory of the present invention, which applies voltage,：
| Operation | TUN | RD | SEL | CG1 | CG0 |
| Read | 0 | 1 | 0 | 0 | 0 |
| Do not read | 0 | 0 | 1 | 0 | 0 |
| Write 0 | 10 | 0 | 5 | 0 | 10 |
| Write 1 | 10 | 0 | 5 | 10 | 0 |
| Do not write | 5 | 5 | 5 | ‐ | ‐ |
Table 2
When writing 0 operation, CG0 connects 10 volts, and CG1 connects 0 volt, and TUN connects 10 volts, and RD connects 0 volt, and SEL connects 5 volts, is compiled by Mr0
Journey, while being wiped by Mt1.
When writing 1 operation, CG0 connects 0 volt, and CG1 connects 10 volts, and TUN connects 10 volts, and RD connects 0 volt, and SEL connects 5 volts, is compiled by Mr1
Journey, while being wiped by Mt0.
The unit do not write, TUN connects 5 volts, and RD connects 5 volts, and SEL connects 5 volts.
In read operation, CG0 connects 0 volt, and CG1 connects 0 volt, and TUN connects 0 volt, and RD connects 1 volt, and SEL connects 0 volt.
During not read operation, CG0 connects 0 volt, and CG1 connects 0 volt, and TUN connects 0 volt, and RD connects 0 volt, and SEL connects 1 volt.
Although the above is the complete description to specific embodiments of the present invention, can take it is various modification, variant and
Alternative.These equivalents and alternative are included within the scope of the disclosure.Therefore, the scope of the present invention should not
Described embodiment is limited to, but should be defined by the appended claims.
Claims (2)
1. a kind of electric erasable programs non-volatility memorizer, including control pipe Mc0 and control pipe Mc1, tunneling tube Mt0 and tunnelling
Pipe Mt1, reads pipe Mr0 and reads pipe Mr1, selecting pipe Ms0 and selecting pipe Ms1, it is characterised in that：Including a high-voltage tube Mhv；
The tunneling tube Mt0 is connected with tunneling tube Mt1 source electrode with drain electrode, and is connected with the source electrode of the high-voltage tube Mhv；The control
Tubulation Mc1 grid, reading pipe Mr1 grid is connected with tunneling tube Mt1 grid；Grid, the reading pipe of the control pipe Mc0
Mt0 grid is connected with tunneling tube Mc0 grid；The drain electrode for reading pipe Mr1 is connected to selecting pipe Ms1 source electrode, described
The drain electrode for reading pipe Mr0 is connected to selecting pipe Ms0 source electrode；The lining of the source electrode, substrate and selecting pipe Ms1 for reading pipe Mr1
Bottom is connected, and is connected to control port RD；Source electrode, the substrate for reading pipe Mr0 is connected with selecting pipe Ms0 substrate,
And it is connected to control port RD；The grid of the selecting pipe Ms0 and selecting pipe Ms1 are respectively connecting to control port SEL；The tunnel
Poling Mt0, tunneling tube Mt1 substrate connect out control port TUN；The drain electrode of the selecting pipe Ms1 is connected to port BL1, choosing
The drain electrode for selecting pipe Ms0 is connected to port BL0；The source electrode of the control pipe Mc0, drain electrode are connected with substrate, and are connected to control end
Mouth CG0；The source electrode of the control pipe Mc1, drain electrode are connected with substrate, and are connected to control port CG1；The high-voltage tube Mhv's
Substrate ground end, is connected after drain and gate connection with control port TUN；
The control pipe is P-type transistor, and the reading pipe is P-type transistor, and selecting pipe is P-type transistor, the high-voltage tube
For N-type transistor.
2. a kind of electric erasable programs non-volatility memorizer operating method, non-using electric erasable programming described in claim 1
Volatile storage, it is characterised in that：When performing read operation, the voltage of each control port is respectively TUN=0, RD=VDD, SEL
=0, CG1=0, CG0=0；When performing not read operation, the voltage of each control port be respectively TUN=0, RD=0, SEL=VDD,
CG1=0, CG0=0；When " 0 " operation is write in execution, the voltage of each control port be respectively TUN=VPP, RD=0, SEL=VMID,
CG1=0, CG0=VPP；When performing one writing operation, the voltage of each control port is respectively TUN=VPP, RD=0, SEL=
VMID, CG1=VPP, CG0=0；When performing not write operation, the voltage of each control port be respectively TUN=VMID, RD=VMID,
SEL=VMID, CG1=0 or VPP, CG0=0 or VPP；Wherein, VPP represents to program the voltage added by erasing operation, during VMID is
Between voltage, VMID values are VPP half.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157308A (en) * | 2014-07-22 | 2014-11-19 | 中国人民解放军国防科学技术大学 | Pseudo-differential structure nonvolatile memory compatible with standard CMOS process |
| CN104299646A (en) * | 2014-10-24 | 2015-01-21 | 中国人民解放军国防科学技术大学 | Standard technology based ultralow-power-consumption nonvolatile memory |
| CN104392747A (en) * | 2014-10-24 | 2015-03-04 | 中国人民解放军国防科学技术大学 | Nonvolatile memory with low power consumption and low erasing voltage based on standard technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7221596B2 (en) * | 2002-07-05 | 2007-05-22 | Impinj, Inc. | pFET nonvolatile memory |
| US6980471B1 (en) * | 2004-12-23 | 2005-12-27 | Sandisk Corporation | Substrate electron injection techniques for programming non-volatile charge storage memory cells |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157308A (en) * | 2014-07-22 | 2014-11-19 | 中国人民解放军国防科学技术大学 | Pseudo-differential structure nonvolatile memory compatible with standard CMOS process |
| CN104299646A (en) * | 2014-10-24 | 2015-01-21 | 中国人民解放军国防科学技术大学 | Standard technology based ultralow-power-consumption nonvolatile memory |
| CN104392747A (en) * | 2014-10-24 | 2015-03-04 | 中国人民解放军国防科学技术大学 | Nonvolatile memory with low power consumption and low erasing voltage based on standard technology |
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