CN105428363A - Electric erasable programming non-volatile memory and operation method - Google Patents
Electric erasable programming non-volatile memory and operation method Download PDFInfo
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- CN105428363A CN105428363A CN201510755892.0A CN201510755892A CN105428363A CN 105428363 A CN105428363 A CN 105428363A CN 201510755892 A CN201510755892 A CN 201510755892A CN 105428363 A CN105428363 A CN 105428363A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
The invention belongs to the field of semiconductor devices, and specifically discloses an electric erasable programming non-volatile memory and an operation method. The memory comprises control tubes Mc0 and Mc1, tunneling tubes Mt0 and Mt1, reading tubes Mr0 and Mr1, selection tubes Ms0 and Ms1, and a high-voltage tube Mhv. The invention also provides an operation method for the memory. The method employs the memory to apply different voltages at all control ports, and finally completes the reading and writing operations of the memory. The structure of the memory can eliminate deep depletion, can prevent hole discharge, reduces the width of a depletion layer, adds an oxidation layer electric field, improves the erasing efficiency of the memory, and reduces the erasing time.
Description
Technical field
The invention belongs to field of semiconductor devices, be specifically related to a kind of electric erasable programming non-volatility memorizer and method of operation
Background technology
Semiconductor memory can be divided into two classes, i.e. volatile storage and non-volatility memorizer; Volatile storage refer to power supply disconnect after, its state can not be kept, even and if non-volatility memorizer encounters power interruptions, the state of its inside still can keep a very long time.
Traditional single polycrystalline non-volatility memorizer tunnelling pipe or adopt N trap electric capacity or adopt p type field effect transistor, but these two kinds of structures have deficiency, and the efficiency of erasing of traditional single polycrystalline non-volatility memorizer is low.
The circuit theory diagrams of traditional single polycrystalline memory unit of the differential configuration that tunnelling pipe is N trap electric capacity are as shown in Fig. 1 (a), Mc0 and Mc1 is control valve, Mt0 and Mt1 is tunnelling pipe, Mr0 and Mr1 is for reading pipe, Ms0 and Ms1 is for selecting pipe, tunnelling pipe generalized section is as Fig. 1 (b), trap connects malleation when wiping, channel surface transoid, produce by heat at short notice and do not provide enough inversion layer holes, therefore can produce and deeply exhaust, as Fig. 1 (b), owing to deeply exhausting, larger pressure drop can be produced on depletion layer, thus the electric field in oxide layer is reduced, F ?N tunnelling current little, the electronics that tunnelling is got off from floating boom collides ionization, produce electron hole pair, depletion layer reduces gradually, tunnelling current increases, because the hole produced cannot be discharged, during beginning, the generation rate in hole is greater than recombination rate, hole can accumulate in N trap, until generation rate equals recombination rate, now reach balance, during balance, depletion layer is as Fig. 1 (c).
The circuit theory diagrams of the unit of single polycrystalline non-volatility memorizer of the field-effect transistor that tunnelling pipe is P type are as shown in Fig. 2 (a), tunnelling pipe profile is as shown in Fig. 2 (b), floating boom is coupled negative voltage or on trap and source, connect positive voltage time, due to can from source injected hole, can not produce and deeply exhaust, namely the final depletion layer degree of depth is descended shown in Fig. 2 (b).Because hole can be discharged by source, can not accumulate, same electrical is depressed, final depletion width is wider than the depletion width of Fig. 1 (c), little than Fig. 1 (c) of the electric field in oxide layer, therefore, final tunnelling current is also little, and efficiency of erasing is lower.
Summary of the invention
In order to improve the efficiency of erasing of non-volatility memorizer, reducing the erasing time, the present invention's structure in the prior art adding a high-voltage tube.Concrete technical scheme is as follows:
A kind of electric erasable programming non-volatility memorizer, comprises control valve Mc0 and Mc1, tunnelling pipe Mt0 and Mt1, reads pipe Mr0 and Mr1, select pipe Ms0 and Ms1, also comprise a high-voltage tube Mhv; The source electrode of described tunnelling pipe Mt0 with Mt1 is connected with drain electrode, and is connected with the source electrode of described high-voltage tube Mhv; The grid of described control valve Mc1, the grid of reading pipe Mr1 are connected with the grid of tunnelling pipe Mt1; The grid of described control valve Mc0, the grid of reading pipe Mt0 are connected with the grid of tunnelling pipe Mc0; The drain electrode of described reading pipe Mr1 is connected to the source electrode selecting pipe Ms1, and the drain electrode of described reading pipe Mr0 is connected to the source electrode selecting pipe Ms0; Source electrode, the substrate of described reading pipe Mr1 are connected with the substrate of selection pipe Ms1, and are connected to control port RD; Source electrode, the substrate of described reading pipe Mr0 are connected with the substrate of selection pipe Ms0, and are connected to control port RD; The grid of described selection pipe Ms0 and Ms1 is connected to control port SEL respectively; The substrate of described tunnelling pipe Mt0, Mt1 connects control port TUN; The drain electrode of described selection pipe Ms1 is connected to port BL1, selects the drain electrode of pipe Ms0 to be connected to port BL0; Source electrode, the drain electrode of described control valve Mc0 are connected with substrate, and are connected to control port CG0; Source electrode, the drain electrode of described control valve Mc1 are connected with substrate, and are connected to control port CG1; The Substrate ground end of described high-voltage tube Mhv, drain and gate is connected with control port TUN after connecting;
Described control valve is P-type crystal pipe, and described reading pipe is P-type crystal pipe, and select pipe to be P-type crystal pipe, described high-voltage tube is N-type transistor.
Present invention also offers a kind of electric erasable programming non-volatility memorizer method of operation, adopt described electric erasable programming non-volatility memorizer, when performing read operation, the unit of selection, the voltage of each control port is respectively TUN=0, RD=VDD, SEL=0, CG1=0, CG0=0; Nonoptional unit, the voltage of each control port is respectively TUN=0, RD=0, SEL=VDD, CG1=0, CG0=0; When writing " 0 " operation to the unit execution selected, the voltage of each control port is respectively TUN=VPP, RD=0, SEL=VMID, CG1=0, CG0=VPP; When performing one writing operation to the unit selected, the voltage of each control port is respectively TUN=VPP, RD=0, SEL=VMID, CG1=VPP, CG0=0; When performing write operation, not by the unit selected, the voltage of each control port is respectively TUN=VMID, RD=VMID, SEL=VMID, CG1=0 or VPP, CG0=0 or VPP.
Wherein, VPP represents the voltage added by program erase operation, and VMID is intermediate voltage, and VMID value is the half of VPP, and VDD represents operating voltage.
Adopt the beneficial effect that the present invention obtains: the present invention proposes a kind of elimination and deeply exhaust, stop hole to be discharged simultaneously, reduce depletion width, increase memory construction and the method for operation of electric field across oxide; Compared with traditional single polycrystalline non-volatility memorizer, improve efficiency of erasing, decrease the erasing time.
Accompanying drawing explanation
Single polycrystalline memory unit figure of Fig. 1 to be tunnelling pipe be differential configuration of N trap electric capacity;
Single polycrystalline nonvolatile storage location figure of Fig. 2 to be tunnelling pipe be p type field effect transistor;
Fig. 3 is structural representation of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
As shown in Figure 3, be structural representation of the present invention.Fig. 3 (a) figure is a kind of electric erasable programming non-volatility memorizer, comprises control valve Mc0 and Mc1, tunnelling pipe Mt0 and Mt1, reads pipe Mr0 and Mr1, select pipe Ms0 and Ms1, also comprise a high-voltage tube Mhv; The source electrode of described tunnelling pipe Mt0 with Mt1 is connected with drain electrode, and is connected with the source electrode of described high-voltage tube Mhv; The grid of described control valve Mc1, the grid of reading pipe Mr1 are connected with the grid of tunnelling pipe Mt1; The grid of described control valve Mc0, the grid of reading pipe Mt0 are connected with the grid of tunnelling pipe Mc0; The drain electrode of described reading pipe Mr1 is connected to the source electrode selecting pipe Ms1, and the drain electrode of described reading pipe Mr0 is connected to the source electrode selecting pipe Ms0; Source electrode, the substrate of described reading pipe Mr1 are connected with the substrate of selection pipe Ms1, and are connected to control port RD; Source electrode, the substrate of described reading pipe Mr0 are connected with the substrate of selection pipe Ms0, and are connected to control port RD; The grid of described selection pipe Ms0 and Ms1 is connected to control port SEL respectively; The substrate of described tunnelling pipe Mt0, Mt1 connects control port TUN; The drain electrode of described selection pipe Ms1 is connected to port BL1, selects the drain electrode of pipe Ms0 to be connected to port BL0;
Source electrode, the drain electrode of described control valve Mc0 are connected with substrate, and are connected to control port CG0; Source electrode, the drain electrode of described control valve Mc1 are connected with substrate, and are connected to control port CG1; The Substrate ground end of described high-voltage tube Mhv, drain and gate is connected with control port TUN after connecting.
Described control valve is P-type crystal pipe, and described reading pipe is P-type crystal pipe, and select pipe to be P-type crystal pipe, described high-voltage tube is N-type transistor.
Present invention also offers a kind of electric erasable programming non-volatility memorizer method of operation, adopt described electric erasable programming non-volatility memorizer, when performing read operation, the voltage of each control port is respectively TUN=0, RD=VDD, SEL=0, CG1=0, CG0=0; When performing not read operation, the voltage of each control port is respectively TUN=0, RD=0, SEL=VDD, CG1=0, CG0=0; During operation that execution is write " 0 ", the voltage of each control port is respectively TUN=VPP, RD=0, SEL=VMID, CG1=0, CG0=VPP; When performing one writing operation, the voltage of each control port is respectively TUN=VPP, RD=0, SEL=VMID, CG1=VPP, CG0=0; Perform not write operation time, the voltage of each control port is respectively TUN=VMID, RD=VMID, SEL=VMID, CG1=0 or VPP, CG0=0 or VPP.
Wherein, VPP represents the voltage added by program erase operation, and VMID is intermediate voltage, and VMID value is the half of VPP.
As figure following table be shown in this memory perform read-write operation time each port voltage value, voltage unit is volt.
| Operation | TUN | RD | SEL | CG1 | CG0 |
| Read | 0 | VDD | 0 | 0 | 0 |
| Do not read | 0 | 0 | VDD | 0 | 0 |
| Write 0 | VPP | 0 | VMID | 0 | VPP |
| Write 1 | VPP | 0 | VMID | VDD | 0 |
| Do not write | VMID | VMID | VMID | 0 or VPP | 0 or VPP |
When performing erase operation, the substrate of tunnelling pipe adds high pressure, the grid of high-voltage tube and miss high pressure, Substrate ground, grid ground connection, the source of tunnelling pipe, drain electrode connects high pressure by high-voltage tube, due to the source of tunnelling pipe, drain electrode can provide hole, therefore, can not produce and deeply exhaust, depletion width is as shown in Fig. 3 (b), simultaneously, when high pressure rise to maximum after, the gate source voltage of high-voltage tube can be less than threshold voltage, now high-voltage tube can cut out automatically, the electronics got off by tunnelling on floating boom collide ionization produce hole can not discharge, hole accumulation, when the generation rate in hole equals recombination rate, at this moment depletion width is as shown in Fig. 3 (c), reduce depletion width, improve electric field across oxide, improve tunnelling current, therefore improve efficiency of erasing.
As shown in table 2, each control port in memory of the present invention applies the operation that namely voltage complete:
| Operation | TUN | RD | SEL | CG1 | CG0 |
| Read | 0 | 1 | 0 | 0 | 0 |
| Do not read | 0 | 0 | 1 | 0 | 0 |
| Write 0 | 10 | 0 | 5 | 0 | 10 |
| Write 1 | 10 | 0 | 5 | 10 | 0 |
| Do not write | 5 | 5 | 5 | ‐ | ‐ |
Table 2
When writing 0 operation, CG0 connects 10 volts, and CG1 connects 0 volt, and TUN connects 10 volts, and RD connects 0 volt, and SEL connects 5 volts, is programmed by Mr0, is wiped by Mt1 simultaneously.
When writing 1 operation, CG0 connects 0 volt, and CG1 connects 10 volts, and TUN connects 10 volts, and RD connects 0 volt, and SEL connects 5 volts, is programmed by Mr1, is wiped by Mt0 simultaneously.
The unit do not write, TUN connects 5 volts, and RD connects 5 volts, and SEL connects 5 volts.
When read operation, CG0 connects 0 volt, and CG1 connects 0 volt, and TUN connects 0 volt, and RD connects 1 volt, and SEL connects 0 volt.
During not read operation, CG0 connects 0 volt, and CG1 connects 0 volt, and TUN connects 0 volt, and RD connects 0 volt, and SEL connects 1 volt.
Although the above is the complete description to specific embodiments of the present invention, various amendment, variant and alternative can be taked.These equivalents and alternative are included within the scope of the invention.Therefore, scope of the present invention should not be limited to described embodiment, but should be defined by the appended claims.
Claims (2)
1. an electric erasable programming non-volatility memorizer, comprises control valve Mc0 and Mc1, tunnelling pipe Mt0 and Mt1, reads pipe Mr0 and Mr1, selects pipe Ms0 and Ms1, it is characterized in that: comprise a high-voltage tube Mhv; The source electrode of described tunnelling pipe Mt0 with Mt1 is connected with drain electrode, and is connected with the source electrode of described high-voltage tube Mhv; The grid of described control valve Mc1, the grid of reading pipe Mr1 are connected with the grid of tunnelling pipe Mt1; The grid of described control valve Mc0, the grid of reading pipe Mt0 are connected with the grid of tunnelling pipe Mc0; The drain electrode of described reading pipe Mr1 is connected to the source electrode selecting pipe Ms1, and the drain electrode of described reading pipe Mr0 is connected to the source electrode selecting pipe Ms0; Source electrode, the substrate of described reading pipe Mr1 are connected with the substrate of selection pipe Ms1, and are connected to control port RD; Source electrode, the substrate of described reading pipe Mr0 are connected with the substrate of selection pipe Ms0, and are connected to control port RD; The grid of described selection pipe Ms0 and Ms1 is connected to control port SEL respectively; The substrate of described tunnelling pipe Mt0, Mt1 connects control port TUN; The drain electrode of described selection pipe Ms1 is connected to port BL1, selects the drain electrode of pipe Ms0 to be connected to port BL0; Source electrode, the drain electrode of described control valve Mc0 are connected with substrate, and are connected to control port CG0; Source electrode, the drain electrode of described control valve Mc1 are connected with substrate, and are connected to control port CG1; The Substrate ground end of described high-voltage tube Mhv, drain and gate is connected with control port TUN after connecting;
Described control valve is P-type crystal pipe, and described reading pipe is P-type crystal pipe, and select pipe to be P-type crystal pipe, described high-voltage tube is N-type transistor.
2. an electric erasable programming non-volatility memorizer method of operation, adopt electric erasable programming non-volatility memorizer described in claim 1, it is characterized in that: when performing read operation, the voltage of each control port is respectively TUN=0, RD=VDD, SEL=0, CG1=0, CG0=0; When performing not read operation, the voltage of each control port is respectively TUN=0, RD=0, SEL=VDD, CG1=0, CG0=0; During operation that execution is write " 0 ", the voltage of each control port is respectively TUN=VPP, RD=0, SEL=VMID, CG1=0, CG0=VPP; When performing one writing operation, the voltage of each control port is respectively TUN=VPP, RD=0, SEL=VMID, CG1=VPP, CG0=0; Perform not write operation time, the voltage of each control port is respectively TUN=VMID, RD=VMID, SEL=VMID, CG1=0 or VPP, CG0=0 or VPP; Wherein, VPP represents the voltage added by program erase operation, and VMID is intermediate voltage, and VMID value is the half of VPP.
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Cited By (1)
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| CN106229005A (en) * | 2016-07-29 | 2016-12-14 | 中国人民解放军国防科学技术大学 | A kind of nonvolatile storage location, memorizer and operational approach |
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| US20050063235A1 (en) * | 2002-07-05 | 2005-03-24 | Impinj, Inc., A Delaware Corporation | PFET nonvolatile memory |
| US20060139998A1 (en) * | 2004-12-23 | 2006-06-29 | George Samachisa | Substrate electron injection techniques for programming non-volatile charge storage memory cells |
| CN104157308A (en) * | 2014-07-22 | 2014-11-19 | 中国人民解放军国防科学技术大学 | Pseudo-differential structure nonvolatile memory compatible with standard CMOS process |
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