CN105426132B - A kind of data acquisition and memory system and method based on double sampled rate - Google Patents
A kind of data acquisition and memory system and method based on double sampled rate Download PDFInfo
- Publication number
- CN105426132B CN105426132B CN201510962325.2A CN201510962325A CN105426132B CN 105426132 B CN105426132 B CN 105426132B CN 201510962325 A CN201510962325 A CN 201510962325A CN 105426132 B CN105426132 B CN 105426132B
- Authority
- CN
- China
- Prior art keywords
- data
- logic module
- storage
- sampling rate
- control logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
Abstract
The invention discloses a kind of data acquisition and memory systems and method based on double sampled rate, high sampling rate data flow is converted into low sampling rate data by data pick-up logic module, high sampling rate data and low sampling rate data flow access to storage and logic module are selected then to select one to be transmitted to storage control logic module for data to be stored via the logic simultaneously, and storage control logic module, which stores data to be stored, completes double sampled rate storage in entry data memory；System and method using the present invention can remain to keep the high time resolution to details of interest while extending the sampling time as long as possible, contradiction that can be between balanced sample time and sample rate；High and low two kinds of sample rates can be arranged according to user's actual need, and the switching trigger condition set by the user of sample rate determines, automatically switches so that the system is easy to use.
Description
Technical field
The present invention relates to digital collection fields more particularly to a kind of based on the data acquisition and memory system of double sampled rate and side
Method.
Background technology
Data collecting system is usually deposited by front end modulate circuit, analog/digital conversion circuit, Digital Logic control circuit and data
Reservoir forms.Modulate circuit is responsible for input signal being adjusted to the range for being suitble to analog/digital circuit to receive, analog/digital circuit be responsible for by
The analog signal of input is digitized, and Digital Logic control circuit is responsible for receiving digital signal and the control of analog/digital circuit output
Data storage processed stores these signals according to current system demand.
For above-mentioned data collecting system, sample rate and data storage depth are very important index.Sample rate index
According to the number (its unit is usually Sa/s or SPS) for being sampled (analog-to-digital conversion) in the acquisition system unit interval to signal, certainly
Determine to be digitized discrete density (i.e. temporal resolution) to analog signal.Storage depth, which refers to data collecting system, to be deposited
The maximum sampled point capacity of storage, the waveform time length that can be stored is determined in the case where common constant sample rate stores.
In traditional data collecting system, the constant sampling rate that can be only set according to user will be transformed
Digital data is stored according to the combination of certain sequence into memory.The benefit of this storage mode is simple in structure, is easy to real
It is existing, logical resource demand is low, memory bandwidth require it is low, but its disadvantage be due to the memory space of sampling system be it is fixed, such as
Fruit system is operated in high sampling rate, and then memory space will be quickly spilt out, and the sampling time is shorter, but can obtain the higher time
Resolution ratio, if be operated under low sampling rate, although the sampling time of storage extends due to reducing sample rate, and not
The details (because sample rate restricts) at the Wave anomaly of certain desired observations can be obtained.In short, since acquisition system stores deeply
The restriction of degree, for traditional constant sample rate data storage method there is the contradictory relation in sampling time and sample rate, two
Person cannot improve simultaneously.
How under the premise of acquisition system storage depth is limited, it is current data acquisition to take into account sample rate and storage time
System problem to be solved.
Invention content
In view of this, the present invention provides a kind of data acquisition and memory system and method based on double sampled rate, with balance
Contradiction of the acquisition system between sampling time and sample rate improves data collecting system performance.
A kind of data acquisition and memory system based on double sampled rate of the present invention, including front end modulate circuit, analog/digital conversion
Circuit, Digital Logic control circuit and data storage, wherein Digital Logic control circuit include data pick-up logic mould again
Block, storage selection logic module, storage control logic module and master control logic module；
The front end modulate circuit receives externally input analog signal, is sent after pretreatment to analog/digital conversion circuit
Digital signal is converted to, and is defined as high sampling rate data；
The digital decimation logic module believes the number received from analog/digital conversion circuit according to sample rate set by user
It number is extracted, obtains low sampling rate data；
Whether the event for needing high sampling rate to store of the master control logic module monitors user setting occurs, if hair
It is raw, that is, switching command is generated, storage selection logic module is sent to；It monitors the high sampling rate memory length simultaneously and whether meets and want
It asks, when meeting, generates and stop acquisition instructions, be sent to storage selection logic module；
Storage selection logic module receives the low sampling rate data and high sampling rate data simultaneously, and according to from master
The instruction that control logic module receives proceeds as follows：When not receiving any instruction, the low sampling rate data are exported
To storage control logic module；When receiving switching command, the high sampling rate data are exported to storage control logic mould
Block；When receiving stopping acquisition instructions, stop sending the high sampling rate data to storage control logic module, it will be described low
Sampling rate is input to storage control logic module；
The storage control logic module exports the data received from storage selection logic module to data storage device
It is stored.
A kind of data acquisition and storage method based on double sampled rate of the present invention, is as follows：
S01, the sample rate that data pick-up logic module is set according to user demand, and by the sample rate to turning from analog/digital
The digital signal for changing circuit output is extracted, and low sampling rate data are obtained；
S02, control storage selection logic module receive the low sampling rate data and high sampling rate data simultaneously；
S03, control storage selection logic module export the low sampling rate data to storage control logic module；Control
Storage control logic module constantly stores the data received into data storage；
Whether the data volume in S04, master control logic module Real-time Monitoring Data memory is less than the sampled point of user setting
Number gos to step S05 if less than if, if more than or equal to go to step S08；
S05, master control logic module monitors user setting need high sampling rate store event whether occur：If event is sent out
Raw, go to step S06, still keeps step S05 constant if not occurring；
S06, control storage selection logic module export the high sampling rate data received to storage control logic
Module；
S07, master control logic module monitors high sampling rate data memory length whether reach user setting length：If reaching
Then go to step S03, still keeps step S07 constant if not up to；
S08, control storage control logic module stopping store pending data into data storage, this double sampled rate is adopted
Collection is deposited storing process and is terminated.
The present invention has the advantages that：
(1) system and method using the present invention can remain to holding pair while extending the sampling time as long as possible
The high time resolution (sample rate high) of details of interest, contradiction that can be between balanced sample time and sample rate.
(2) high and low two kinds of sample rates in the present invention can be arranged according to user's actual need, the switching of sample rate by with
The trigger condition of family setting determines, automatically switches so that the system is easy to use.
Description of the drawings
Fig. 1 is data collecting system typical structure block diagram of the present invention；
Fig. 2 is dual seizure rate acquisition system data storage logic structure diagram of the present invention；
Fig. 3 is dual seizure rate acquisition system data Stored Procedure block diagram of the present invention.
Specific implementation mode
The present invention will now be described in detail with reference to the accompanying drawings and examples.
In view of this, the present invention provides a kind of data collecting system based on double sampled rate, data can be allowed to acquire system
System can also be sampled according to the trigger condition set by user with height with storing the tendency of non-sensitive waveform compared with low sampling rate
Forward and backward or a period of time nearby Wave data occurs for rate storage trigger event.Can effectively it delay in specific application scene
Solve sample rate and the contradictory relation between the sampling time.
Based on above-mentioned purpose, the technical scheme is that：High sampling rate data flow turns by data pick-up logic module
Turn to low sampling rate data, high sampling rate data and low sampling rate data flow access to storage selection logic module simultaneously and after pass through
It selects one to be transmitted to storage control logic module for data to be stored by the logic, stores control logic module by number to be stored
It is stored according to double sampled rate is completed in storage entry data memory.
As shown in Fig. 1, a kind of data acquisition and memory system based on double sampled rate, including：Front end modulate circuit, mould/
Number conversion circuit, Digital Logic control circuit and data storage, wherein external analog signal is input to front end modulate circuit,
Again by analog/digital conversion circuit, Digital Logic control circuit, store into data storage, Digital Logic control circuit is simultaneously
It connects modulate circuit, analog/digital conversion circuit, data storage and plays global control action, while Digital Logic control circuit also connects
It connects host computer and carries out data interaction.Above-mentioned control process is run in the form of Digital Logic among Digital Logic control circuit,
Its logical architecture is as shown in Fig. 2, Digital Logic control circuit selects logic module, storage by data pick-up logic module, storage
Control logic module and master control logic module composition.The master control logic module user setting needs high sampling rate to store
Whether event occurs, and if it happens, that is, generates switching command, is sent to storage selection logic module；
The front end modulate circuit receives externally input analog signal, is sent after pretreatment to analog/digital conversion circuit
Digital signal is converted to, and is defined as high sampling rate data；Wherein, the function of front end modulate circuit is to acquire to be to input data
The analog signal of system the operations such as is amplified, reduces, filtering and enabling to be input to analog/digital conversion circuit with suitable form the most
In.
The digital decimation logic module believes the number received from analog/digital conversion circuit according to sample rate set by user
It number is extracted, obtains low sampling rate data；
Whether the event for needing high sampling rate to store of the master control logic module monitors user setting occurs, if hair
It is raw, that is, switching command is generated, storage selection logic module is sent to；It monitors the high sampling rate memory length simultaneously and whether meets and want
It asks, when meeting, generates and stop acquisition instructions, be sent to storage selection logic module；Wherein, Digital Logic control circuit receives
After being instructed to host computer, also forward end modulate circuit, analog/digital conversion circuit send control signal, for adjusting front end conditioning electricity
Road and analog/digital conversion circuit enter the working condition that a user wants.
Storage selection logic module receives the low sampling rate data and high sampling rate data simultaneously, and according to from master
The instruction that control logic module receives proceeds as follows：When not receiving any instruction, the low sampling rate data are exported
To storage control logic module；When receiving switching command, the high sampling rate data are exported to storage control logic mould
Block；When receiving stopping acquisition instructions, stop sending the high sampling rate data to storage control logic module, it will be described low
Sampling rate is input to storage control logic module；
The storage control logic module exports the data received from storage selection logic module to data storage device
It is stored.
A kind of 100MSa/s includes to 10KSa/s variable sample rate data collecting systems：Front end modulate circuit, analog/digital turn
Change circuit, Digital Logic control circuit and data storage.Wherein, it is logical to be input to front end modulate circuit for external analog input signal
It crosses analog/digital conversion circuit, Digital Logic control circuit, store into data storage, Digital Logic control circuit connects simultaneously
Modulate circuit, analog/digital conversion circuit, data storage play global control action, while Digital Logic control circuit is also connected with
Position machine carries out data interaction.
The data collecting system memory capacity is fixed, and maximum supports the storage of 1MSample sampled datas.User is not
Resolution accuracy stores input analog voltage signal waveform for a long time as far as possible simultaneously when losing signal saltus step, and the data are arranged and adopt
Collecting system works under dual seizure rate memory module, and high capture rate is set as 100MSa/s, and low capture rate is set as 10KSa/s,
Storage depth is set as 1MSample, and high capture rate trigger signal is input voltage rising edge saltus step, the every section of storage of high capture rate
Point is 1KSample.
Based on the data acquisition and memory system of the present invention, the data acquisition based on double sampled rate that the present invention also provides a kind of
Storage method, as shown in figure 3, being as follows：
S00, setting data collecting system work under 100MSa/s high sampling rates, and by the sample rate to turning from analog/digital
The digital signal for changing circuit output is extracted, and low sampling rate data are obtained；
The sample rate that S01, setting data pick-up export low sampling rate data is 10KSa/s；
S02, control storage selection logic module receive the low sampling rate data and high sampling rate data simultaneously；
S03, control storage selection logic module export the low sampling rate data to storage control logic module；Control
Storage control logic module constantly stores the data received into data storage；
Whether storage data quantity is less than 1MSample for S04, master control logic monitoring, and S05 is jumped to if being less than, if more than
Equal to then jumping to S08；
S05, master control logic module monitors user setting need high sampling rate store event whether occur, and monitoring be
No generation input voltage rising edge saltus step, if event occurs, go to step S06, and step S05 is still kept not if not occurring
Become；
S06, control storage selection logic module export the high sampling rate data received to storage control logic
Module；
Whether S07, master control logic monitoring high sampling rate memory length reach 1KSample, go to step if reaching
S03 still keeps step S07 constant if not occurring；
S08, order storage control logic stopping store data to be stored into memory, this double sampled rate acquisition is deposited
Storing process terminates.
In conclusion the above is merely preferred embodiments of the present invention, being not intended to limit the scope of the present invention.
All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in the present invention's
Within protection domain.
Claims (2)
1. a kind of data acquisition and memory system based on double sampled rate, which is characterized in that turn including front end modulate circuit, analog/digital
Circuit, Digital Logic control circuit and data storage are changed, wherein Digital Logic control circuit includes data pick-up logic again
Module, storage selection logic module, storage control logic module and master control logic module；
The front end modulate circuit receives externally input analog signal, is sent after pretreatment to analog/digital conversion circuit conversion
For digital signal, and it is defined as high sampling rate data；
The data pick-up logic module according to sample rate set by user to from the digital signal that analog/digital conversion circuit receives into
Row extracts, and obtains low sampling rate data；
Whether the event for needing high sampling rate to store of the master control logic module monitors user setting occurs, if it happens, i.e.,
Switching command is generated, storage selection logic module is sent to；Monitor whether the high sampling rate memory length meets the requirements simultaneously, when
It when meeting, generates and stops acquisition instructions, be sent to storage selection logic module；
The storage selection logic module receives the low sampling rate data and high sampling rate data simultaneously, and is patrolled according to from master control
The instruction that module receives is collected to proceed as follows：When not receiving any instruction, the low sampling rate data are exported to depositing
Store up control logic module；When receiving switching command, the high sampling rate data are exported to storage control logic module；When
When receiving stopping acquisition instructions, stop sending the high sampling rate data to storage control logic module, by the low sampling
Rate data are input to storage control logic module；
The data received from storage selection logic module are exported to data storage device and are carried out by the storage control logic module
Storage.
2. a kind of data acquisition and storage method based on system described in claim 1, which is characterized in that be as follows：
S00, front end modulate circuit receive externally input analog signal, are sent after pretreatment to analog/digital conversion circuit conversion
For digital signal, and it is defined as high sampling rate data；
S01, the sample rate that data pick-up logic module is set according to user demand, and by the sample rate to electric from analog/digital conversion
The digital signal of road output is extracted, and low sampling rate data are obtained；
S02, control storage selection logic module receive the low sampling rate data and high sampling rate data simultaneously；
S03, control storage selection logic module export the low sampling rate data to storage control logic module；Control storage
Control logic module constantly stores the data received into data storage；
Whether the data volume in S04, master control logic module Real-time Monitoring Data memory is less than the sampling number of user setting, if
Less than the S05 that then gos to step, if more than or equal to then go to step S08；
S05, master control logic module monitors user setting need high sampling rate store event whether occur：If event occurs,
Go to step S06, still keeps step S05 constant if not occurring；
S06, control storage selection logic module export the high sampling rate data received to storage control logic module；
S07, master control logic module monitors high sampling rate data memory length whether reach user setting length：It is jumped if reaching
Step S03 is gone to, still keeps step S07 constant if not up to；
S08, control storage control logic module stopping store data to be stored into data storage, this double sampled rate is adopted
Collection storing process terminates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510962325.2A CN105426132B (en) | 2015-12-21 | 2015-12-21 | A kind of data acquisition and memory system and method based on double sampled rate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510962325.2A CN105426132B (en) | 2015-12-21 | 2015-12-21 | A kind of data acquisition and memory system and method based on double sampled rate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105426132A CN105426132A (en) | 2016-03-23 |
| CN105426132B true CN105426132B (en) | 2018-10-23 |
Family
ID=55504365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510962325.2A Active CN105426132B (en) | 2015-12-21 | 2015-12-21 | A kind of data acquisition and memory system and method based on double sampled rate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105426132B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107576988B (en) * | 2017-09-29 | 2021-06-18 | 中国科学院地质与地球物理研究所 | Automatic switching method and device for sampling rate of satellite-borne magnetometer |
| CN112235705B (en) * | 2020-10-13 | 2022-05-10 | 恒玄科技(上海)股份有限公司 | Double-ear hearing aid |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6671755B1 (en) * | 1999-05-24 | 2003-12-30 | Forfàs | System for data capture from a rotor |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
| CN102945095A (en) * | 2012-11-08 | 2013-02-27 | 山东大学 | Quick gesture judgment method for Android embedded touch screen equipment |
-
2015
- 2015-12-21 CN CN201510962325.2A patent/CN105426132B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6671755B1 (en) * | 1999-05-24 | 2003-12-30 | Forfàs | System for data capture from a rotor |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
| CN102945095A (en) * | 2012-11-08 | 2013-02-27 | 山东大学 | Quick gesture judgment method for Android embedded touch screen equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105426132A (en) | 2016-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105426132B (en) | A kind of data acquisition and memory system and method based on double sampled rate | |
| CN102788892B (en) | A kind of digital oscilloscope for accurately triggering | |
| CN104772550A (en) | System for multi-signal collecting of welding process and movement control of welding platform | |
| CN101776708A (en) | Multichannel voltage collecting device and method | |
| CN100529772C (en) | Power network overvoltage signal frequency conversion sampling method | |
| CN106019350A (en) | Nuclear pulse signal acquisition device and system | |
| CN103401725A (en) | Cross-platform equipment monitoring system based on cloud storage and monitoring method of cross-platform equipment monitoring system | |
| CN104598347A (en) | Waveform data acquisition module suitable for high density server test | |
| CN102496260B (en) | Multiple communication technology type of method for electric power information acquisition control | |
| CN206564662U (en) | A kind of video quality detecting system | |
| CN108804044B (en) | Deep storage based data acquisition method and deep storage data acquisition system | |
| WO2016201756A1 (en) | Multi-channel data collection and testing system | |
| CN102768495A (en) | Dynamic real-time cutting depth control method based on load of sugarcane harvesting mechanical cutterhead | |
| CN204649933U (en) | A kind of monitoring system showing the grid-connected rear state of synchronous motor | |
| CN203773270U (en) | FPGA-based multipath data collector of X ray detection equipment | |
| CN108319183A (en) | A kind of multichannel analog amount harvester and method | |
| CN105137141A (en) | Hand-held oscilloscope | |
| CN111505701B (en) | Compact accelerator beam phase and position measuring system and method | |
| CN214954951U (en) | General virtual module for detection | |
| CN205080177U (en) | Hand -held oscilloscope | |
| CN101764614B (en) | V-shaped sampling method of AD converter based on FPGA | |
| CN104834481B (en) | A kind of signal analysis device and method of the playback of large capacity quick storage | |
| CN105929464A (en) | System for meteorological monitoring | |
| CN202222005U (en) | Broadband signal trigger acquisition device | |
| CN209419723U (en) | The power supply indicating unit of set-top box |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |