CN105426132A - Data acquisition and storage system and method based on double sampling rates - Google Patents
Data acquisition and storage system and method based on double sampling rates Download PDFInfo
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- CN105426132A CN105426132A CN201510962325.2A CN201510962325A CN105426132A CN 105426132 A CN105426132 A CN 105426132A CN 201510962325 A CN201510962325 A CN 201510962325A CN 105426132 A CN105426132 A CN 105426132A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
Abstract
The invention discloses a data acquisition and storage system and method based on double sampling rates. A high-sampling-rate data stream is converted into low-sampling-rate data through a data extraction logic module, the high-sampling-rate data stream and the low-sampling-rate data stream are connected to a storage selection logic module at the same time, then one of the high-sampling-rate data stream and the low-sampling-rate data stream is selected through logical selection to be data to be stored and transmitted to a storage control logic module, and the storage control logic module stores the data to be stored in a data storage unit so that double-sampling-rate storage can be achieved. By the adoption of the system and method, high time resolution on concerned details can still be maintained on the basis that sampling time is prolonged as much as possible, and the contradiction between sampling time and sampling rate can be overcome; the high sampling rate and the low sampling rate can be set as needed, switching between the sampling rates is decided by a triggering condition set by a user, switching is conducted automatically, and the system is convenient to use.
Description
Technical field
The present invention relates to digital collection field, particularly relate to a kind of data acquisition storage system based on two sampling rate and method.
Background technology
Data acquisition system (DAS) is made up of front end modulate circuit, analog/digital conversion circuit, Digital Logic control circuit and data-carrier store usually.Modulate circuit is responsible for scope input signal being adjusted to applicable mould/number circuit reception, mould/number circuit is responsible for the simulating signal of input to carry out digitizing, and Digital Logic control circuit is responsible for receiving the digital signal of mould/number circuit output and these signals store according to current system demand by control data storer.
For above-mentioned data acquisition system (DAS), sampling rate and data storage depth are very important indexs.Sampling rate refers to the number of times (its unit is generally Sa/s or SPS) of data acquisition system (DAS) unit interval interior sample to signal (analog to digital conversion), decides and carries out the discrete density of digitizing (i.e. temporal resolution) to simulating signal.Storage depth refers to the maximum sampled point capacity that data acquisition system (DAS) can store, and situation about storing at common constant sample rate has been made decision the waveform time length that can store.
In traditional data acquisition system (DAS), only according to the constant sampling rate of user's setting, the digital data after conversion can be stored in storer according to certain sequential combination.The benefit of this storage mode be structure simple, be easy to realize, logical resource demand is low, memory bandwidth requires low, but its shortcoming is because the storage space of sampling system is fixing, if system works is in high sampling rate, storage space will overflow very soon, sampling time is shorter, but higher temporal resolution can be obtained, if under being operated in low sampling rate, although the sampling time stored extends but owing to reducing sampling rate, can not obtain again some details wanting the Wave anomaly place observed (because sampling rate restriction).In a word, due to the restriction of acquisition system storage depth, traditional constant sample rate data storage method is also existed to the contradictory relation of sampling time and sampling rate, both can not improve simultaneously.
How under the limited prerequisite of acquisition system storage depth, take into account sampling rate and storage time is the problem that current data acquisition system (DAS) needs to solve.
Summary of the invention
In view of this, the invention provides a kind of data acquisition storage system based on two sampling rate and method, to balance the contradiction of acquisition system between sampling time and sampling rate, improve data acquisition system (DAS) performance.
A kind of data acquisition storage system based on two sampling rate of the present invention, comprise front end modulate circuit, analog/digital conversion circuit, Digital Logic control circuit and data-carrier store, wherein Digital Logic control circuit comprises again data pick-up logic module, stores and select logic module, store control logic module and master control logic module;
Described front end modulate circuit accepts the simulating signal of outside input, and after pre-service, deliver to analog/digital conversion circuit conversion is digital signal, and is defined as high sampling rate data;
The sampling rate that described digital decimation logic module sets according to user extracts the digital signal received from analog/digital conversion circuit, obtains low sampling rate data;
Whether the event needing high sampling rate to store that described master control logic module monitors user is arranged occurs, if occurred, namely generates switching command, is sent to store to select logic module; Monitor this high sampling rate memory length whether to meet the demands simultaneously, when meeting, generating and stopping acquisition instructions, be sent to store and select logic module;
Described storage selects logic module to receive described low sampling rate data and high sampling rate data simultaneously, and proceed as follows according to the instruction received from master control logic module: when not receiving any instruction, export described low sampling rate data to store control logic module; When receiving switching command, export described high sampling rate data to store control logic module; When receiving stopping acquisition instructions, stopping sending described high sampling rate data to store control logic module, described low sampling rate data are inputed to store control logic module;
Described store control logic module exports the data selecting logic module to receive from storage to data storage and stores.
A kind of data acquisition storage means based on two sampling rate of the present invention, concrete steps are as follows:
S01, extract the sampling rate of logic module according to user's request setting data, and by this sampling rate, the digital signal exported from analog/digital conversion circuit is extracted, obtain low sampling rate data;
S02, control store select logic module to receive described low sampling rate data and high sampling rate data simultaneously;
S03, control store select logic module to export described low sampling rate data to store control logic module; The data received constantly are stored in data-carrier store by control store steering logic module;
Whether the data volume in S04, master control logic module Real-time Monitoring Data storer is less than the sampling number that user is arranged, if be less than, jumps to step S05, if be more than or equal to, jumps to step S08;
Whether the event needing high sampling rate to store that S05, master control logic module monitors user are arranged occurs: if event occurs, jump to step S06, if do not occur, still keep step S05 constant;
S06, control store select logic module to export the described high sampling rate data received to store control logic module;
Whether the memory length of S07, master control logic module monitors high sampling rate data reaches user arranges length: if reach, jump to step S03, if do not reach, still keep step S07 constant;
S08, control store steering logic module stop pending data being stored in data-carrier store, and this pair of sampling rate collection is deposited storing process and terminated.
The present invention has following beneficial effect:
(1) adopt system and method for the present invention can as far as possible long extend the sampling time while still can keep to paid close attention to details high time resolution (sampling rate is high), can contradiction between balanced sample time and sampling rate.
(2) the high and low two kinds of sampling rates in the present invention can be arranged according to user's actual need, and the trigger condition that the switching of sampling rate is arranged by user determines, automatically switches, makes this system easy to use.
Accompanying drawing explanation
Fig. 1 is data acquisition system (DAS) typical structure block diagram of the present invention;
Fig. 2 is dual seizure rate acquisition system data storage logic structured flowchart of the present invention;
Fig. 3 is dual seizure rate acquisition system data Stored Procedure block diagram of the present invention.
Embodiment
To develop simultaneously embodiment below in conjunction with accompanying drawing, describe the present invention.
In view of this, the invention provides a kind of data acquisition system (DAS) based on two sampling rate, data acquisition system (DAS) can be allowed to store the tendency of non-sensitive waveform compared with low sampling rate, the trigger condition set by user, with high sampling rate storage trigger event, Wave data that is forward and backward or neighbouring a period of time can also occur simultaneously.The contradictory relation between sampling rate and sampling time effectively can be alleviated in application-specific scene.
Based on above-mentioned purpose, technical scheme of the present invention is: high sampling rate data stream is converted into low sampling rate data through data pick-up logic module, high sampling rate data and low sampling rate data stream access to store simultaneously selects logic module then to select one to be that data to be stored transfer to store control logic module via this logic, and data to be stored are stored in data-carrier store and complete two sampling rate storage by store control logic module.
As shown in Figure 1, a kind of data acquisition storage system based on two sampling rate, comprise: front end modulate circuit, analog/digital conversion circuit, Digital Logic control circuit and data-carrier store, wherein, external analog signal inputs to front end modulate circuit, again by analog/digital conversion circuit, Digital Logic control circuit, be stored in data-carrier store, Digital Logic control circuit connects modulate circuit simultaneously, analog/digital conversion circuit, data-carrier store play overall control action, and Digital Logic control circuit also connects host computer and carries out data interaction simultaneously.Above-mentioned control procedure runs among Digital Logic control circuit with the form of Digital Logic, as shown in Figure 2, Digital Logic control circuit selects logic module, store control logic module and master control logic module to form by data pick-up logic module, storage to its logical architecture.Whether the event needing high sampling rate to store that described master control logic module user is arranged occurs, if occurred, namely generates switching command, is sent to store to select logic module;
Described front end modulate circuit accepts the simulating signal of outside input, and after pre-service, deliver to analog/digital conversion circuit conversion is digital signal, and is defined as high sampling rate data; Wherein, the function of front end modulate circuit be the simulating signal of input data acquisition system (DAS) is amplified, is reduced, the operation such as filtering enables to input in analog/digital conversion circuit with suitable form the most.
The sampling rate that described digital decimation logic module sets according to user extracts the digital signal received from analog/digital conversion circuit, obtains low sampling rate data;
Whether the event needing high sampling rate to store that described master control logic module monitors user is arranged occurs, if occurred, namely generates switching command, is sent to store to select logic module; Monitor this high sampling rate memory length whether to meet the demands simultaneously, when meeting, generating and stopping acquisition instructions, be sent to store and select logic module; Wherein, after Digital Logic control circuit receives host computer instruction, also forward end modulate circuit, analog/digital conversion circuit transmit control signal, and enter for adjusting front end modulate circuit and analog/digital conversion circuit the duty that a user wants.
Described storage selects logic module to receive described low sampling rate data and high sampling rate data simultaneously, and proceed as follows according to the instruction received from master control logic module: when not receiving any instruction, export described low sampling rate data to store control logic module; When receiving switching command, export described high sampling rate data to store control logic module; When receiving stopping acquisition instructions, stopping sending described high sampling rate data to store control logic module, described low sampling rate data are inputed to store control logic module;
Described store control logic module exports the data selecting logic module to receive from storage to data storage and stores.
A kind of 100MSa/s to 10KSa/s variable sample rate data acquisition system (DAS) comprises: front end modulate circuit, analog/digital conversion circuit, Digital Logic control circuit and data-carrier store.Wherein, external analog input signal input to front end modulate circuit by analog/digital conversion circuit, Digital Logic control circuit, be stored in data-carrier store, Digital Logic control circuit connects modulate circuit simultaneously, analog/digital conversion circuit, data-carrier store play overall control action, and Digital Logic control circuit also connects host computer and carries out data interaction simultaneously.
This data acquisition system (DAS) memory span is fixed, and maximum support 1MSample sampled data stores.User is for storing input analog voltage signal waveform when not losing signal saltus step as far as possible for a long time while of resolution accuracy, arrange under this data acquisition system (DAS) works in dual seizure rate memory module, high capture rate is set to 100MSa/s, low capture rate is set to 10KSa/s, storage depth is set to 1MSample, high capture rate trigger pip is the saltus step of input voltage rising edge, and high capture rate every section memory point is 1KSample.
Based on data acquisition storage system of the present invention, present invention also offers a kind of data acquisition storage means based on two sampling rate, as shown in Figure 3, concrete steps are as follows:
Under S00, setting data acquisition system work in 100MSa/s high sampling rate, and by this sampling rate, the digital signal exported from analog/digital conversion circuit is extracted, obtain low sampling rate data;
It is 10KSa/s that S01, setting data extract the sampling rate exporting low sampling rate data;
S02, control store select logic module to receive described low sampling rate data and high sampling rate data simultaneously;
S03, control store select logic module to export described low sampling rate data to store control logic module; The data received constantly are stored in data-carrier store by control store steering logic module;
The monitoring of S04, master control logic has stored data volume and whether has been less than 1MSample, if be less than, jumps to S05, if be more than or equal to, jumps to S08;
Whether the event needing high sampling rate to store that S05, master control logic module monitors user are arranged occurs, and whether monitoring the saltus step of input voltage rising edge occurs, if event occurs, jumps to step S06, if do not occur, still keeps step S05 constant;
S06, control store select logic module to export the described high sampling rate data received to store control logic module;
Whether S07, master control logic monitoring high sampling rate memory length reaches 1KSample, if reach, jumps to step S03, if do not occur, still keeps step S07 constant;
S08, demanded storage steering logic stop data to be stored to be stored in storer, and this pair of sampling rate collection is deposited storing process and terminated.
In sum, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. the data acquisition storage system based on two sampling rate, it is characterized in that, comprise front end modulate circuit, analog/digital conversion circuit, Digital Logic control circuit and data-carrier store, wherein Digital Logic control circuit comprises again data pick-up logic module, stores and select logic module, store control logic module and master control logic module;
Described front end modulate circuit accepts the simulating signal of outside input, and after pre-service, deliver to analog/digital conversion circuit conversion is digital signal, and is defined as high sampling rate data;
The sampling rate that described digital decimation logic module sets according to user extracts the digital signal received from analog/digital conversion circuit, obtains low sampling rate data;
Whether the event needing high sampling rate to store that described master control logic module monitors user is arranged occurs, if occurred, namely generates switching command, is sent to store to select logic module; Monitor this high sampling rate memory length whether to meet the demands simultaneously, when meeting, generating and stopping acquisition instructions, be sent to store and select logic module;
Described storage selects logic module to receive described low sampling rate data and high sampling rate data simultaneously, and proceed as follows according to the instruction received from master control logic module: when not receiving any instruction, export described low sampling rate data to store control logic module; When receiving switching command, export described high sampling rate data to store control logic module; When receiving stopping acquisition instructions, stopping sending described high sampling rate data to store control logic module, described low sampling rate data are inputed to store control logic module;
Described store control logic module exports the data selecting logic module to receive from storage to data storage and stores.
2., based on a data acquisition storage means for system according to claim 1, it is characterized in that, concrete steps are as follows:
S01, extract the sampling rate of logic module according to user's request setting data, and by this sampling rate, the digital signal exported from analog/digital conversion circuit is extracted, obtain low sampling rate data;
S02, control store select logic module to receive described low sampling rate data and high sampling rate data simultaneously;
S03, control store select logic module to export described low sampling rate data to store control logic module; The data received constantly are stored in data-carrier store by control store steering logic module;
Whether the data volume in S04, master control logic module Real-time Monitoring Data storer is less than the sampling number that user is arranged, if be less than, jumps to step S05, if be more than or equal to, jumps to step S08;
Whether the event needing high sampling rate to store that S05, master control logic module monitors user are arranged occurs: if event occurs, jump to step S06, if do not occur, still keep step S05 constant;
S06, control store select logic module to export the described high sampling rate data received to store control logic module;
Whether the memory length of S07, master control logic module monitors high sampling rate data reaches user arranges length: if reach, jump to step S03, if do not reach, still keep step S07 constant;
S08, control store steering logic module stop pending data being stored in data-carrier store, and this pair of sampling rate collection is deposited storing process and terminated.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107576988A (en) * | 2017-09-29 | 2018-01-12 | 中国科学院地质与地球物理研究所 | A kind of spaceborne magnetometer sample rate automatic switching method and device |
| CN112235705A (en) * | 2020-10-13 | 2021-01-15 | 恒玄科技(上海)股份有限公司 | Double-ear hearing aid |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6671755B1 (en) * | 1999-05-24 | 2003-12-30 | Forfàs | System for data capture from a rotor |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
| CN102945095A (en) * | 2012-11-08 | 2013-02-27 | 山东大学 | Quick gesture judgment method for Android embedded touch screen equipment |
-
2015
- 2015-12-21 CN CN201510962325.2A patent/CN105426132B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6671755B1 (en) * | 1999-05-24 | 2003-12-30 | Forfàs | System for data capture from a rotor |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
| CN102945095A (en) * | 2012-11-08 | 2013-02-27 | 山东大学 | Quick gesture judgment method for Android embedded touch screen equipment |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107576988A (en) * | 2017-09-29 | 2018-01-12 | 中国科学院地质与地球物理研究所 | A kind of spaceborne magnetometer sample rate automatic switching method and device |
| CN112235705A (en) * | 2020-10-13 | 2021-01-15 | 恒玄科技(上海)股份有限公司 | Double-ear hearing aid |
| CN112235705B (en) * | 2020-10-13 | 2022-05-10 | 恒玄科技(上海)股份有限公司 | Double-ear hearing aid |
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