CN105137141A - Hand-held oscilloscope - Google Patents
Hand-held oscilloscope Download PDFInfo
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- CN105137141A CN105137141A CN201510622274.9A CN201510622274A CN105137141A CN 105137141 A CN105137141 A CN 105137141A CN 201510622274 A CN201510622274 A CN 201510622274A CN 105137141 A CN105137141 A CN 105137141A
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Abstract
The invention belongs to the electronic measuring instrument field and especially relates to a hand-held oscilloscope. The oscilloscope comprises a box body, a signal interface, a circuit system and a button system. The circuit system comprises a control system, a display, a cell and an attenuator. The cell is connected to a power supply circuit so as to provide power for a whole circuit system. The attenuator receives a signal input from a signal interface and is connected to an amplifier. The amplifier is connected to a mode switching circuit and a trigger circuit. The mode switching circuit is connected to an AD converter. The AD converter converts an analog signal into a digital quantity and is stored in a memory. The memory caches data and then is sent to the control system so as to process. The control system processes the data according to an operation command of a user so that a function to be realized is displayed through a display. In the oscilloscope, a FPGA chip is taken as a core processor; the portable hand-held oscilloscope with a small size, convenient usage and low cost is provided.
Description
Technical field
The present invention relates to electronic measuring instrument field, particularly the hand-held oscillograph of one.
Background technology
Oscillograph is a kind of use electronic measuring instrument very widely, and it is mainly used in the measurement of various electric signal parameter, by invisible waveform image, thus makes people easily study the change procedure of electric signal.At present, the oscillograph numerous types on market, it adopts mesa structure substantially, and this structure makes oscillograph bulky, and user carries extremely inconvenient.And for general low-end subscribers, they only need the most frequently used basic function, function too much on oscillograph seems redundancy, function too much just makes complex structure, cost is high, an oscillographic price of least significant end is also at about 3000 yuan in the market, and this student being also vast low end client is such as engaged in newly manufacturing cannot bear.We can remove some unnecessary functions of existing oscillograph completely, simplify its structure, then optimization system designs thus designs a kind of low cost, and user carries, oscillograph easy to use.
Summary of the invention
The object of the invention is to the defect for prior art and deficiency, there is provided one to carry, easy to use, hand-held oscillograph with low cost, it not only has the signals collecting measurement function of ordinary oscilloscope, can also a function signal generator be used as, produce the waveform of difformity and frequency.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is: a kind of hand-held oscillograph, this oscillograph comprises the signaling interface 2 be installed on box body 1, Circuits System 3 and key system 4, described signaling interface 2 is connected with Circuits System 3 respectively with key system 4, described Circuits System 3 comprises control system 5, display 6, battery 18, input signal processing unit and output signal processing unit, described display 6, input signal processing unit is connected with control system 5 respectively with output signal processing unit, described battery 18 powers to control system 5 by feed circuit 9, described input signal processing unit comprises the attenuator 8 connected successively, amplifier 10, mode switching circuit 11, AD converter 13 and DDR2 storer 14, described attenuator 8 is connected with signaling interface 2, described DDR2 storer 14 is connected with control system 5.
Described output signal processing unit comprises the D/A converter 15, amplitude regulating circuit 16 and the wave filter 17 that connect successively, and described D/A converter 15 is connected with control system 5, and described wave filter 17 is connected with signaling interface 2.
Described key system comprises adjusting knob 401, TRIGGER button 402, SAVE/SAMPLE button 403, METER button 404, SCOPE button 405, WAVE button 406, MENU button 407, direction key 408 and function key, described TRIGGER button 402 is connected with amplifier 10 by trigger circuit 12, described SAVE/SAMPLE button 403 is connected with mode switching circuit 11, described adjustment button 401 is connected with amplitude regulating circuit 16, described METER button 404, SCOPE button 405, WAVE button 406, MENU button 407, direction key 408 and function key are connected with control system 5 respectively.Described function key comprises F1 button 409, F2 button 410, F3 button 411 and F4 button 412, F1 button 409, F2 button 410, F3 button 411 are distributed in below display 6 with F4 button 412 successively, described MENU button 407, SCOPE button 405, METER button 404, WAVE button 406 are distributed on the right side of display 6 with TRIGGER button 402 successively, and described adjusting knob 401, SAVE/SAMPLE button 403 are distributed on the left of display 6 with direction key 408.
Described Circuits System 3 is arranged in box body 1; described display 6 is arranged on centre position, box body 1 front; described signaling interface 2 is arranged on the right side of box body 1; described box body 1 top right side is provided with hand strap 101 and switch 102; left side is provided with dog hole 103; described signaling interface 2 is provided with protective sleeve 201, and described protective sleeve 201 is provided with hook 202, and described box body 1 back side is provided with bracing frame 104.
Described signaling interface is provided with signal input port CH1203, signal input port CH2204, wave form output port 205, ground wire terminal 206 and two wave shape correcting terminals 207.
Described control system 5 comprises FPGA processor 7, oscillatory circuit 19, FLASH module 20 and SRAM reservoir 21, described FPGA processor 7 internal build has pll clock 701, for system provides reference clock, described FPGA processor 7 internal build has FIFO_A buffer module 702, FIFO_B buffer module 703 and RAM cache module 704, be used for realizing transmitting with the data of peripheral hardware, described FPGA processor 7 internal build has control top layer 705, operational order detects bottom 706 and funcall bottom 707, be used for the work of FPGA processor 7 control system, the internal logic of process data realizes, described FPGA processor 7 internal build has ROM waveform table 708, be used for depositing the data that waveform occurs.Described pll clock 701 sends into clock frequency division module 709 after frequency multiplication, described clock frequency division module 709 is for trigger circuit 12 and control top layer 705 and provide different clock sources, described operational order detects bottom 706 and communicates with key system 4, the command information that operational order detection bottom 706 receives key system 4 sends command process bottom 710 to, after described command process bottom 710 pairs of command informations carry out classification process, be transferred to and control top layer 705, control top layer 705 and command information is transferred to funcall bottom 707, funcall bottom 707 drive waveforms generation bottom 711, oscilloscope display bottom 712, multimeter display bottom 713, function signal generator display bottom 714, menu interface display bottom 715, Waveform storage display bottom 716 drives bottom 717 to work with peripheral hardware.Described peripheral hardware drives bottom 717 to drive D/A converter 15, AD converter 13 and DDR2 storer 14 to work, described waveform generation bottom 711 reads the Wave data of ROM waveform table 708, by data stored in RAM cache module 704, RAM cache module 704 transfers data to D/A converter 15, carries out data communication between described Waveform storage display bottom 716 and DDR2 storer 14.Described oscilloscope display bottom 712, multimeter display bottom 713, function signal generator display bottom 714, menu interface display bottom 715 and Waveform storage show bottom 716 all by data stored in FIFO_B buffer module 703, FIFO_B buffer module 703 transfers data to SRAM memory 21, SRAM memory 21 transfers data to display 6 again, oscilloscope display bottom 712, multimeter display bottom 713, function signal generator display bottom 714, menu interface display bottom 715 shows bottom 716 with Waveform storage and is all connected with Display Driver bottom 718, Display Driver bottom 718 driving display 6 works.
Beneficial effect of the present invention is: the present invention is by simplifying structure, optimization system designs, design the oscillograph that a kind of box body shape is hand-holdable, its compact, user carry, easy to use, owing to adopting fpga chip as control system, under the disposition of mass data, greatly reduce production cost in satisfied high speed, make it possess the very strong market competitiveness, and the present invention integrates the function of oscillograph function signal generator, there is wider usable range.
Accompanying drawing explanation
Below the content expressed by this Figure of description and the mark in figure are briefly described:
Fig. 1 is the structural representation of the specific embodiment of the present invention.
Fig. 2 is the structural representation put on after protective sleeve of the specific embodiment of the present invention.
Fig. 3 is the structure schematic diagram of the specific embodiment of the present invention.
Fig. 4 is the theory diagram of the Circuits System of the specific embodiment of the present invention.
Fig. 5 is the theory diagram of the control system of the specific embodiment of the present invention.
In figure: 1-box body; 2-signaling interface; 3-Circuits System; 4-key system; 5-control system; 6-display; 7-FPGA processor; 8-attenuator; 9-feed circuit; 10-amplifier; 11-mode switching circuit; 12-trigger circuit; 13-high-speed A/D converter; 14-DDR2 storer; 15-high speed D/A converter; 16-amplitude regulating circuit; 17-wave filter; 18-battery; 19-oscillatory circuit; 20-FLASH module; 21-SRAM reservoir; 101-hand strap; 102-switch; 103-dog hole; 104-bracing frame; 201-protective sleeve; 202-hook; 203-signal input port CH1; 204-signal input port CH2; 205-wave form output port; 206-ground wire terminal; 207-wave shape correcting terminal; 401-adjusting knob; 402-TRIGGER button; 403-SAVE/SAMPLE button; 404-METER button; 405-SCOPE button; 406-WAVE button; 407-MENU button; 408-direction key; 409-F1 button; 410-F2 button; 411-F3 button; 412-F4 button; 701-pll clock; 702-FIFO_A buffer module; 703-FIFO_B buffer module; 704-RAM cache module; 705-control top layer; 706-operational order detects bottom; 707-funcall bottom; 708-ROM waveform table; 709-clock frequency division module; 710-command process bottom; 711-waveform generation bottom; 712-oscilloscope display bottom; 713-multimeter display bottom; 714-function signal generator display bottom; 715-menu interface display bottom; 716-Waveform storage display bottom; 717-peripheral hardware drives bottom; 718-Display Driver bottom.(original waveform generation bottom label has problems, and changes)
Embodiment
Contrast accompanying drawing below, by the description to embodiment, the specific embodiment of the present invention is as the effect of the mutual alignment between the shape of involved each component, structure, each several part and annexation, each several part and principle of work, manufacturing process and operation using method etc., be described in further detail, have more complete, accurate and deep understanding to help those skilled in the art to inventive concept of the present invention, technical scheme.
As shown in Figures 1 to 5, the hand-held oscillograph of one of the present invention, comprise the signaling interface 2 be installed on box body 1, Circuits System 3 and key system 4, described signaling interface 2 is connected with Circuits System 3 respectively with key system 4, described Circuits System 3 comprises control system 5, display 6, battery 18, input signal processing unit and output signal processing unit, described display 6, input signal processing unit is connected with control system 5 respectively with output signal processing unit, described battery 18 powers to control system 5 by feed circuit 9, described input signal processing unit comprises the attenuator 8 connected successively, amplifier 10, mode switching circuit 11, AD converter 13 and DDR2 storer 14, described attenuator 8 is connected with signaling interface 2, described DDR2 storer 14 is connected with control system 5.
Further, described control system is connected with high speed D/A converter 15, described high speed D/A converter 15 carries out outputting analog signal after digital-to-analog conversion, and it is connected with amplitude regulating circuit 16, described amplitude regulating circuit 16 is connected with wave filter 17, after simulating signal carries out output amplitude adjustment by amplitude regulating circuit 16, then exported by signaling interface 2 after wave filter 17 smothing filtering.
Described key system 4 communicates with control system 5, worked by input operation command control circuit system 3, it comprises adjusting knob 401, TRIGGER button 402, SAVE/SAMPLE button 403, METER button 404, SCOPE button 405, WAVE button 406, MENU button 407, direction key 408 and four function button F1 buttons 409, F2 button 410, F3 button 411 and F4 buttons 412.
Described adjusting knob 401 is connected with amplitude regulating circuit 16, for the signal amplitude that span of control limit of control regulating circuit 16 exports, described TRIGGER button 402 is connected with trigger circuit 12, for the work of control triggering electric circuit 12, described SAVE/SAMPLE button 403 is connected with mode switching circuit 11, for signal sampling and the memory function of switched system.
Described box body 1 is in cuboidal configuration; described Circuits System 3 is arranged in box body 1; described display 6 is arranged on box body 1 middle position; described signaling interface 2 is arranged on the right side of box body 1; described box body 1 top right side is connected with hand strap 101 and switch 102; left side is connected with dog hole 103; described signaling interface 2 is connected with protective sleeve 201; described protective sleeve 201 is connected with hook 202; when not using, protective sleeve 201 covers signaling interface; hook 202 hooks dog hole 103 and prevents it from dropping, and described box body 1 back side is connected with bracing frame 104.
Described signaling interface 2 is connected with signal input port CH1203, signal input port CH2204, wave form output port 205, ground wire terminal 206 and two wave shape correcting terminals 207.
Described four function button F1 buttons 409, F2 button 410, F3 button 411 are distributed in below display 6 with F4 button 412 successively, described MENU button 407, SCOPE button 405, METER button 404, WAVE button 406 are distributed on the right side of display 6 with TRIGGER button 402 successively, and described adjusting knob 401, SAVE/SAMPLE button 403 are distributed on the left of display 6 with direction key 408.
Described control system 5 comprises FPGA processor 7, oscillatory circuit 19, FLASH module 20 and SRAM reservoir 21, described FPGA processor 7 internal build has pll clock 701, for system provides reference clock, described FPGA processor 7 internal build has FIFO_A buffer module 702, FIFO_B buffer module 703 and RAM cache module 704, be used for realizing transmitting with the data of peripheral hardware, described FPGA processor 7 internal build has control top layer 705, operational order detects bottom 706 and funcall bottom 707, be used for the work of FPGA processor 7 control system, the internal logic of process data realizes, described FPGA processor 7 internal build has ROM waveform table 708, be used for depositing the data that waveform occurs.
Described pll clock 701 sends into clock frequency division module 709 after frequency multiplication, described clock frequency division module 709 is for trigger circuit 12 and control top layer 705 and provide different clock sources, described operational order detects bottom 706 and communicates with key system 4, its command information receiving key system 4 sends command process bottom 710 to, after described command process bottom 710 pairs of command informations carry out classification process, be transferred to and control top layer 705, control top layer 705 and command information is transferred to funcall bottom 707, funcall bottom 707 drive waveforms generation bottom 711, oscilloscope display bottom 712, multimeter display bottom 713, function signal generator display bottom 714, menu interface display bottom 715, Waveform storage display bottom 716 drives bottom 717 to work with peripheral hardware, realize corresponding function.
Described peripheral hardware drives bottom 717 to drive high speed D/A converter 15, high-speed A/D converter 13 and DDR2 storer 14 to work, described waveform generation bottom 711 reads the Wave data of ROM waveform table 708, by data stored in RAM cache module 704, RAM cache module 704 transfers data to high speed D/A converter 15, there is data communication between described Waveform storage display bottom 716 and DDR2 storer 14.
Described oscilloscope display bottom 712, multimeter display bottom 713, function signal generator display bottom 714, menu interface display bottom 715 and Waveform storage show bottom 716 all by data stored in FIFO_B buffer module 703, FIFO_B buffer module 703 transfers data to SRAM memory 21, SRAM memory 21 transfers data to display 6 again, meanwhile, above-mentioned each bottom enable Display Driver bottom 718 driving display 6 works.
The present invention has the function that signal sampling stores display, voltage measurement display, waveform generation.
During use, user's right hand inserts between box body and hand strap, hold on the right side of box body, after opening switch, system enters duty, use oscilloprobe access signaling interface to carry out signal sampling storage to show with voltage measurement, the signal input port CH1 on signaling interface and signal input port CH2 is for the invention provides two paths of signals Measurement channel; Wave form output port access function signal generator probe on signaling interface realizes the output that waveform occurs; Display is used for doing system interface, it shows the operational order of various input and the display of completion system required function, key system is used as the guidance panel of system, when pressing MENU button, carry out system interface menu setting, function button F1 button, F2 button, F3 button and F4 button have been used for corresponding menucommand and have arranged; When pressing SCOPE button, system entering signal samples storage display state, press TRIGGER button triggering system collection signal, now SAVE/SAMPLE button can make system switch between signal sampling display and storage display two states, the upper and lower key of direction key can conditioning signal display time horizontal shift, left-right key can conditioning signal display time cycle; When pressing METER button, system enters voltage display measurement state, and display directly shows surveyed magnitude of voltage, does not need to read from waveform as oscillograph to calculate magnitude of voltage; Press WAVE button, system enters the state that waveform occurs, the amplitude of turn adjusting knob regulation output waveform, and display demonstrates amplitude and the frequency of occurred waveform, and now, direction key is used for the frequency of regulation output waveform; After finishing using; for preventing signaling interface covered with dust; short circuit is caused to Circuits System; user can use protective sleeve to cover signaling interface; when user does not want to use hand-held to hold box body; the bracing frame at the box body back side can be strutted to support box body, such the present invention just can place and use on the table.
The principle that signal sampling stores display is: the operational order of control system detects the operational order that bottom detects key system input in real time, after pressing SCOPE button, command process bottom detects bottom from operational order and obtains signal sampling memory command information, sent to control top layer, control top layer and send command information to funcall bottom, funcall bottom layer driving peripheral hardware drives bottom layer driving high-speed A/D converter and DDR2 memory operation, now because TRIGGER button is not also pressed, trigger circuit can not work, system can not collect signal data, after pressing TRIGGER button, trigger circuit are under the stabilizing clock source that clock frequency division module provides, guarantee that the frequency of system acquisition signal and the frequency of system works exist stable consistent difference, so just can accurately calculate signal collected frequency, now, the signal gathered inputs from signal input port CH1 or signal input port CH2, the signal of attenuator to input carries out necessary decay, be transferred to amplifier again to amplify, amplifier can improve the sensitivity of systems axiol-ogy signal, when trigger circuit are triggered, the signal gathered is transferred to high-speed A/D converter through mode switching circuit, mode switching circuit presses key control by SAVE/SAMPLE, this key is late for being defaulted as signal sampling display mode, system shows the waveform sampled in real time, after pressing, entering signal stores display mode, the waveform of storage of collected and then show, high-speed A/D converter carries out analog to digital conversion, the analog quantity of collection signal is converted to digital quantity stored in DDR2 storer, DDR2 storer is as data storing and impact damper, data after being changed by signal import the FIFO_A buffer module of control system into, FIFO_A buffer module funcall bottom enable under transfer data to oscilloscope display bottom or Waveform storage display bottom, oscilloscope display bottom or Waveform storage display bottom more enable FIFO_B buffer module transfer data to SRAM memory, SRAM memory is as the data buffer of display, effectively can alleviate the pressure that when a large amount of high-speed data shows, display faces, simultaneously, oscilloscope display bottom or Waveform storage display bottom call the work of Display Driver bottom layer driving display, with the sampling display of settling signal or Waveform storage display.
It is similar that the principle of voltage measurement display and signal sampling store the principle shown, because voltage measurement also belongs to the scope of signal measurement in essence, it is also gather required measuring voltage by means of signal input port CH1 or signal input port CH2, after pressing METER button, same as above, the magnitude of voltage gathered imports control system into, call multimeter display bottom by the funcall bottom in control system and demonstrate magnitude of voltage, with signal sampling store show time unlike, after pressing METER button, SAVE/SAMPLE button is invalid when pressing again, namely mode switching circuit does not work, system default is signal sampling display mode, now also need to press the enable trigger circuit work of TRIGGER button, system just can gather magnitude of voltage and show.
The principle that waveform occurs is: same as above, after pressing WAVE button, control top layer and receive waveform generation command information, command information is transferred to funcall bottom, funcall bottom calls the function that waveform generation bottom completes waveform generation, waveform generation bottom reads the Wave data deposited in advance from ROM waveform table, here we provide conventional triangular wave, sawtooth wave, sinusoidal wave waveform, the data read out are first through RAM cache module buffer memory, be transferred to high speed D/A converter again, funcall bottom calls peripheral hardware driving bottom high speed D/A converter and completes digital-to-analog conversion simultaneously, export corresponding waveform, direction key controls the frequency of output waveform, the amplitude of the waveform directly exported by high speed D/A converter is fixing, and amplitude is very little, in order to make the amplitude of output waveform adjustable and there is certain amplitude, amplitude regulating circuit is accessed after high speed D/A converter, the amplitude of amplitude regulating circuit regulates and is controlled by adjusting knob, waveform after amplitude modulation contains many noises, need by access wave filter level and smooth and filter out noise, wave filter is directly connected with wave form output port, by wave form output.
The Specifeca tion speeification that the present invention can reach through actual verification is as follows: the main performance that signal sampling stores display is, bandwidth: 60M; Maximum real-time sampling rate: 200MSa/s; Passage: 2; Store the degree of depth: 2Mpts; Vertical sensitivity 2mv/div to 5v/div.
The main performance of voltage measurement display is, DC voltage measurement scope: 60mv to 360v; Ac voltage measurement scope 60mv to 270v; DC voltage measurement error: 5% to 8%; Ac voltage measurement error: 8% to 10%.
The main performance that waveform occurs is, waveform catalog: triangular wave, and sawtooth wave is sinusoidal wave; Rate-adaptive pacemaker scope: 26Hz to 1.8MHz; Rate-adaptive pacemaker error: 2% to 3%; Amplitude output area: 0v to 5.00v; Amplitude output error: 2% to 5%.
In the present invention, the effect of members is as follows:
Described FPGA processor adopts the CycloneIV family chip EP4CE10F17C8N of ALTERA company, it contains 10320 logical blocks (LE), 414Kbits in-line memory, 23 embedded 18*18 multipliers, 2 general PLL, when meeting native system performance design, use this chip can be cost-saving, FPGA processor is the core of control system, is mainly used to the normal operation controlling whole system.
Described DDR2 reservoir adopts the MT47H64M16HR chip of company of Micron Technology of the U.S., its storage space can reach 1Gbit, and be the design of 16bit bus, inner flank speed can reach 400Mhz, DDR2 reservoir can the storage mass data of two-forty, plays the effect of data buffer storage and storage in systems in which.
The DA chip of described high speed D/A converter adopts DA9708, the A/D chip of described high-speed A/D converter adopts AD9208, high speed D/A converter Main Function has been digital-to-analog conversion, the digital quantity of reception is converted to analog quantity, the effect of high-speed A/D converter is contrary with it, mainly complete analog to digital conversion, convert the analog quantity received to digital quantity.
Described battery adopts rated voltage to be the rechargeable battery of 9V, and it provides electric energy for whole system.
Described feed circuit adopt Voltage stabilizing module composition, the 9V DC voltage of battery reduces and stable output 5V and 3.3V two-way voltage by it, and wherein 5V voltage is used for attenuator, amplifier, wave filter, high speed D/A converter, high-speed A/D converter and monitor power supply; 3.3V voltage is used for DDR2 storer, FPGA processor and FLASH module for power supply.
Described FLASH module adopts NorFlashS29GL128P chip, and its storage can reach 128MBit, is mainly used to store the program of FPGA processor and the data needed for initialization thereof, so just effectively can prevent the generation causing system data Loss because of power down.
Described oscillatory circuit adopts the passive crystal oscillator of 50Mhz to form, and it provides clock source for FPGA processor.Above by reference to the accompanying drawings to invention has been exemplary description; obvious specific implementation of the present invention is not subject to the restrictions described above; as long as have employed the improvement of the various unsubstantialities that method of the present invention is conceived and technical scheme is carried out; or design of the present invention and technical scheme directly applied to other occasion, all within protection scope of the present invention without to improve.The protection domain that protection scope of the present invention should limit with claims is as the criterion.
Claims (10)
1. a hand-held oscillograph, it is characterized in that, this oscillograph comprises the signaling interface (2) be installed on box body (1), Circuits System (3) and key system (4), described signaling interface (2) is connected with Circuits System (3) respectively with key system (4), described Circuits System (3) comprises control system (5), display (6), battery (18), input signal processing unit and output signal processing unit, described display (6), input signal processing unit is connected with control system (5) respectively with output signal processing unit, described battery (18) is powered to control system (5) by feed circuit (9), described input signal processing unit comprises the attenuator (8) connected successively, amplifier (10), mode switching circuit (11), AD converter (13) and storer (14), described attenuator (8) is connected with signaling interface (2), described storer (14) is connected with control system (5).
2. hand-held oscillograph according to claim 1, it is characterized in that: described output signal processing unit comprises the D/A converter (15), amplitude regulating circuit (16) and the wave filter (17) that connect successively, described D/A converter (15) is connected with control system (5), and described wave filter (17) is connected with signaling interface (2).
3. hand-held oscillograph according to claim 1, it is characterized in that: described key system comprises adjusting knob (401), TRIGGER button (402), SAVE/SAMPLE button (403), METER button (404), SCOPE button (405), WAVE button (406), MENU button (407), direction key (408) and function key, described TRIGGER button (402) is connected with amplifier (10) by trigger circuit (12), described SAVE/SAMPLE button (403) is connected with mode switching circuit (11), described adjustment button (401) is connected with amplitude regulating circuit (16), described METER button (404), SCOPE button (405), WAVE button (406), MENU button (407), direction key (408) and function key are connected with control system (5) respectively.
4. hand-held oscillograph according to claim 3, it is characterized in that: described function key comprises F1 button (409), F2 button (410), F3 button (411) and F4 button (412), F1 button (409), F2 button (410), F3 button (411) and F4 button (412) are distributed in display (6) below successively, described MENU button (407), SCOPE button (405), METER button (404), WAVE button (406) and TRIGGER button (402) are distributed in display (6) right side successively, described adjusting knob (401), SAVE/SAMPLE button (403) and direction key (408) are distributed in display (6) left side.
5. hand-held oscillograph according to claim 1, it is characterized in that: described Circuits System (3) is arranged in box body (1), described display (6) is arranged on box body (1) centre position, front, described signaling interface (2) is arranged on box body (1) right side, described box body (1) top right side is provided with hand strap (101) and switch (102), left side is provided with dog hole (103), described signaling interface (2) is provided with protective sleeve (201), described protective sleeve (201) is provided with hook (202), described box body (1) back side is provided with bracing frame (104).
6. hand-held oscillograph according to claim 1, is characterized in that: described signaling interface is provided with signal input port CH1 (203), signal input port CH2 (204), wave form output port (205), ground wire terminal (206) and two wave shape correcting terminals (207).
7. hand-held oscillograph according to claim 1, it is characterized in that: described control system (5) comprises FPGA processor (7), oscillatory circuit (19), FLASH module (20) and SRAM reservoir (21), described FPGA processor (7) internal build has pll clock (701), for system provides reference clock, described FPGA processor (7) internal build has FIFO_A buffer module (702), FIFO_B buffer module (703) and RAM cache module (704), be used for realizing transmitting with the data of peripheral hardware, described FPGA processor (7) internal build has control top layer (705), operational order detects bottom (706) and funcall bottom (707), be used for FPGA processor (7) control system work, the internal logic of process data realizes, described FPGA processor (7) internal build has ROM waveform table (708), be used for depositing the data that waveform occurs.
8. hand-held oscillograph according to claim 7, it is characterized in that: described pll clock (701) sends into clock frequency division module (709) after frequency multiplication, described clock frequency division module (709) for trigger circuit (12) and control top layer (705) different clock sources is provided, described operational order detects bottom (706) and communicates with key system (4), the command information that operational order detects bottom (706) reception key system (4) sends command process bottom (710) to, after described command process bottom (710) carries out classification process to command information, be transferred to and control top layer (705), control top layer (705) and command information is transferred to funcall bottom (707), funcall bottom (707) drive waveforms generation bottom (711), oscilloscope display bottom (712), multimeter display bottom (713), function signal generator display bottom (714), menu interface display bottom (715), Waveform storage display bottom (716) and peripheral hardware drive bottom (717) to work.
9. hand-held oscillograph according to claim 8, it is characterized in that: described peripheral hardware drives bottom (717) to drive D/A converter (15), AD converter (13) and storer (14) to work, described waveform generation bottom (711) reads the Wave data of ROM waveform table (708), by data stored in RAM cache module (704), RAM cache module (704) transfers data to D/A converter (15), carries out data communication between described Waveform storage display bottom (716) and storer (14).
10. hand-held oscillograph according to claim 8, it is characterized in that: described oscilloscope display bottom (712), multimeter display bottom (713), function signal generator display bottom (714), menu interface display bottom (715) with Waveform storage show bottom (716) all by data stored in FIFO_B buffer module (703), FIFO_B buffer module (703) transfers data to SRAM memory (21), SRAM memory (21) transfers data to display (6) again, oscilloscope display bottom (712), multimeter display bottom (713), function signal generator display bottom (714), menu interface display bottom (715) and Waveform storage show bottom (716) and are all connected with Display Driver bottom (718), Display Driver bottom (718) driving display (6) works.
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| CN201510622274.9A CN105137141A (en) | 2015-09-24 | 2015-09-24 | Hand-held oscilloscope |
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| CN201510622274.9A CN105137141A (en) | 2015-09-24 | 2015-09-24 | Hand-held oscilloscope |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017152326A1 (en) * | 2016-03-06 | 2017-09-14 | 张舒维 | Internet of things-based novel oscilloscope |
| CN113917203A (en) * | 2021-09-29 | 2022-01-11 | 重庆电子工程职业学院 | Portable waveform test pen |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017152326A1 (en) * | 2016-03-06 | 2017-09-14 | 张舒维 | Internet of things-based novel oscilloscope |
| CN113917203A (en) * | 2021-09-29 | 2022-01-11 | 重庆电子工程职业学院 | Portable waveform test pen |
| CN113917203B (en) * | 2021-09-29 | 2023-05-02 | 重庆电子工程职业学院 | Portable waveform test pen |
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Application publication date: 20151209 |