CN105405756A - Method of improving low-dielectric film thickness stability - Google Patents
Method of improving low-dielectric film thickness stability Download PDFInfo
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- CN105405756A CN105405756A CN201510716938.8A CN201510716938A CN105405756A CN 105405756 A CN105405756 A CN 105405756A CN 201510716938 A CN201510716938 A CN 201510716938A CN 105405756 A CN105405756 A CN 105405756A
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 230000008569 process Effects 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 42
- 230000015572 biosynthetic process Effects 0.000 claims description 36
- 229910052710 silicon Inorganic materials 0.000 claims description 33
- 239000010703 silicon Substances 0.000 claims description 33
- 230000006872 improvement Effects 0.000 claims description 10
- 238000000205 computational method Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 abstract 3
- 238000004364 calculation method Methods 0.000 abstract 1
- 238000005755 formation reaction Methods 0.000 description 39
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000013480 data collection Methods 0.000 description 3
- HMMGMWAXVFQUOA-UHFFFAOYSA-N octamethylcyclotetrasiloxane Chemical compound C[Si]1(C)O[Si](C)(C)O[Si](C)(C)O[Si](C)(C)O1 HMMGMWAXVFQUOA-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Vapour Deposition (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention relates to the field of semiconductors, and particularly relates to a method of improving low-dielectric film thickness stability. The method is applied to a formula for a multi-wafer film forming process. The method comprises steps: the average film forming time and the average film forming rate for each wafer group are collected; according to the collected average film forming time and the average film forming rate, the compensation time for each wafer group is calculated according to a calculation method; and the film forming time and the compensation time for a corresponding group are added to obtain the new film forming time for each group, and according to the new film forming time, the film forming process is carried out on the wafers.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to a kind of method improving low dielectric film thickness stability.
Background technology
Low dielectric medium (Lowk) film is mainly used in the dielectric substance layer of back segment, general use octamethylcy-clotetrasiloxane (OMCTS) and oxygen (O2) are as main reactant reaction film forming, be liquid condition under OMCTS normal temperature and pressure, film formation reaction is very sensitive to temperature.Reaction cavity (Processchamber) is after setting up atmosphere, comprising Goclean, periodicclean, season, wait for the film-forming process time started longer (processchamberidle), fewer in the amount of wafer surface filming, the thickness on wafer is thinning, wherein, wait for that film-forming process time started and thickness relation are as Fig. 1.
ProducerGT equipment is that AMAT company is used in the technologic ripe product of Lowk.The reaction cavity film formation reaction formula of this equipment is divided into monolithic film formation reaction mode and multi-disc film formation reaction mode according to film forming thickness.For the technique of multi-disc film formation reaction mode, when equipment is at three technique processchamber while during film forming, due to the reason that silicon chip (wafer) transmits, processchamber may have a long period and wait for that wafer enters processchamber and starts film-forming process after the film formation reaction of goclean or periodicclean completes, cause film forming on wafer partially thin, very large negatively influencing is had to the stability of product and electric performance test, even has influence on product yield.
As shown in Figures 2 and 3, in multi-disc film formation reaction formula, sheet numbers different after film formation reaction also can cause different-thickness to affect, with
3pcs1clean is the thickness formula of example is that the historical record that example is worked continuously is checked, processchamber has the beginning film-forming process time in various degree, and the film forming thickness of correspondence also has corresponding on the low side, i.e. the less stable of film thickness.
Summary of the invention
The defect such as the film thickness caused for the stand-by period in the medium technique to be filmed of prior art is on the low side, the present invention devises a kind of method improving low dielectric film thickness stability, the method increases the stability of film.
The present invention adopts following technical scheme:
Improve a method for low dielectric film thickness stability, be applied in the formula of many silicon chips film-forming process, described method comprises:
Collect and often organize the average film formation time of silicon chip and average rate of film build;
According to the described average film formation time collected and average rate of film build, calculate the make-up time often organizing silicon chip according to computational methods;
The described make-up time of described film formation time with corresponding group is added, is often organized new film formation time, and
According to described new film formation time, film-forming process is carried out to silicon chip.
Preferably, described many silicon chips film-forming process comprises three groups of silicon chips.
Preferably, the mean value of the film formation time of first group of silicon chip is datum line; The mean value of the film formation time of second group of silicon chip is t2; The mean value of the film formation time of the 3rd group of silicon chip is t3.
Preferably, the average rate of film build of described first group, second group, the 3rd group silicon chip is Vd.
Preferably, calculate the film formation time compared to datum line according to average rate of film build Vd, often exceed the film forming thickness of described Preset Time on silicon chip and reduce
Preferably, described Preset Time is 10s.
Preferably, the make-up time Δ t1=0 second of described first group of silicon chip.
Preferably, make-up time Δ t2=(the t2/10) × T of described second group of silicon chip.
Preferably, make-up time Δ t3=(the t3/10) × T of described 3rd group of silicon chip.
The invention has the beneficial effects as follows:
The stand-by period of the present invention to the beginning film-forming process that silicon chip transmission causes is longer, thus the situation causing film thickness on the low side, by the continuous improvement to film forming formula, the stand-by period is reduced the impact of film forming thickness stability, improve the stability of thickness.The present invention, according to the Changing Pattern of process cavity along with the time of film formation reaction, compensates the film formation time of different film formation reaction, and final film forming thickness can be stabilized in a less scope, has castering action to the yield stability of semiconductor simultaneously.
Accompanying drawing explanation
Fig. 1 is film formation time and thickness relation in prior art of the present invention;
Fig. 2 is the film formation time schematic diagram of continuous silicon chip in prior art of the present invention;
Fig. 3 is the thickness schematic diagram of continuous silicon chip in prior art of the present invention;
Fig. 4 is the relation schematic diagram of thickness of the present invention and film formation time;
Fig. 5 is the relation schematic diagram of the sheet number of silicon chip in film formation time of the present invention and film-forming process.
Embodiment
It should be noted that, when not conflicting, following technical proposals, can combine between technical characteristic mutually.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
The present invention mainly solve large-scale production manufacture in low-kBD1 processing procedure silicon chip transmission between film forming thickness stability problem.For the situation of many silicon chips film-forming process, when silicon chip (wafer) is worked continuously, board can enter the situation of a circulation, and along with the technique of wafer is carried out, the hardware action of board and the circulation of technique formula are carried out.By the history data collection to operation, analyze job history data, find out the circulation law about film forming dead time (building up film formation time, the idle time) and cleancount.For the wafer of same cleancount, according to the data of idle time (as long as wafer carries out technique continuously, data just circulate always), and calculate the mean value of the idle time of the silicon chip sheet number (cleancount) in same many silicon chips film-forming process.Film forming thickness on Wafer also changes along with the change of idle time, and the idle time is elongated, namely away from datum line (baseline), wafer become thickness thinning, the idle time shortens, namely close to the upper film forming of baseline, wafer just close to baseline.The compensation of film formation time is carried out to the wafer of cleancount in same many silicon chips film-forming process, the film formation time compensated is calculated (average idle time) by the mean value of idle time, data determine the film forming thickness on the wafer surface that the average idle time can reduce by experiment, in conjunction with actual rate of film build, the film formation time needing to compensate just can be calculated.After compensating the film formation time of cleancount, originally the film forming thickness of the idle wafer of baseline around just increases to some extent, and the original idle time also increased to some extent away from the film forming thickness of the wafer of baseline.Although film forming thickness both increases, the gap of film forming thickness can diminish, and particularly there will be no the wafer that film forming thickness is low especially.Overall wafer thickness convergence is better.
Fig. 4 is the relation schematic diagram of thickness of the present invention and film formation time; As shown in Figure 4, by the adjustment of operation formula, with
formula 3pcs periodicclean is example, and film forming thickness than is originally restrained more, as Fig. 4.Decrease product and exceed the situation that control line (OOC, OutOfControl) even exceeds specification (OOS, OutOfSpecification), enhance product stability.
Fig. 5 is the relation schematic diagram of the sheet number of silicon chip in film formation time of the present invention and film-forming process, as shown in Figure 5, according to the historical data of film forming operation, finds out the rule of film forming during operation, Using statistics method, the situation of film forming is done to the compensation of corresponding film formation time.Need to carry out Data Collection and formula and revise two main steps.
First: Data Collection, according to the historical data of actual film forming operation, be summarized as membrane process (processchamberidle) time, obtain the relation of idle time and cleancount, see Fig. 5.The mean value of an idle time is found out from the relation of idle time and cleancount, more than first group, silicon chip film-forming process (is called for short first group, idle time average by that analogy) is set as baseline, the average idle time of second group is t2, and the average idle time of the 3rd group is t3.Simultaneously, average rate of film build (deprate) Vd of collection chamber (processchamber), and the relation of idle time and wafer film forming thickness, what calculate is than the relation of baseline more than idle time and thickness herein, namely more every than baseline many idle time 10 seconds then on wafer film forming thickness reduce
10s is selected to be because generally want idle10 just can have obvious thickness downward trend above second.
Second: formula amendment and maintaining method, calculate according to the mean value of the idle time calculated and current deprate the time Δ t that the film formation time often organizing cleancount needs to compensate.Former film formation time adding, the correspondence of calculating often organizes make-up time corresponding to cleancount, is new film formation time.Make-up time is a difference, when normal adjustment film formation time, needs to keep this difference between each group of cleancount.When daily monitoring (monitor), the time of processchamberidle is different with when working continuously, so the data of daily display (monitor) are just as a reference.
As mentioned above, the computational methods often organizing the make-up time are:
The idle time of first group of wafer is the idle time of baseline, so Δ t1=0 second;
The average idle time of second group of wafer is t2, Δ t2=(t2/10) × T;
The average idle time of the 3rd group of wafer is t3, Δ t3=(t3/10) × T.
In sum, the stand-by period of the present invention to the beginning film-forming process that silicon chip transmission causes is longer, thus the situation causing film thickness on the low side, by the continuous improvement to film forming formula, stand-by period is reduced the impact of film forming thickness stability, improves the stability of thickness.The present invention, according to the Changing Pattern of process cavity along with the time of film formation reaction, compensates the film formation time of different film formation reaction, and final film forming thickness can be stabilized in a less scope, has castering action to the yield stability of semiconductor simultaneously.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (9)
1. improve a method for low dielectric film thickness stability, it is characterized in that, be applied in the formula of many silicon chips film-forming process, described method comprises:
Collect and often organize the average film formation time of silicon chip and average rate of film build;
According to the described average film formation time collected and average rate of film build, calculate the make-up time often organizing silicon chip according to computational methods;
The described make-up time of described film formation time with corresponding group is added, is often organized new film formation time, and
According to described new film formation time, film-forming process is carried out to silicon chip.
2. the method for the low dielectric film thickness stability of improvement according to claim 1, is characterized in that, described many silicon chips film-forming process comprises three groups of silicon chips.
3. the method for the low dielectric film thickness stability of improvement according to claim 2, is characterized in that, the mean value of the film formation time of first group of silicon chip is datum line; The mean value of the film formation time of second group of silicon chip is t2; The mean value of the film formation time of the 3rd group of silicon chip is t3.
4. the method for the low dielectric film thickness stability of improvement according to claim 3, is characterized in that, the average rate of film build of described first group, second group, the 3rd group silicon chip is Vd.
5. the method for the low dielectric film thickness stability of improvement according to claim 4, is characterized in that, calculates the film formation time compared to datum line according to average rate of film build Vd, often exceedes the film forming thickness of described Preset Time on silicon chip and reduces
6. the method for the low dielectric film thickness stability of improvement according to claim 5, is characterized in that, described Preset Time is 10s.
7. the method for the low dielectric film thickness stability of improvement according to claim 6, is characterized in that, the make-up time Δ t1=0 second of described first group of silicon chip.
8. the method for the low dielectric film thickness stability of improvement according to claim 6, is characterized in that, make-up time Δ t2=(the t2/10) × T of described second group of silicon chip.
9. the method for the low dielectric film thickness stability of improvement according to claim 6, is characterized in that, make-up time Δ t3=(the t3/10) × T of described 3rd group of silicon chip.
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| CN201510716938.8A CN105405756B (en) | 2015-10-28 | 2015-10-28 | A kind of method for improving low dielectric film thickness stability |
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| CN105405756B CN105405756B (en) | 2018-06-19 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101231508A (en) * | 2008-01-17 | 2008-07-30 | 中电华清微电子工程中心有限公司 | Control method for fabrication technology of analysis estimation-correcting integrated circuit by time series |
| US20090170223A1 (en) * | 2007-12-27 | 2009-07-02 | Advanced Micro Devices, Inc. | Methods for calibrating a process for growing an epitaxial silicon film and methods for growing an epitaxial silicon film |
| CN102605351A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Method for resetting after LPCVD (low pressure chemical vapor deposition) maintenance |
| CN102800564A (en) * | 2011-05-26 | 2012-11-28 | 中国科学院微电子研究所 | Method and system for avoiding misoperation during debugging of semiconductor process menu |
| CN103436863A (en) * | 2013-08-15 | 2013-12-11 | 镇江大全太阳能有限公司 | Method for automatically generating tubular PECVD (Plasma Enhanced Chemical Vapor Deposition) coating time |
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- 2015-10-28 CN CN201510716938.8A patent/CN105405756B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090170223A1 (en) * | 2007-12-27 | 2009-07-02 | Advanced Micro Devices, Inc. | Methods for calibrating a process for growing an epitaxial silicon film and methods for growing an epitaxial silicon film |
| CN101231508A (en) * | 2008-01-17 | 2008-07-30 | 中电华清微电子工程中心有限公司 | Control method for fabrication technology of analysis estimation-correcting integrated circuit by time series |
| CN102800564A (en) * | 2011-05-26 | 2012-11-28 | 中国科学院微电子研究所 | Method and system for avoiding misoperation during debugging of semiconductor process menu |
| CN102605351A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Method for resetting after LPCVD (low pressure chemical vapor deposition) maintenance |
| CN103436863A (en) * | 2013-08-15 | 2013-12-11 | 镇江大全太阳能有限公司 | Method for automatically generating tubular PECVD (Plasma Enhanced Chemical Vapor Deposition) coating time |
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