CN105405756B - A kind of method for improving low dielectric film thickness stability - Google Patents
A kind of method for improving low dielectric film thickness stability Download PDFInfo
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- CN105405756B CN105405756B CN201510716938.8A CN201510716938A CN105405756B CN 105405756 B CN105405756 B CN 105405756B CN 201510716938 A CN201510716938 A CN 201510716938A CN 105405756 B CN105405756 B CN 105405756B
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- 238000000034 method Methods 0.000 title claims abstract description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 42
- 239000010703 silicon Substances 0.000 claims abstract description 42
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 38
- 238000000205 computational method Methods 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000005755 formation reaction Methods 0.000 description 34
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- HMMGMWAXVFQUOA-UHFFFAOYSA-N octamethylcyclotetrasiloxane Chemical compound C[Si]1(C)O[Si](C)(C)O[Si](C)(C)O[Si](C)(C)O1 HMMGMWAXVFQUOA-UHFFFAOYSA-N 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 238000013480 data collection Methods 0.000 description 2
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000007619 statistical method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Vapour Deposition (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The present invention relates to semiconductor applications more particularly to a kind of methods for improving low dielectric film thickness stability.The present invention is applied in the formula of more silicon chip film-forming process, and this method includes：Collect the average film formation time of every group of silicon chip and average rate of film build；According to the average film formation time of collection and average rate of film build, the compensation time of every group of silicon chip is calculated according to computational methods；Film formation time with corresponding group of compensation time is added, obtain every group of new film formation time and film-forming process is carried out to silicon chip according to new film formation time.
Description
Technical field
The present invention relates to semiconductor applications more particularly to a kind of methods for improving low dielectric film thickness stability.
Background technology
Low dielectric medium (Low k) film is mainly used in the dielectric substance layer of back segment, generally using octamethylcy-clotetrasiloxane
(OMCTS) it reacts and forms a film as main reactant with oxygen (O2), be liquid condition under OMCTS normal temperature and pressures, film formation reaction pair
Temperature is very sensitive.Reaction cavity (Process chamber) is after atmosphere is established, including Go clean, periodic
Clean, season wait for the film-forming process time started longer (process chamber idle), in wafer surface filmings
Amount is fewer, and the film thickness on wafer is thinning, wherein, wait for film-forming process time started and film thickness relationship such as Fig. 1.
Producer GT equipment is that AMAT companies are used in the technologic ripe product of Low k.The reaction of the equipment
Cavity film formation reaction formula is divided into monolithic film formation reaction mode and multi-disc film formation reaction mode according to film forming thickness.For multi-disc into
The technique of film reaction mode, when equipment is when three technique process chamber form a film simultaneously, since silicon chip (wafer) passes
The reason of sending, process chamber might have after the completion of the film formation reaction of go clean or periodic clean compared with
Fall into a long wait wafer and enter process chamber and start film-forming process, cause to form a film on wafer partially thin, to the steady of product
Qualitative and electric performance test has very big negatively influencing or even influences product yield.
As shown in Figures 2 and 3, in multi-disc film formation reaction formula, different the piece numbers will also result in different thickness after film formation reaction
Degree influences, withThe historical record worked continuously for film thickness formula for 3pcs1clean checks, process
Chamber has the different degrees of beginning film-forming process time, and corresponding film forming thickness also has corresponding relatively low, i.e. film thickness
The stability of degree is poor.
Invention content
For in the prior art wait for film-forming process in stand-by period caused by film thickness it is relatively low the defects of, this hair
Bright to devise a kind of method for improving low dielectric film thickness stability, the method increase the stability of film.
The present invention adopts the following technical scheme that：
A kind of method for improving low dielectric film thickness stability, in the formula applied to more silicon chip film-forming process, institute
The method of stating includes：
Collect the average film formation time of every group of silicon chip and average rate of film build；
According to the average film formation time of collection and average rate of film build, every group of silicon chip is calculated according to computational methods
Compensate the time；
The film formation time is added with corresponding group of compensation time, obtain every group of new film formation time and
Film-forming process is carried out to silicon chip according to the new film formation time.
Preferably, more silicon chip film-forming process include three groups of silicon chips.
Preferably, line on the basis of the average value of the film formation time of first group of silicon chip；The film formation time of second group of silicon chip is put down
Mean value is t2；The average value of the film formation time of third group silicon chip is t3.
Preferably, described first group, second group, the average rate of film build of third group silicon chip be Vd.
Preferably, film formation time compared to datum line is calculated according to average rate of film build Vd, when often default more than one
Between film forming thickness on silicon chip reduce
Preferably, the preset time is 10s.
Preferably, the Δ t1=0 seconds compensation time of first group of silicon chip.
Preferably, compensation time Δ t2=(t2/10) × T of second group of silicon chip.
Preferably, compensation time Δ t3=(t3/10) × T of the third group silicon chip.
The beneficial effects of the invention are as follows：
The present invention starts film-forming process stand-by period caused by being transmitted to silicon chip is longer, relatively low so as to cause film thickness
Situation, by the continuous improvement to the formula that forms a film, influence of the stand-by period to film forming thickness stability is reduced, improves film thickness
Stability.The present invention according to process cavity with the changing rule of the time of film formation reaction, to the film forming of different film formation reactions
Time compensates, and final film forming thickness can be stablized in a smaller range, while has to the yield stability of semiconductor
Castering action.
Description of the drawings
Fig. 1 is film formation time and film thickness relationship in the prior art of the invention；
Fig. 2 is the film formation time schematic diagram of present invention silicon chip continuous in the prior art；
Fig. 3 is the film thickness schematic diagram of present invention silicon chip continuous in the prior art；
Fig. 4 is the relation schematic diagram of film thickness of the present invention and film formation time；
Fig. 5 is film formation time of the present invention and the relation schematic diagram of the piece number of silicon chip in film-forming process.
Specific embodiment
It should be noted that in the absence of conflict, following technical proposals can be combined with each other between technical characteristic.
The specific embodiment of the present invention is further described below in conjunction with the accompanying drawings：
Present invention mainly solves film forming thickness stability between the transmission of low-k BD1 processing procedure silicon chips in mass production
Problem.In the case of more silicon chip film-forming process, when silicon chip (wafer) is worked continuously, board can enter the situation of a cycle,
It is carried out with the technique of wafer, hardware action and technique the formula cycle of board carry out.It is received by the historical data to operation
Collection analyzes job history data, finds out about film forming dead time (building up film formation time, idle times) and clean count
Circulation law.For the wafer of same clean count, according to the data of idle times (as long as wafer is carried out continuously work
Skill, data just recycle always), and when calculating the idle of silicon chip the piece number (clean count) in same more silicon chip film-forming process
Between average value.Film forming thickness on Wafer changes also with the variation of idle times, and the idle times are elongated, i.e., far from base
Directrix (baseline), wafer is upper thinning into film thickness, and the idle times shorten, i.e., close to baseline, forms a film on wafer and just connect
Nearly baseline.The compensation of film formation time is carried out to the wafer of clean count in same more silicon chip film-forming process, compensation
Film formation time calculates (average idle times) by the average value of idle times, determines that the average idle times can subtract by experimental data
The film forming thickness on few wafer surfaces, with reference to practical rate of film build, it is possible to the film formation time for needing to compensate be calculated.
After the compensation of the film formation time of clean count, originally the idle times close to the wafer of baseline film forming thickness just
Increase, and the film forming thickness of original wafer of the idle times far from baseline also increased.Although film forming thickness all increases
, but the gap of film forming thickness can become smaller, the wafer that particularly there will be no film forming thickness especially low.Whole wafer
Thickness convergence is more preferable.
Fig. 4 is the relation schematic diagram of film thickness of the present invention and film formation time；As shown in figure 4, by the adjustment of operation formula, withFor periodic clean of formula 3pcs, film forming thickness than is originally more restrained, such as Fig. 4.Reduce product
Beyond control line (OOC, Out Of Control) or even the situation beyond specification (OOS, Out Of Specification), increase
Strong product stability.
Fig. 5 is the relation schematic diagram of the piece number of silicon chip in film formation time of the present invention and film-forming process, as shown in figure 5, according to
Form a film the historical data of operation, the rule to form a film during operation is found out, using statistical method, when doing corresponding film forming to the situation of film forming
Between compensation.It needs to carry out data collection and formula two main steps of modification.
First：Data collection according to the historical data of practical film forming operation, summarizes film-forming process (process chamber
Idle) the time obtains the relationship of idle times and clean count, referring to Fig. 5.From idle times and the pass of clean count
The average value of an idle times is found out in system, the idle of silicon chip film-forming process more than first group (referred to as first group, and so on)
Time average is set as baseline, and second group of average idle times are t2, and the average idle times of third group are t3.Together
When, average rate of film build (dep rate) Vd and idle times of collection chamber (process chamber) and wafer into
The relationship of film thickness, what is calculated herein is the relationship for being more than idle times and film thickness than baseline, i.e., more than baseline
Every 10 seconds of idle times, then film forming thickness was reduced on waferSelection 10s is because generally wanting idle10 seconds or more ability
There is apparent film thickness downward trend.
Second：Formula is changed and maintaining method, is counted according to the average value of the idle times of calculating and current dep rate
Calculate the time Δ t that the film formation time needs of every group of clean count compensate.Plus every group of the correspondence calculated on former film formation time
Clean count corresponding compensation times, as new film formation time.It is a difference to compensate the time, in normal adjustment film forming
During the time, need to keep this difference between each group clean count.At daily monitoring (monitor), process
The time of chamber idle is different with when working continuously, so the data of daily display (monitor) are intended only as one
With reference to.
As described above, the computational methods of every group of compensation time are：
The idle times of first group of wafer are the idle times of baseline, so Δ t1=0 seconds；
The average idle times of second group of wafer are t2, Δ t2=(t2/10) × T；
The average idle times of third group wafer are t3, Δ t3=(t3/10) × T.
In conclusion the present invention starts film-forming process stand-by period caused by being transmitted to silicon chip is longer, so as to cause thin
By the continuous improvement to the formula that forms a film, influence of the stand-by period to film forming thickness stability is dropped for the relatively low situation of film thickness
It is low, improve the stability of film thickness.The present invention according to process cavity with the changing rule of the time of film formation reaction, to different film forming
The film formation time of reaction compensates, and final film forming thickness can be stablized in a smaller range, while to the good of semiconductor
Rate stability has castering action.
By explanation and attached drawing, the exemplary embodiments of the specific structure of specific embodiment are given, based on essence of the invention
God can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard the whole variations and modifications of true intention and range for covering the present invention as.It is weighing
The range and content of any and all equivalence, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (5)
- A kind of 1. method for improving low dielectric film thickness stability, which is characterized in that applied to more silicon chip film-forming process In formula, the method includes：Collect the average film formation time of every group of silicon chip and average rate of film build；According to the average film formation time of collection and average rate of film build, the compensation of every group of silicon chip is calculated according to computational methods Time；The film formation time is added with corresponding group of compensation time, obtain every group of new film formation time andFilm-forming process is carried out to silicon chip according to the new film formation time；More silicon chip film-forming process include three groups of silicon chips；Line on the basis of the average value of the film formation time of first group of silicon chip；The average value of the film formation time of second group of silicon chip is t2；The The average value of the film formation time of three groups of silicon chips is t3；Described first group, second group, the average rate of film build of third group silicon chip be Vd；Film formation time compared to datum line is calculated according to average rate of film build Vd, often more than a preset time on silicon chip Film forming thickness is reduced
- 2. the method according to claim 1 for improving low dielectric film thickness stability, which is characterized in that described default Time is 10s.
- 3. the method according to claim 2 for improving low dielectric film thickness stability, which is characterized in that described first The Δ t1=0 seconds compensation time of group silicon chip.
- 4. the method according to claim 2 for improving low dielectric film thickness stability, which is characterized in that described second Compensation time Δ t2=(t2/10) × T of group silicon chip.
- 5. the method according to claim 2 for improving low dielectric film thickness stability, which is characterized in that the third Compensation time Δ t3=(t3/10) × T of group silicon chip.
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| CN105405756B true CN105405756B (en) | 2018-06-19 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101231508A (en) * | 2008-01-17 | 2008-07-30 | 中电华清微电子工程中心有限公司 | Control method for fabrication technology of analysis estimation-correcting integrated circuit by time series |
| CN102605351A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Method for resetting after LPCVD (low pressure chemical vapor deposition) maintenance |
| CN102800564A (en) * | 2011-05-26 | 2012-11-28 | 中国科学院微电子研究所 | Method and system for avoiding misoperation during debugging of semiconductor process menu |
| CN103436863A (en) * | 2013-08-15 | 2013-12-11 | 镇江大全太阳能有限公司 | Method for automatically generating tubular PECVD (Plasma Enhanced Chemical Vapor Deposition) coating time |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7682845B2 (en) * | 2007-12-27 | 2010-03-23 | Globalfoundries Inc. | Methods for calibrating a process for growing an epitaxial silicon film and methods for growing an epitaxial silicon film |
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- 2015-10-28 CN CN201510716938.8A patent/CN105405756B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101231508A (en) * | 2008-01-17 | 2008-07-30 | 中电华清微电子工程中心有限公司 | Control method for fabrication technology of analysis estimation-correcting integrated circuit by time series |
| CN102800564A (en) * | 2011-05-26 | 2012-11-28 | 中国科学院微电子研究所 | Method and system for avoiding misoperation during debugging of semiconductor process menu |
| CN102605351A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Method for resetting after LPCVD (low pressure chemical vapor deposition) maintenance |
| CN103436863A (en) * | 2013-08-15 | 2013-12-11 | 镇江大全太阳能有限公司 | Method for automatically generating tubular PECVD (Plasma Enhanced Chemical Vapor Deposition) coating time |
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