CN105390536A - 绝缘栅双极型晶体管及其制备方法 - Google Patents
绝缘栅双极型晶体管及其制备方法 Download PDFInfo
- Publication number
- CN105390536A CN105390536A CN201510636146.XA CN201510636146A CN105390536A CN 105390536 A CN105390536 A CN 105390536A CN 201510636146 A CN201510636146 A CN 201510636146A CN 105390536 A CN105390536 A CN 105390536A
- Authority
- CN
- China
- Prior art keywords
- substrate
- drift region
- bipolar transistor
- insulated gate
- gate bipolar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 238000002360 preparation method Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 20
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 238000001459 lithography Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000007921 spray Substances 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
Abstract
本发明公开了一种绝缘栅双极型晶体管及其制备方法,所述绝缘栅双极型晶体管包括半导体衬底;在所述半导体衬底的正面外延生长成的N-漂移区;在上述N-漂移区上制备形成包括栅极和发射极的上部端子;在所述半导体衬底的背面形成集电极的下部端子;在所述N-漂移区内部至少形成一个P型浮岛。本发明提供的绝缘栅双极型晶体管及其制备方法,旨在防止绝缘栅双极型晶体管击穿电压下降,减少导通压降,以提高IGBT元器件在高电压领域应用时的可靠性。
Description
技术领域
本发明涉及半导体器件技术领域,具体涉及一种绝缘栅双极型晶体管及其制备方法,特别是能防止击穿电压降低,减少导通电压降,提高工作效率的绝缘栅双极型晶体管及其制备方法。
背景技术
随着IT技术的发展,各个领域对高性能电力半导体元件的需求都在增加。其中绝缘栅双极型晶体管(InsulatedGateBipolarTransistor,IGBT)作为新型电力半导体场控自关断器件,集功率MOSFET的高速开关性能与双极性器件(BJT)的大电流驱动能力、低正向电压降和优秀的正向传导性能于一体,具有耐高压、承受电流大等优点,在各种电力变换中获得极广泛的应用。
如图1所示,现有技术的绝缘栅双极型晶体管的下端是集电极,上端是发射极和栅极,由N+发射极、P基极、N漂移区和栅极构成的MOSFET,以及由P基极、N漂移区和P集电极构成的PNPBJT连接而成,现有技术的绝缘栅双极型晶体管,当在集电极施加一个负偏压并低于门限值时,N漂移区和P+之间创建的J1结就会受到反向偏压控制,此时,耗尽层则会向低掺杂浓度的N漂移区扩展。这个耗尽层的区域越大,能支持的击穿电压就越高,IGBT管在关断时就能阻抗高电压。当栅极和发射极短接并在集电极端子施加一个正电压时,N漂移区和P基区之间的J2结受反向电压控制,此时,仍然是由N漂移区中的耗尽层承受外部施加的电压。
上述绝缘栅双极型晶体管应具有以下特征:关断时的可承受的阻断电压,即击穿电压提高,同时导通压降减少。然而,电力半导体的击穿电压和导通损耗是此消彼长的权衡关系,为了解决这一问题,开发出了在低掺杂浓度的N-漂移区插入P型浮岛的FLIMOS(FloatingIslandMOS)。最大电场强度向浮岛和P基区分散,可以提高既有的掺杂浓度,减少JFET区的阻抗。但是,在高电压状态下采用FLIMOS时,会发生因为漂移区的扩大,存在导通阻抗增大,而且制造成本也会增加的问题。
发明内容
为了解决现有技术中存在的上述问题,本发明提供了一种绝缘栅双极型晶体管及其制备方法,旨在防止绝缘栅双极型晶体管击穿电压下降,减少导通压降,以提高IGBT元器件在高电压领域应用时的可靠性。
本发明的技术方案如下:
一种绝缘栅双极型晶体管,包括半导体衬底;在所述半导体衬底的正面外延生长成的N-漂移区;在上述N-漂移区上制备形成包括栅极和发射极的上部端子;在所述半导体衬底的背面形成集电极的下部端子;在所述N-漂移区内部至少形成一个P型浮岛。
本发明公开的绝缘栅双极型晶体管通过在N-漂移区插入浮岛结构的P层,提高N-漂移区浓度,从而防止击穿电压下降,减少导通压降,以达到提高半导体性能的效果。
本发明还公开了上述绝缘栅双极型晶体管的制备方法,包括步骤:
S01、准备P型衬底,在所述P型衬底上外延生长形成预定厚度的N-漂移区;
S02、在所述N-漂移区上喷涂光刻胶,进行光刻加工;在光刻胶喷涂处注入硼离子,形成至少一个浮岛结构的P层;
S03、在所述浮岛结构的P层的N-漂移区,通过外延生长再形成一个N-漂移区;
S04、在所述再形成的N-漂移区上形成包括发射极和栅极的上部端子,在所述P型衬底的背面形成包括集电极的下部端子。
进一步的,所述外延生长是将P型衬底置于超高真空腔中,将需要生长的单晶物质加热到预定温度,使其以分子流射出,在P型衬底上生长出单晶层。
上述绝缘栅双极型晶体管的制备方法,包括步骤:
S11、提供一个N型半导体材料制成的N型衬底;
S12、将光刻胶溶液喷涂到所述N型衬底表面,定义需要注入的区域,进行光刻加工;然后使用离子注入法将硼离子嵌入衬底中,形成至少一个浮岛结构的P层;
S13、在所述浮岛结构的P层的N型衬底表面,外延生长形成一层N-漂移区;
S14、在所述外延生成的N-漂移区上形成包括发射极和栅极的上部端子;然后,通过CMP工艺对所述N型衬底的背面进行减薄/抛光,形成包括P型集电极的下部端子。
上述绝缘栅双极型晶体管的制备方法,包括步骤:
S21、提供预定掺杂浓度的N型半导体材料制成的第一衬底;
S22、在所述第一衬底表面上形成一层光刻胶薄膜,进行光刻加工,接着,用离子注入法将高能硼离子嵌入第一衬底中,形成至少一个浮岛结构的P层;
S23、提供与所述第一衬底掺杂浓度相同的第二衬底,将第二衬底与所述第一衬底黏着键合形成N-漂移区;
S24、将第二衬底的表面通过CMP工艺减薄/抛光,形成包括发射极和栅极的上部端子;并通过CMP工艺对所述第一衬底的背面进行减薄/抛光,形成包括P型集电极的下部端子。
本发明公开的绝缘栅双极型晶体管的制备方法是在半导体衬底上形成浮岛结构,省略了N-漂移区外延生长的工艺成本,从而能节省绝缘栅双极型晶体管的制造成本,比外延生成的N-漂移区具有更均匀的掺杂浓度。
附图说明
图1为现有技术中的绝缘栅双极型晶体管的结构示意图;
图2为本发明在一实施例中的工艺流程示意图;
图3为本发明在另一实施例中的工艺流程示意图;
图4为本发明在又一实施例中的工艺流程示意图;
图5为本发明的绝缘栅双极型晶体管在一实施例的电场分布图。
具体实施方式
下面结合附图对本发明的具体实施方式做详细阐述。
本发明公开的绝缘栅双极型晶体管包括半导体衬底;在所述半导体衬底的正面外延生长成的N-漂移区;在上述N-漂移区上制备形成包括栅极和发射极的上部端子;在所述半导体衬底的背面形成集电极的下部端子;在所述N-漂移区内部至少形成一个P型浮岛。
以下结合图2,详细介绍本发明的绝缘栅双极型晶体管在一实施例的制备方法:
图2是该制备方法的流程图,如图2(a)所示,需要准备P型衬底(110),然后,如图2(b)所示,在上述P型衬底(110)上外延生长形成预定厚度的N-漂移区(120),在N-漂移区上喷涂光刻胶,进行光刻加工;在光刻胶喷涂处注入硼离子,形成至少一个浮岛结构的P层(122);然后,如图2(c)所示,在形成的浮岛结构的P层(122)的N-漂移区(120)上,通过外延生长再形成一个N-漂移区(120),上述外延工艺是在单晶衬底上通过分子束外延技术生长出与衬底晶向一致的极薄的单晶层,即将衬底置于超高真空腔中,将需要生长的单晶物质加热到适当的温度,使其以分子流射出,在衬底上生长出极薄的单晶层。外延工序具有以下特征:形成的单晶层可以是单原子层的厚度,非常薄,但是对复杂的超晶格结构能进行精密控制;之后,如图2(d)所示,在通过图2(c)所示的工序再生长的N-漂移区(120)上形成包括发射极(140)和栅极(130)的上部端子,在上述衬底(110)的背面形成包括集电极(150)的下部端子,从而制备在N-漂移区形成具有浮岛结构的P层的绝缘栅双极型晶体管。
以下,结合图3介绍本发明的另一优选实施例的绝缘栅双极型晶体管的制备方法:
如图3(a)所示,提供一个N型半导体材料做衬底(210),上述N型衬底(210)在经过后续工艺流程后要形成一个浮岛结构的P层,因此需要达到一定的厚度;
如图3(b)所示,将光刻胶溶液喷涂到衬底表面上,定义需要注入的区域,进行光刻加工,接下来,使用离子注入法将硼离子嵌入衬底中,形成至少一个浮岛结构的P层(212);
然后,如图3(c)所示,形成至少一个浮岛结构的P层(212)的上述衬底(210)表面,外延生长一层N-漂移区(220),此时,上述N-漂移区(220)要考虑浮岛和后续工艺形成的P基极之间的距离,因此需要达到一定的厚度;
之后,如图3(d)所示,外延生成的N-漂移区(220)上形成包括发射极(240)和栅极(230)的上部端子。然后,通过CMP工艺对所述衬底(210)的背面进行减薄/抛光,形成包括P型集电极(250)的下部端子,从而制备在N-漂移区形成具有浮岛结构的P层的绝缘栅双极型晶体管。
在上述实施例以外,结合图4来介绍一下本发明的又一优选实施例的绝缘栅双极型晶体管的制备方法:
图4是显示本发明的又一优选实施例的绝缘栅双极型晶体管制备方法的流程图。
如图4(a)所示,本发明的绝缘栅双极型晶体管的制备方法具体步骤包括:提供第一衬底(310);在所述第一衬底(310)表面上形成一层光刻胶薄膜,进行光刻加工;接着,用离子注入法将高能硼离子嵌入衬底中,形成至少一个浮岛结构的P层(312),此时,上述衬底(310)可优选使用低掺杂浓度的NPT型N型半导体材料;
然后,准备一块与上述第一衬底掺杂浓度相同的第二衬底(320),将上述第二衬底(320)与上述具有浮岛结构P层(312)的第一衬底黏着键合;
如图4(b)所示,上述第一衬底(310)与第二衬底(320)黏合键合形成N-漂移区;
之后,如图4(c)所示,与上述第一衬底(310)黏着键合的第二衬底(320)的表面通过CMP(ChemicalMechanicalPolishing)工艺减薄/抛光,形成包括发射极(340)和栅极(330)的上部端子;
最后,如图4(d)所示,通过CMP工艺对上述第一衬底(310)的背面进行减薄/抛光,形成包括P型集电极(250)的下部端子,从而在第一衬底的正面制备具有浮岛结构的P层的绝缘栅双极型晶体管。
如图5所示,(1)是现有技术的绝缘栅双极型晶体管的电场分布图,(2)是如本发明所述具有浮岛结构的P层的绝缘栅双极型晶体管的电场分布图。从(2)可知,具有浮岛结构的P层的本发明所述的绝缘栅双极型晶体管,由于N-漂移区的浓度高,因此斜率大,但是浮岛结构使得电场分散,因此即便是在高电压状态下,也能保持良好的工作性能。
本发明所述的绝缘栅双极型晶体管及其制备方法是在N-漂移区上插入浮岛结构(FloatingIsland)的P层,从而使得N-漂移区的掺杂浓度提高,能防止击穿电压降低,减少导通电压降,具有改善工作性能的效果。
此外,本发明所述的绝缘栅双极型晶体管及其制备方法是在N型硅片上加入浮岛结构(FloatingIsland),省略了生成N-漂移区的外延工艺,起到节省成本的效果。
而且,本发明所述的绝缘栅双极型晶体管及其制备方法是将形成浮岛结构的衬底与其他衬底黏着键合在一起,省略了生成N-漂移区的外延工艺,起到节省成本的效果。
与此同时,本发明所述的绝缘栅双极型晶体管及其制备方法是将形成浮岛结构的衬底与其他衬底黏着键合在一起形成了N-漂移区,这比外延生成的N-漂移区的掺杂浓度更均匀。
以上所述的本发明实施方式,并不构成对本发明保护范围的限定。任何在本发明的精神和原则之内所作的修改、等同替换和改进等,均应包含在本发明的权利要求保护范围之内。
Claims (5)
1.一种绝缘栅双极型晶体管,其特征在于:包括半导体衬底;在所述半导体衬底的正面外延生长成的N-漂移区;在上述N-漂移区上制备形成包括栅极和发射极的上部端子;在所述半导体衬底的背面形成集电极的下部端子;在所述N-漂移区内部至少形成一个P型浮岛。
2.如权利要求1所述的绝缘栅双极型晶体管的制备方法,其特征在于,包括步骤:
S01、准备P型衬底,在所述P型衬底上外延生长形成预定厚度的N-漂移区;
S02、在所述N-漂移区上喷涂光刻胶,进行光刻加工;在光刻胶喷涂处注入硼离子,形成至少一个浮岛结构的P层;
S03、在所述浮岛结构的P层的N-漂移区,通过外延生长再形成一个N-漂移区;
S04、在所述再形成的N-漂移区上形成包括发射极和栅极的上部端子,在所述P型衬底的背面形成包括集电极的下部端子。
3.如权利要求2所述的绝缘栅双极型晶体管的制备方法,其特征在于:所述外延生长是将P型衬底置于超高真空腔中,将需要生长的单晶物质加热到预定温度,使其以分子流射出,在P型衬底上生长出单晶层。
4.如权利要求1所述的绝缘栅双极型晶体管的制备方法,其特征在于,包括步骤:
S11、提供一个N型半导体材料制成的N型衬底;
S12、将光刻胶溶液喷涂到所述N型衬底表面,定义需要注入的区域,进行光刻加工;然后使用离子注入法将硼离子嵌入衬底中,形成至少一个浮岛结构的P层;
S13、在所述浮岛结构的P层的N型衬底表面,外延生长形成一层N-漂移区;
S14、在所述外延生成的N-漂移区上形成包括发射极和栅极的上部端子;然后,通过CMP工艺对所述N型衬底的背面进行减薄/抛光,形成包括P型集电极的下部端子。
5.如权利要求1所述的绝缘栅双极型晶体管的制备方法,其特征在于,包括步骤:
S21、提供预定掺杂浓度的N型半导体材料制成的第一衬底;
S22、在所述第一衬底表面上形成一层光刻胶薄膜,进行光刻加工,接着,用离子注入法将高能硼离子嵌入第一衬底中,形成至少一个浮岛结构的P层;
S23、提供与所述第一衬底掺杂浓度相同的第二衬底,将第二衬底与所述第一衬底黏着键合形成N-漂移区;
S24、将第二衬底的表面通过CMP工艺减薄/抛光,形成包括发射极和栅极的上部端子;并通过CMP工艺对所述第一衬底的背面进行减薄/抛光,形成包括P型集电极的下部端子。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510636146.XA CN105390536A (zh) | 2015-09-30 | 2015-09-30 | 绝缘栅双极型晶体管及其制备方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510636146.XA CN105390536A (zh) | 2015-09-30 | 2015-09-30 | 绝缘栅双极型晶体管及其制备方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105390536A true CN105390536A (zh) | 2016-03-09 |
Family
ID=55422622
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510636146.XA Pending CN105390536A (zh) | 2015-09-30 | 2015-09-30 | 绝缘栅双极型晶体管及其制备方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105390536A (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018000223A1 (zh) * | 2016-06-29 | 2018-01-04 | 黄嘉杰 | 一种绝缘栅双极型晶体管结构及其制造方法 |
CN110767593A (zh) * | 2019-10-14 | 2020-02-07 | 芯盟科技有限公司 | 一种半导体结构及其形成方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03261179A (ja) * | 1990-03-09 | 1991-11-21 | Fuji Electric Co Ltd | 絶縁ゲート型バイポーラトランジスタ |
CN1102274A (zh) * | 1993-10-29 | 1995-05-03 | 电子科技大学 | 具有异型掺杂岛的半导体器件耐压层 |
US6091108A (en) * | 1997-11-13 | 2000-07-18 | Abb Research Ltd. | Semiconductor device of SiC having an insulated gate and buried grid region for high breakdown voltage |
KR20130035579A (ko) * | 2011-09-30 | 2013-04-09 | 고려대학교 산학협력단 | 절연 게이트 바이폴라 트랜지스터 및 이의 제조방법 |
-
2015
- 2015-09-30 CN CN201510636146.XA patent/CN105390536A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03261179A (ja) * | 1990-03-09 | 1991-11-21 | Fuji Electric Co Ltd | 絶縁ゲート型バイポーラトランジスタ |
CN1102274A (zh) * | 1993-10-29 | 1995-05-03 | 电子科技大学 | 具有异型掺杂岛的半导体器件耐压层 |
US6091108A (en) * | 1997-11-13 | 2000-07-18 | Abb Research Ltd. | Semiconductor device of SiC having an insulated gate and buried grid region for high breakdown voltage |
KR20130035579A (ko) * | 2011-09-30 | 2013-04-09 | 고려대학교 산학협력단 | 절연 게이트 바이폴라 트랜지스터 및 이의 제조방법 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018000223A1 (zh) * | 2016-06-29 | 2018-01-04 | 黄嘉杰 | 一种绝缘栅双极型晶体管结构及其制造方法 |
US10692995B2 (en) | 2016-06-29 | 2020-06-23 | Ka Kit WONG | Insulated-gate bipolar transistor structure and method for manufacturing the same |
CN110767593A (zh) * | 2019-10-14 | 2020-02-07 | 芯盟科技有限公司 | 一种半导体结构及其形成方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101645769B1 (ko) | 선택적으로 도핑된 jfet 영역들을 갖는 파워 반도체 디바이스들 및 이러한 디바이스들을 형성하는 관련 방법들 | |
CN103413824B (zh) | 一种rc-ligbt器件及其制作方法 | |
CN103137472B (zh) | 结合快复管的igbt器件制造方法 | |
CN102800591A (zh) | 一种fs-igbt器件的制备方法 | |
CN101540343A (zh) | 偏移场板结构的4H-SiC PiN/肖特基二极管及其制作方法 | |
CN108511528B (zh) | 具有深漏区的横向双扩散金属氧化物复合半导体场效应管及其制作方法 | |
CN102723360A (zh) | 半绝缘外延的碳化硅及相关的宽带隙晶体管 | |
JP2016189465A (ja) | 2種類のエミッタ領域を有するエミッタを備えるバイポーラトランジスタデバイス | |
Tang et al. | An implanted-emitter 4H-SiC bipolar transistor with high current gain | |
JP2015023141A (ja) | 半導体装置 | |
CN101752415A (zh) | 一种绝缘栅双极晶体管及其制造方法 | |
CN102044543B (zh) | 一种单片集成igbt和frd的半导体器件 | |
KR20130076314A (ko) | 파워소자 및 이의 제조방법 | |
WO2021072812A1 (zh) | 横向GaN基增强型结型场效应管器件及其制备方法 | |
CN104425259A (zh) | 反向导通绝缘栅双极型晶体管制造方法 | |
CN105390536A (zh) | 绝缘栅双极型晶体管及其制备方法 | |
CN105720107A (zh) | 一种快恢复二极管及其制造方法 | |
CN105529359B (zh) | 具有包含深能级掺杂剂的辅助结构的半导体器件 | |
CN109920840B (zh) | 一种具有L型SiO2隔离层的复合型RC-LIGBT器件 | |
CN104934485A (zh) | 半导体装置 | |
US9236433B2 (en) | Semiconductor devices in SiC using vias through N-type substrate for backside contact to P-type layer | |
CN106298774A (zh) | 一种mps二极管及其制造方法 | |
CN114300544A (zh) | 一种快恢复二极管及其制作方法 | |
CN102931223B (zh) | Igbt集电极结构 | |
JP2014225589A (ja) | 半導体装置およびその動作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160309 |
|
RJ01 | Rejection of invention patent application after publication |