CN105378843A - 具有位单元和逻辑单元划分的单片式三维(3d)随机存取存储器(ram)阵列架构 - Google Patents

具有位单元和逻辑单元划分的单片式三维(3d)随机存取存储器(ram)阵列架构 Download PDF

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Publication number
CN105378843A
CN105378843A CN201480039131.9A CN201480039131A CN105378843A CN 105378843 A CN105378843 A CN 105378843A CN 201480039131 A CN201480039131 A CN 201480039131A CN 105378843 A CN105378843 A CN 105378843A
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CN
China
Prior art keywords
3dic
layer
ram
disposed
3dram
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Pending
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CN201480039131.9A
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English (en)
Chinese (zh)
Inventor
P·卡迈勒
Y·杜
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Qualcomm Inc
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Qualcomm Inc
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Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105378843A publication Critical patent/CN105378843A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
CN201480039131.9A 2013-07-11 2014-07-10 具有位单元和逻辑单元划分的单片式三维(3d)随机存取存储器(ram)阵列架构 Pending CN105378843A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361845044P 2013-07-11 2013-07-11
US61/845,044 2013-07-11
US14/012,478 US20150019802A1 (en) 2013-07-11 2013-08-28 Monolithic three dimensional (3d) random access memory (ram) array architecture with bitcell and logic partitioning
US14/012,478 2013-08-28
PCT/US2014/046152 WO2015006563A1 (en) 2013-07-11 2014-07-10 A monolithic three dimensional (3d) random access memory (ram) array architecture with bitcell and logic partitioning

Publications (1)

Publication Number Publication Date
CN105378843A true CN105378843A (zh) 2016-03-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480039131.9A Pending CN105378843A (zh) 2013-07-11 2014-07-10 具有位单元和逻辑单元划分的单片式三维(3d)随机存取存储器(ram)阵列架构

Country Status (6)

Country Link
US (1) US20150019802A1 (https=)
EP (1) EP3020045A1 (https=)
JP (1) JP6407992B2 (https=)
KR (1) KR20160029835A (https=)
CN (1) CN105378843A (https=)
WO (1) WO2015006563A1 (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110603640A (zh) * 2017-07-17 2019-12-20 美光科技公司 存储器电路系统
CN110741558A (zh) * 2017-06-15 2020-01-31 交流通讯有限公司 具有逻辑三维存储器的极化编码器、通信单元、集成电路及其方法
CN115996200A (zh) * 2021-10-15 2023-04-21 西安紫光国芯半导体有限公司 3d-ic基带芯片、堆叠芯片及数据处理方法
CN116741227A (zh) * 2023-08-09 2023-09-12 浙江力积存储科技有限公司 一种三维存储器架构及其操作方法和存储器

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9679630B2 (en) 2015-11-06 2017-06-13 Carver Scientific, Inc. Electroentropic memory device
US9929149B2 (en) 2016-06-21 2018-03-27 Arm Limited Using inter-tier vias in integrated circuits
AU2017367692B2 (en) 2016-12-02 2022-04-14 Carver Scientific, Inc. Memory device and capacitive energy storage device
JP7338975B2 (ja) 2018-02-12 2023-09-05 三星電子株式会社 半導体メモリ素子
FR3089678B1 (fr) 2018-12-11 2021-09-17 Commissariat Energie Atomique Memoire ram realisee sous la forme d’un circuit integre 3d
US11139283B2 (en) 2018-12-22 2021-10-05 Xcelsis Corporation Abstracted NAND logic in stacks
US11469214B2 (en) 2018-12-22 2022-10-11 Xcelsis Corporation Stacked architecture for three-dimensional NAND
EP4024222A1 (en) 2021-01-04 2022-07-06 Imec VZW An integrated circuit with 3d partitioning

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1716599A (zh) * 2004-06-29 2006-01-04 尔必达存储器股份有限公司 具有芯片间互连选择装置的三维半导体器件
CN102216997A (zh) * 2009-02-24 2011-10-12 莫塞德技术公司 包括主器件的堆叠的半导体器件
US20120092943A1 (en) * 2010-10-13 2012-04-19 Elpida Memory, Inc. Semiconductor device and test method thereof
CN102834868A (zh) * 2010-04-05 2012-12-19 莫塞德技术公司 具有三维结构的半导体存储装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089993B1 (en) * 1989-09-29 1998-12-01 Texas Instruments Inc Memory module arranged for data and parity bits
JP3707888B2 (ja) * 1996-02-01 2005-10-19 株式会社日立製作所 半導体回路
US5673227A (en) * 1996-05-14 1997-09-30 Motorola, Inc. Integrated circuit memory with multiplexed redundant column data path
WO2000051184A1 (en) * 1999-02-23 2000-08-31 Hitachi, Ltd Semiconductor integrated circuit device
WO2009105362A1 (en) * 2008-02-19 2009-08-27 Rambus Inc. Multi-bank flash memory architecture with assignable resources
US8273610B2 (en) * 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US9257152B2 (en) * 2012-11-09 2016-02-09 Globalfoundries Inc. Memory architectures having wiring structures that enable different access patterns in multiple dimensions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1716599A (zh) * 2004-06-29 2006-01-04 尔必达存储器股份有限公司 具有芯片间互连选择装置的三维半导体器件
CN102216997A (zh) * 2009-02-24 2011-10-12 莫塞德技术公司 包括主器件的堆叠的半导体器件
CN102834868A (zh) * 2010-04-05 2012-12-19 莫塞德技术公司 具有三维结构的半导体存储装置
US20120092943A1 (en) * 2010-10-13 2012-04-19 Elpida Memory, Inc. Semiconductor device and test method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110741558A (zh) * 2017-06-15 2020-01-31 交流通讯有限公司 具有逻辑三维存储器的极化编码器、通信单元、集成电路及其方法
CN110741558B (zh) * 2017-06-15 2023-08-01 交流通讯有限公司 具有逻辑三维存储器的极化编码器、通信单元、集成电路及其方法
CN110603640A (zh) * 2017-07-17 2019-12-20 美光科技公司 存储器电路系统
CN110603640B (zh) * 2017-07-17 2023-06-27 美光科技公司 存储器电路系统
CN115996200A (zh) * 2021-10-15 2023-04-21 西安紫光国芯半导体有限公司 3d-ic基带芯片、堆叠芯片及数据处理方法
CN116741227A (zh) * 2023-08-09 2023-09-12 浙江力积存储科技有限公司 一种三维存储器架构及其操作方法和存储器
CN116741227B (zh) * 2023-08-09 2023-11-17 浙江力积存储科技有限公司 一种三维存储器架构及其操作方法和存储器

Also Published As

Publication number Publication date
EP3020045A1 (en) 2016-05-18
JP6407992B2 (ja) 2018-10-17
KR20160029835A (ko) 2016-03-15
JP2016528727A (ja) 2016-09-15
US20150019802A1 (en) 2015-01-15
WO2015006563A1 (en) 2015-01-15

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