CN105374870A - 具备亚阈值势垒的hemt外延结构 - Google Patents

具备亚阈值势垒的hemt外延结构 Download PDF

Info

Publication number
CN105374870A
CN105374870A CN201510813225.3A CN201510813225A CN105374870A CN 105374870 A CN105374870 A CN 105374870A CN 201510813225 A CN201510813225 A CN 201510813225A CN 105374870 A CN105374870 A CN 105374870A
Authority
CN
China
Prior art keywords
gan
layer
aln
epitaxial structure
potential barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510813225.3A
Other languages
English (en)
Inventor
黎明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Gastone Technology Co Ltd
Original Assignee
Chengdu Gastone Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Gastone Technology Co Ltd filed Critical Chengdu Gastone Technology Co Ltd
Priority to CN201510813225.3A priority Critical patent/CN105374870A/zh
Publication of CN105374870A publication Critical patent/CN105374870A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明提供了一种具备亚阈值势垒的HEMT外延结构。其包括由下至上依次形成的Si衬底、SiN/AlN成核层、GaN缓冲层和外延层，GaN缓冲层用于吸收Si衬底与外延层之间因晶格失配产生的应力，外延层包括由下至上依次形成的AlN/GaN超晶格隔离层、GaN掺杂层、GaN沟道层、AlN势垒层和GaN帽层，GaN掺杂层中的掺杂物为Mg。本发明能够实现毫米波段的应用。

Description

具备亚阈值势垒的HEMT外延结构
技术领域
本发明涉及半导体器件技术领域，特别是涉及一种具备亚阈值势垒的HEMT外延结构。
背景技术
硅基芯片经历几十年发展，Si基CMOS器件尺寸不断缩小，其频率性能却不断提高，当特征尺寸达到25nm时，其fT可达490GHz。但Si材料的Johnson优值仅为0.5THzV,而尺寸的缩小使Si基CMOS器件的击穿电压远小于1V，这极大地限制了硅基芯片在超高速数字领域的应用。
近年来，人们不断地寻找Si材料的替代品，由于宽禁带半导体氮化镓(GaN)材料具有超高的Johnson优值(可达到5THzV)，其器件沟道尺寸达到10nm量级时，击穿电压仍能保持在10V左右，因此，GaN材料已逐渐引起国内外广泛的重视。随着，GaN材料在要求高转换效率和精确阈值控制、宽带、大动态范围的电路(如超宽带ADC、DAC)数字电子领域具有广阔和特殊的应用前景，GaN基逻辑器件已成为近几年超高速半导体领域研究的热点，正成为Si基CMOS高速电路在数模和射频电路领域的后续发展中的有力竞争者,是国家重点支持的尖端技术，堪称信息产业的“心脏”。
目前，基于GaN的HEMT逻辑器件的加工尺度已进入了GaN纳电子的范畴，fT已达到190GHz，正向着300GHz到500GHz进军。但是，一方面，由于常规GaN器件受限于AlGaN势垒的“内在应力”和“表面耗尽效应”，其AlGaN势垒极限厚度无法突破18nm，不能满足毫米波应用器件等比例缩小的要求，阻碍了其向毫米波段超高速数字电路方向的发展；另一方面，对于这些传统器件结构本身而言，其中势垒引起的大栅流和电流崩塌是阻碍器件性能提高和实际应用的主要瓶颈。因此，目前的GaN器件还不能实现毫米波段的应用。
发明内容
本发明主要解决的技术问题是提供一种具备亚阈值势垒的HEMT外延结构，能够实现毫米波段的应用。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种具备亚阈值势垒的HEMT外延结构，包括由下至上依次形成的Si衬底、SiN/AlN成核层、GaN缓冲层和外延层，所述GaN缓冲层用于吸收所述Si衬底与所述外延层之间因晶格失配产生的应力，所述外延层包括由下至上依次形成的AlN/GaN超晶格隔离层、GaN掺杂层、GaN沟道层、AlN势垒层和GaN帽层，所述GaN掺杂层中的掺杂物为Mg。
优选地，所述SiN/AlN成核层、GaN缓冲层、AlN/GaN超晶格隔离层、GaN掺杂层、GaN沟道层、AlN势垒层和GaN帽层均采用MOCVD工艺生长。
优选地，所述SiN/AlN成核层的厚度均为400-800nm。
优选地，所述GaN缓冲层的厚度为1-2um。
优选地，所述AlN/GaN超晶格隔离层用于对所述GaN缓冲层的应力进行调节。
优选地，所述GaN沟道层用于在低场下为二维电子气提供导电沟道。
优选地，所述AlN势垒层用于使所述GaN掺杂层提供的自由电子向所述GaN沟道层内转移，所述AlN势垒层的厚度为1.5nm。
优选地，所述GaN帽层的厚度为1-3nm。
区别于现有技术的情况，本发明的有益效果是：
1.有利于大幅度降低高速GaNHEMT器件的成本，并且可与常规的Si基CMOS器件无缝契合，实现大规模化应用的射频与数字的集成。
2.可有效地解决常规AlGaN势垒GaN器件遇到的“内在应力”和“表面耗尽效应”，明显改善常规GaN器件的大栅流和电流崩塌现象，提高器件可靠性。
3.可极大地减小GaN器件的漏电流，提升器件效率。
4.通过AlN/GaN超晶格隔离层隔离Si衬底和GaN沟道层，可以有效改善Si基衬底和GaN体系之间的晶格失配问题，增加了器件的二维电子气，提高器件可靠性。
附图说明
图1是本发明实施例具备亚阈值势垒的HEMT外延结构的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参见图1，是本发明实施例具备亚阈值势垒的HEMT外延结构的示意图。本实施例的具备亚阈值势垒的HEMT外延结构包括由下至上依次形成的Si衬底1、SiN/AlN成核层2、GaN缓冲层3和外延层，GaN缓冲层4用于吸收Si衬底1与外延层之间因晶格失配产生的应力，外延层包括由下至上依次形成的AlN/GaN超晶格隔离层4、GaN掺杂层5、GaN沟道层6、AlN势垒层7和GaN帽层8，GaN掺杂层5中的掺杂物为Mg。在本实施例中，SiN/AlN成核层2、GaN缓冲层3、AlN/GaN超晶格隔离层4、GaN掺杂层5、GaN沟道层6、AlN势垒层7和GaN帽层8均采用MOCVD(Metal-organicChemicalVaporDeposition，金属有机化合物沉积工艺)生长。
其中，Si衬底1主要起支撑作用。可选地，Si衬底1采用高电阻率Si材料。
SiN/AlN成核层2的厚度均为400-800nm。SiN/AlN成核层2用于吸收Si衬底1与其它层之间因为晶格失配产生的应力，避免产生晶格驰豫。
GaN缓冲层3的厚度为1-2um。GaN缓冲层3用于吸收Si衬底1与其它层之间因为晶格失配产生的应力。
AlN/GaN超晶格隔离层4用于对GaN缓冲层3的应力进行调节，避免晶格弛豫。AlN/GaN超晶格隔离层4可以做到很薄，形成超薄亚阈值势垒，可有效地解决常规AlGaN势垒GaN器件遇到的“内在应力”和“表面耗尽效应”，明显改善常规GaN器件的大栅流和电流崩塌现象，提高器件可靠性。
GaN掺杂层5由于进行了Mg掺杂，可以极大地减小器件的漏电流，提升器件效率。
GaN沟道层6用于在低场下为二维电子气提供导电沟道。
AlN势垒层7用于使GaN掺杂层5提供的自由电子向GaN沟道层6内转移，AlN势垒层7的厚度为1.5nm。
GaN帽层8的厚度为1-3nm。
本发明实施例的具备亚阈值势垒的HEMT外延结构由于采用AlN/GaN超晶格结构形成亚阈值势垒，可以提升器件的性能，大幅度降低成本，还可与Si基CMOS高速逻辑电路器件工艺兼容，在数模和RF电路应用中拥有巨大的潜力，适用于毫米波段领域。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (8)

1.一种具备亚阈值势垒的HEMT外延结构，其特征在于，包括由下至上依次形成的Si衬底、SiN/AlN成核层、GaN缓冲层和外延层，所述GaN缓冲层用于吸收所述Si衬底与所述外延层之间因晶格失配产生的应力，所述外延层包括由下至上依次形成的AlN/GaN超晶格隔离层、GaN掺杂层、GaN沟道层、AlN势垒层和GaN帽层，所述GaN掺杂层中的掺杂物为Mg。
2.根据权利要求1所述的具备亚阈值势垒的HEMT外延结构，其特征在于，所述SiN/AlN成核层、GaN缓冲层、AlN/GaN超晶格隔离层、GaN掺杂层、GaN沟道层、AlN势垒层和GaN帽层均采用金属有机化合物沉积MOCVD工艺生长。
3.根据权利要求1或2所述的具备亚阈值势垒的HEMT外延结构，其特征在于，所述SiN/AlN成核层的厚度均为400-800nm。
4.根据权利要求1或2所述所述的具备亚阈值势垒的HEMT外延结构，其特征在于，所述GaN缓冲层的厚度为1-2um。
5.根据权利要求1或2所述的具备亚阈值势垒的HEMT外延结构，其特征在于，所述AlN/GaN超晶格隔离层用于对所述GaN缓冲层的应力进行调节。
6.根据权利要求1或2所述的具备亚阈值势垒的HEMT外延结构，其特征在于，所述GaN沟道层用于在低场下为二维电子气提供导电沟道。
7.根据权利要求1或2所述的具备亚阈值势垒的HEMT外延结构，其特征在于，所述AlN势垒层用于使所述GaN掺杂层提供的自由电子向所述GaN沟道层内转移，所述AlN势垒层的厚度为1.5nm。
8.根据权利要求1或2所述的具备亚阈值势垒的HEMT外延结构，其特征在于，所述GaN帽层的厚度为1-3nm。
CN201510813225.3A 2015-11-20 2015-11-20 具备亚阈值势垒的hemt外延结构 Pending CN105374870A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510813225.3A CN105374870A (zh) 2015-11-20 2015-11-20 具备亚阈值势垒的hemt外延结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510813225.3A CN105374870A (zh) 2015-11-20 2015-11-20 具备亚阈值势垒的hemt外延结构

Publications (1)

Publication Number Publication Date
CN105374870A true CN105374870A (zh) 2016-03-02

Family

ID=55376872

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510813225.3A Pending CN105374870A (zh) 2015-11-20 2015-11-20 具备亚阈值势垒的hemt外延结构

Country Status (1)

Country Link
CN (1) CN105374870A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409993A (zh) * 2016-10-27 2017-02-15 江苏新广联半导体有限公司 具有电磁波防护结构的GaN基半导体器件的外延结构及制作方法
CN108428741A (zh) * 2017-02-14 2018-08-21 英诺赛科（珠海）科技有限公司 氮化镓半导体器件及其制作方法
CN113224193A (zh) * 2021-04-12 2021-08-06 华南理工大学 结合嵌入电极与钝化层结构的InGaN/GaN多量子阱蓝光探测器及其制备方法与应用

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120098599A1 (en) * 2009-06-30 2012-04-26 Univeristy Of Florida Research Foundation Inc. Enhancement mode hemt for digital and analog applications
WO2013161704A1 (ja) * 2012-04-26 2013-10-31 シャープ株式会社 Iii族窒化物半導体積層基板およびiii族窒化物半導体電界効果トランジスタ
CN104465743A (zh) * 2013-09-19 2015-03-25 富士通株式会社 半导体器件及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120098599A1 (en) * 2009-06-30 2012-04-26 Univeristy Of Florida Research Foundation Inc. Enhancement mode hemt for digital and analog applications
WO2013161704A1 (ja) * 2012-04-26 2013-10-31 シャープ株式会社 Iii族窒化物半導体積層基板およびiii族窒化物半導体電界効果トランジスタ
CN104465743A (zh) * 2013-09-19 2015-03-25 富士通株式会社 半导体器件及其制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
XU-QIANG SHEN ET AL: ""Self-generated microcracks in an ultra-thin AlN/GaN superlattice interlayer and their influences on the GaN epilayer grown on Si(110) substrates by metal–organic chemical vapor deposition"", 《CRYSTENGCOMM》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409993A (zh) * 2016-10-27 2017-02-15 江苏新广联半导体有限公司 具有电磁波防护结构的GaN基半导体器件的外延结构及制作方法
CN108428741A (zh) * 2017-02-14 2018-08-21 英诺赛科（珠海）科技有限公司 氮化镓半导体器件及其制作方法
CN108428741B (zh) * 2017-02-14 2021-12-14 英诺赛科（珠海）科技有限公司 氮化镓半导体器件及其制作方法
CN113224193A (zh) * 2021-04-12 2021-08-06 华南理工大学 结合嵌入电极与钝化层结构的InGaN/GaN多量子阱蓝光探测器及其制备方法与应用

Similar Documents

Publication Publication Date Title
CN102856373B (zh) 高电子迁移率晶体管
CN103904134A (zh) 基于GaN基异质结构的二极管结构及制作方法
CN102324436B (zh) 大失配硅基衬底锑化物高电子迁移率晶体管及制造方法
CN102789982A (zh) 一种增强型AlN/GaN高电子迁移率晶体管及其制作方法
CN101740384B (zh) 制备增强型铝镓氮/氮化镓高电子迁移率晶体管的方法
CN103123934A (zh) 具势垒层的氮化镓基高电子迁移率晶体管结构及制作方法
CN105226093A (zh) GaN HEMT器件及其制作方法
CN104299999A (zh) 一种具有复合栅介质层的氮化镓基异质结场效应晶体管
CN104332504A (zh) 一种GaN基异质结肖特基二极管器件及其制作方法
CN205680686U (zh) 一种GaN增强耗尽型MOS‑HEMT器件
CN102931230B (zh) 铝镓氮做高阻层的双异质结氮化镓基hemt及制作方法
CN105374870A (zh) 具备亚阈值势垒的hemt外延结构
CN106098757A (zh) 场效应晶体管
CN103872145A (zh) 一种GaN异质结功率二极管
CN206250202U (zh) 一种增强型 GaN HEMT 外延材料结构
CN105322009A (zh) 氮化镓基高电子迁移率晶体管外延结构及其制造方法
CN102544086B (zh) 氮化镓基高电子迁移率晶体管及其制作方法
CN105304706A (zh) Si基MHEMT外延结构
CN204118078U (zh) 一种GaN基异质结肖特基二极管器件
CN102842613A (zh) 双异质结构氮化镓基高电子迁移率晶体管结构及制作方法
CN101515568A (zh) InP衬底上集成增强型和耗尽型HEMT的制作方法
CN206697485U (zh) 基于Si衬底AlGaN/GaN异质结基的增强型HEMT器件
CN101221983A (zh) 实空间转移高电子迁移率场效应晶体管材料
CN205303470U (zh) 一种增强型GaN器件
CN111799326A (zh) 一种新型二维电子气浓度调控的晶体管结构及制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: 610000 Sichuan, Shuangliu County, Southwest Airport Economic Development Zone, the Internet of things industry park

Applicant after: CHENGDU HIWAFER TECHNOLOGY CO., LTD.

Address before: 610000 Sichuan, Shuangliu County, Southwest Airport Economic Development Zone, the Internet of things industry park

Applicant before: CHENGDU GASTONE TECHNOLOGY CO., LTD.

COR Change of bibliographic data
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160302