CN105374764A - Packaging structure for integrating inductor - Google Patents
Packaging structure for integrating inductor Download PDFInfo
- Publication number
- CN105374764A CN105374764A CN201410438990.7A CN201410438990A CN105374764A CN 105374764 A CN105374764 A CN 105374764A CN 201410438990 A CN201410438990 A CN 201410438990A CN 105374764 A CN105374764 A CN 105374764A
- Authority
- CN
- China
- Prior art keywords
- encapsulating structure
- packaging body
- integrated inductor
- chip
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of microelectronics, and specifically relates to a packaging structure. A packaging structure for integrating an inductor comprises a packaging body, the packaging body is provided with pins connected with the outside, the inner part of the packaging body comprises a chip, the chip is provided with circuit lead-out terminals, the circuit lead-out terminals of set positions are connected with the corresponding pins via first conducting wires, the circuit lead-out terminals of other positions are connected with the corresponding pins via second conducting wires, and the first conducting wires wind in a spiral shape to form an inductor. According to the packaging structure, the circuit lead-out terminals of the set positions of the chip are connected with the corresponding pins via the first conducting wires, the inductor arranged in an external circuit of the pins is replaced, the process complexity of the packaging structure is not increased, the design of the external circuit is simplified, and convenience is provided for the practical application of clients.
Description
Technical field
The present invention relates to microelectronics technology, be specifically related to a kind of encapsulating structure.
Background technology
Too much area is often taken owing to being integrated in by inductance on chip, often not containing inductance in the encapsulating structure of chip, and in the practical application of chip, usually need again in peripheral circuit to arrange inductance, thus occupy the space of printed circuit board too much, and add the application cost of client.
Figure 1 shows that the encapsulating structure of prior art, the inside of packaging body (1), the exit of chip (3) is directly connected by metal lead wire (4) with corresponding pin (2).Also do not have at present a kind of desirable mode can solve inductance to take up room large problem.
Summary of the invention
The object of the invention is to, a kind of encapsulating structure of integrated inductor is provided, solve above technical problem.
Technical problem solved by the invention can realize by the following technical solutions:
An encapsulating structure for integrated inductor, comprises a packaging body, and described packaging body is provided with the pin be connected with outside, and the inside of described packaging body comprises chip, and described chip is provided with circuit exit, wherein,
Described circuit exit and the corresponding pin of desired location adopt first kind wire to connect, and the described circuit exit of all the other positions is connected by Equations of The Second Kind wire with corresponding described pin, and described first kind wire turns to helical form to form inductance.
The encapsulating structure of integrated inductor of the present invention, described pin comprises first and second, described first inside being positioned at described packaging body, and described second outside being positioned at described packaging body, in order to be connected with the external circuit board.
The encapsulating structure of integrated inductor of the present invention, comprises multiple described desired location, connects described first kind wire between the described circuit exit of desired location described in each and corresponding pin.
The encapsulating structure of integrated inductor of the present invention, the coiling axis direction of described inductance is vertical with the extension direction of described first.
The encapsulating structure of integrated inductor of the present invention, the coiling axis direction of described inductance is identical with the extension direction of described first.
The encapsulating structure of integrated inductor of the present invention, described packaging body adopts the encapsulating structure of pasting type, is connected with the external circuit board by surface-pasted form.
The encapsulating structure of integrated inductor of the present invention, described packaging body adopts plug-type encapsulating structure, is connected with the external circuit board by the form of grafting.
Beneficial effect: owing to adopting above technical scheme, the present invention connects first kind wire between the circuit exit and corresponding pin of the desired location of chip, to replace the inductance that should be arranged in external circuit, when not increasing encapsulating structure process complexity, simplify periphery circuit design also for the practical application of client is provided convenience.
Accompanying drawing explanation
Fig. 1 is the encapsulating structure schematic diagram of prior art;
Fig. 2 is the encapsulating structure schematic diagram of a kind of embodiment of the present invention;
Fig. 3 is the encapsulating structure schematic diagram of another kind of embodiment of the present invention;
Fig. 4 is the main body view of encapsulating structure of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite of not making creative work, all belongs to the scope of protection of the invention.
It should be noted that, when not conflicting, the embodiment in the present invention and the feature in embodiment can combine mutually.
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
With reference to Fig. 2, Fig. 3, Fig. 4, a kind of encapsulating structure of integrated inductor, comprises a packaging body 1, and packaging body 1 is provided with the pin 2 be connected with outside, and the inside of packaging body 1 comprises chip 3, and chip 3 is provided with circuit exit, wherein,
The circuit exit of desired location adopts first kind wire 5 to connect with corresponding pin 2, and the circuit exit of all the other positions is connected by Equations of The Second Kind wire 4 with corresponding pin 2, and first kind wire 5 turns to helical form to form inductance.
The present invention connects first kind wire 5 between the circuit exit and corresponding pin of the desired location of chip 3, to replace the inductance that should be arranged in external circuit, when not increasing encapsulating structure process complexity, simplify periphery circuit design also for the practical application of client is provided convenience.
The encapsulating structure of integrated inductor of the present invention, pin 2 can comprise first and second, first inside being positioned at packaging body 1, and second outside being positioned at packaging body 1, in order to be connected with the external circuit board.
The encapsulating structure of integrated inductor of the present invention, the coiling axis direction of inductance can be vertical with the extension direction of first.Or the encapsulating structure of integrated inductor of the present invention, the coiling axis direction of inductance can be identical with the extension direction of first.By metal lead wire is turned to difform inductance, to adapt to the needs of chip and pin type of attachment.The coiling axis direction of preferred inductance is vertical with the extension direction of first, at utmost to reduce the area occupied of inductance.
The encapsulating structure of integrated inductor of the present invention, comprises multiple desired location, connects first kind wire 5 between the circuit exit of each desired location and corresponding pin 2.
The encapsulating structure of integrated inductor of the present invention, packaging body 1 can be the encapsulating structure of pasting type, is connected with the external circuit board by surface-pasted form.As shown in Figure 2, the pin of packaging body 1 can be the encapsulation of surface attaching type, directly welds, be easy to the miniaturization of electronic product on the surface of outside printed circuit board.Packaging body 1 can be the encapsulating structure of both sides wiring configuration, also can be the encapsulating structure of four limit wiring configuration.
The encapsulating structure of integrated inductor of the present invention, packaging body 1 can be plug-type encapsulating structure, is connected with the external circuit board by the form of grafting.As adopted the encapsulating structure of Dual-In-Line type, be easy to the assembling with the external circuit board.
The foregoing is only preferred embodiment of the present invention; not thereby embodiments of the present invention and protection range is limited; to those skilled in the art; should recognize and all should be included in the scheme that equivalent replacement done by all utilizations specification of the present invention and diagramatic content and apparent change obtain in protection scope of the present invention.
Claims (7)
1. an encapsulating structure for integrated inductor, comprises a packaging body, and described packaging body is provided with the pin be connected with outside, and the inside of described packaging body comprises chip, and described chip is provided with circuit exit, it is characterized in that,
Described circuit exit and the corresponding pin of desired location adopt first kind wire to connect, and the described circuit exit of all the other positions is connected by Equations of The Second Kind wire with corresponding described pin, and described first kind wire turns to helical form to form inductance.
2. the encapsulating structure of integrated inductor according to claim 1, it is characterized in that, described pin comprises first and second, described first inside being positioned at described packaging body, described second outside being positioned at described packaging body, in order to be connected with the external circuit board.
3. the encapsulating structure of integrated inductor according to claim 1, is characterized in that, comprises multiple described desired location, connects described first kind wire between the described circuit exit of desired location described in each and corresponding pin.
4. the encapsulating structure of integrated inductor according to claim 1, is characterized in that, the coiling axis direction of described inductance is vertical with the extension direction of described first.
5. the encapsulating structure of integrated inductor according to claim 1, is characterized in that, the coiling axis direction of described inductance is identical with the extension direction of described first.
6. the encapsulating structure of integrated inductor according to claim 1, is characterized in that, described packaging body adopts the encapsulating structure of pasting type, is connected with the external circuit board by surface-pasted form.
7. the encapsulating structure of integrated inductor according to claim 1, is characterized in that, described packaging body adopts plug-type encapsulating structure, is connected with the external circuit board by the form of grafting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438990.7A CN105374764A (en) | 2014-08-29 | 2014-08-29 | Packaging structure for integrating inductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438990.7A CN105374764A (en) | 2014-08-29 | 2014-08-29 | Packaging structure for integrating inductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105374764A true CN105374764A (en) | 2016-03-02 |
Family
ID=55376821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410438990.7A Pending CN105374764A (en) | 2014-08-29 | 2014-08-29 | Packaging structure for integrating inductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105374764A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003258193A (en) * | 2002-03-05 | 2003-09-12 | Seiko Instruments Inc | Semiconductor integrated circuit and method for manufacturing the same |
| CN1669139A (en) * | 2002-09-10 | 2005-09-14 | 半导体元件工业有限责任公司 | Semiconductor devices with wire bond inductor and method |
| JP2009158839A (en) * | 2007-12-27 | 2009-07-16 | Sharp Corp | Semiconductor package, semiconductor device and wire bonding method |
-
2014
- 2014-08-29 CN CN201410438990.7A patent/CN105374764A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003258193A (en) * | 2002-03-05 | 2003-09-12 | Seiko Instruments Inc | Semiconductor integrated circuit and method for manufacturing the same |
| CN1669139A (en) * | 2002-09-10 | 2005-09-14 | 半导体元件工业有限责任公司 | Semiconductor devices with wire bond inductor and method |
| JP2009158839A (en) * | 2007-12-27 | 2009-07-16 | Sharp Corp | Semiconductor package, semiconductor device and wire bonding method |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160302 |
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| RJ01 | Rejection of invention patent application after publication |