CN203882998U - Circuit structure capable enabling occupied space reduction of external inductor of chip - Google Patents
Circuit structure capable enabling occupied space reduction of external inductor of chip Download PDFInfo
- Publication number
- CN203882998U CN203882998U CN201420279903.3U CN201420279903U CN203882998U CN 203882998 U CN203882998 U CN 203882998U CN 201420279903 U CN201420279903 U CN 201420279903U CN 203882998 U CN203882998 U CN 203882998U
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- China
- Prior art keywords
- chip
- area
- pad
- circuit structure
- external
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000001939 inductive effect Effects 0.000 claims description 2
- 238000004804 winding Methods 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Coils Or Transformers For Communication (AREA)
Abstract
The utility model belongs to the electronic technical field and relates to a circuit structure. The circuit structure capable enabling occupied space reduction of an external inductor of a chip. The circuit structure includes a chip; pads are distributed on the chip; the pads are divided into a plurality of regions; a gap between the plurality of regions is provided with a first external-connection inductor; and two ends of the first external-connection inductor are connected with two pads which are arranged at different regions. According to the circuit structure of the utility model, the pads of the chip are divided into a plurality of regions; when a corresponding pin of the chip is needed to be connected with the external-connection inductor, the external-connection inductor can be arranged in the gap between the regions, and therefore, space of a printed circuit board can be saved to the greatest extent, and the miniaturization of the circuit structure can be benefitted; and the inductor and the connection pin of the chip can be short as mush as possible, which is conducive to the improvement of circuit performance.
Description
Technical field
The utility model relates to electronic technology field, is specifically related to a kind of circuit structure.
Background technology
In the circuit of portable type electronic product; chip periphery circuit usually needs to arrange inductance; to realize filtering, suppress immediate current, to reduce electromagnetic interference (Electromagnetic Interference; and the function such as power transfer EMI); but the setting of above-mentioned inductance usually can take the space of printed circuit board too much; in today of small-sized portable electric appts fast development; traditional inductor layout often can not meet instructions for use, and irrational layout also can affect circuit performance and the stability of circuit is produced and disturbed.
Utility model content
The purpose of this utility model is, a kind of circuit structure that off-chip capacitive sense takes up room that reduces is provided, and solves above technical problem.
The technical problem that the utility model solves can realize by the following technical solutions:
Reduce the circuit structure that off-chip capacitive sense takes up room, wherein, comprise a chip, on described chip, be distributed with pad, described pad is divided into multiple regions, the first external inductance is set in the gap between described region, and the two ends of described the first external inductance connect respectively two pads across described region.
Preferably, a pad of desired location is connected the second external inductance, the described pad of described the second external inductive loop winding allocation and/or described adjacent pad with another adjacent pad.
Preferably, described pad is divided into first area, second area, described first area is positioned at the outside of described second area and around described second area, described the first external inductance is set in the gap between described first area and described second area, one end of described the first external inductance connects a pad of described first area, and the other end of described the first external inductance connects a pad of described second area.
Preferably, described first area is positioned at the center of described chip, and described second area is positioned at the marginal position of described chip.
Preferably, the gap between described first area and described second area is greater than the gap between pad and the adjacent described pad of described desired location.
Preferably, comprise multiple described desired locations, described desired location is positioned at described first area or described second area.
Preferably, the soldered ball corresponding with the size of described pad is set described in each on pad.
Beneficial effect: owing to adopting above technical scheme, the utility model, by the pad of chip is divided into multiple regions, arranges external inductance in the gap between region, can at utmost save the space of printed circuit board, is conducive to the miniaturization of circuit structure; Make simultaneously inductance and chip to be connected pin short as far as possible, be conducive to improve circuit performance.
Brief description of the drawings
Fig. 1 is the chip structure schematic diagram of a kind of embodiment of the present utility model;
Fig. 2 is the cutaway view of Fig. 1 of the present utility model;
Fig. 3 is a kind of process program flow chart of realizing of the utility model.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiment.Based on the embodiment in the utility model, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite of not making creative work, belongs to the scope that the utility model is protected.
It should be noted that, in the situation that not conflicting, the feature in embodiment and embodiment in the utility model can combine mutually.
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail, but not as restriction of the present utility model.
With reference to Fig. 1, Fig. 2, reduce the circuit structure that off-chip capacitive sense takes up room, wherein, comprise a chip 1, on chip 1, be distributed with pad, pad is divided into multiple regions, and the two ends that the external inductance 3 of one first external inductance 3, the first is set in the gap between region connect respectively two trans-regional pads.
The utility model, by the pad of chip is divided into multiple regions, in the time that the respective pins of chip needs external inductance, arranges external inductance in the gap between region, can at utmost save the space of printed circuit board, is conducive to the miniaturization of circuit structure; Make simultaneously inductance and chip to be connected pin short as far as possible, be conducive to improve circuit performance.
As a kind of preferred embodiment of the present utility model, a pad of desired location is connected pad and/or the adjacent pad of the external inductance 4 of the second external inductance 4, the second around desired location with another adjacent pad.Preferably, the pad of a part of coil encircling desired location of the second external inductance 4, the remainder coil encircling adjacent pad of the second external inductance, farthest to utilize the space between pad.
As a kind of preferred embodiment of the present utility model, pad is divided into first area, second area, first area is positioned at the outside of second area and around second area, the first external inductance 3 is set in the gap between first area and second area, a pad of the connection first area, one end of the first external inductance 3, the other end of the first external inductance 3 connects a pad of second area.The first external inductance 3 can be strip, extends from one end along the length direction in gap to the other end.
As a kind of preferred embodiment of the present utility model, first area is positioned at the center of chip 1, and second area is positioned at the marginal position of chip 1.
As a kind of preferred embodiment of the present utility model, comprise multiple desired locations, desired location is positioned at first area or second area.As shown in fig. 1, the second external inductance 4 is positioned at the outer peripheral areas of chip.
As a kind of preferred embodiment of the present utility model, the gap between first area and second area is greater than the gap between pad and the adjacent pad of desired location.Can in the gap between first area and second area, place larger-size external inductance, as shown in fig. 1 the first external inductance 3.
As a kind of preferred embodiment of the present utility model, the soldered ball 2 corresponding with the size of pad is set on each pad.Spacing range between soldered ball 2 is less than 1.0mm, or the spacing range between soldered ball 2 is 1.0mm to 1.5mm.
As the improved embodiment of one of the present utility model, the area of the pad of desired location is greater than the area of adjacent pad, on chip, setting position arranges the pad that size is larger, and corresponding soldered ball is set on pad, the sectional area of interconnection structure is increased, the electric current of flowing through on interconnection structure increases, and can reduce the dead resistance of chip between desired location and circuit board, is conducive to the improvement of circuit performance.
The utility model can be realized by following process program, shown in Fig. 3:
Step S1: silk screen printing soldering paste on the pad face of chip, ball attachment machine can adopt the ball attachment machine of vacuum draw principle, chip is contained on positioning fixture, the pad of chip faces up, that aims at ball attachment machine plants ball unit, plant the suction nozzle of ball unit and draw tin ball to be placed, external inductance is also drawn by corresponding suction nozzle together with the tin ball that is connected to two ends simultaneously;
Step S2: place tin ball to the corresponding pad of chip;
Step S3: Reflow Soldering, by the tin ball fusing on pad, is fixed on pad it;
Step S4: by positioner by the soldered ball face of chip just on the corresponding link position of printed circuit board;
Step S5: by chip and printed circuit board are heated simultaneously, realize chip and printed circuit board interconnection.
The utility model also can adopt other alternative modes to realize.
The foregoing is only the utility model preferred embodiment; not thereby limit execution mode of the present utility model and protection range; to those skilled in the art; the scheme that being equal to of should recognizing that all utilization the utility model specifications and diagramatic content done replaces and apparent variation obtains, all should be included in protection range of the present utility model.
Claims (7)
1. reduce the circuit structure that off-chip capacitive sense takes up room, it is characterized in that, comprise a chip, on described chip, be distributed with pad, described pad is divided into multiple regions, the first external inductance is set in the gap between described region, and the two ends of described the first external inductance connect respectively two pads across described region.
2. according to claim 1ly reduce the circuit structure that off-chip capacitive sense takes up room, it is characterized in that, one pad of desired location is connected the second external inductance, the described pad of described the second external inductive loop winding allocation and/or described adjacent pad with another adjacent pad.
3. according to claim 2ly reduce the circuit structure that off-chip capacitive sense takes up room, it is characterized in that, described pad is divided into first area, second area, described first area is positioned at the outside of described second area and around described second area, described the first external inductance is set in the gap between described first area and described second area, one end of described the first external inductance connects a pad of described first area, and the other end of described the first external inductance connects a pad of described second area.
4. according to claim 3ly reduce the circuit structure that off-chip capacitive sense takes up room, it is characterized in that, described first area is positioned at the center of described chip, and described second area is positioned at the marginal position of described chip.
5. according to claim 3ly reduce the circuit structure that off-chip capacitive sense takes up room, it is characterized in that, the gap between described first area and described second area is greater than the gap between pad and the adjacent described pad of described desired location.
6. according to claim 3ly reduce the circuit structure that off-chip capacitive sense takes up room, it is characterized in that, comprise multiple described desired locations, described desired location is positioned at described first area or described second area.
7. according to claim 1ly reduce the circuit structure that off-chip capacitive sense takes up room, it is characterized in that, the soldered ball corresponding with the size of described pad is set on pad described in each.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420279903.3U CN203882998U (en) | 2014-05-28 | 2014-05-28 | Circuit structure capable enabling occupied space reduction of external inductor of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420279903.3U CN203882998U (en) | 2014-05-28 | 2014-05-28 | Circuit structure capable enabling occupied space reduction of external inductor of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203882998U true CN203882998U (en) | 2014-10-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420279903.3U Expired - Lifetime CN203882998U (en) | 2014-05-28 | 2014-05-28 | Circuit structure capable enabling occupied space reduction of external inductor of chip |
Country Status (1)
| Country | Link |
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| CN (1) | CN203882998U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024764A (en) * | 2015-03-25 | 2016-10-12 | 英飞凌科技美国公司 | Semiconductor Package with Integrated Output Inductor on a Printed Circuit Board |
| CN106211577A (en) * | 2016-09-09 | 2016-12-07 | 青岛海信电器股份有限公司 | Terminal unit |
| CN109216296A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Semiconductor package part and method |
| US11942435B2 (en) | 2017-06-30 | 2024-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method |
-
2014
- 2014-05-28 CN CN201420279903.3U patent/CN203882998U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024764A (en) * | 2015-03-25 | 2016-10-12 | 英飞凌科技美国公司 | Semiconductor Package with Integrated Output Inductor on a Printed Circuit Board |
| CN106211577A (en) * | 2016-09-09 | 2016-12-07 | 青岛海信电器股份有限公司 | Terminal unit |
| CN109216296A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Semiconductor package part and method |
| US10872864B2 (en) | 2017-06-30 | 2020-12-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method |
| US20210111127A1 (en) * | 2017-06-30 | 2021-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Package and Method |
| US11664323B2 (en) * | 2017-06-30 | 2023-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method |
| US11942435B2 (en) | 2017-06-30 | 2024-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20141015 |