CN105359261A - 用于晶体管的键合焊盘堆叠 - Google Patents

用于晶体管的键合焊盘堆叠 Download PDF

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Publication number
CN105359261A
CN105359261A CN201480037406.5A CN201480037406A CN105359261A CN 105359261 A CN105359261 A CN 105359261A CN 201480037406 A CN201480037406 A CN 201480037406A CN 105359261 A CN105359261 A CN 105359261A
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China
Prior art keywords
metal
bonding welding
welding pad
layer
metal layer
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CN201480037406.5A
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CN105359261B (zh
Inventor
J·王
L·林
Q·贾
Q·杨
J·刘
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

在所描述的示例中，形成包括底部介电层(211)和顶部介电层(212)的介电堆叠，其具有在键合焊盘(215)上方的接触孔(239)。接触孔(239)内的底部介电层(211)的外边缘延伸超过顶部介电层(212)的外边缘，以限定具有键合焊盘边缘的暴露的键合焊盘区域。第一金属层(226)被沉积。第二金属层(227)被沉积在第一金属层(226)上。第二金属层(227)被湿法刻蚀以使其从接触孔(239)中的底部介电层(211)的侧壁凹进。第一金属层(226)被湿法刻蚀以使其从顶部介电层(212)凹进。第一金属层(226)在键合焊盘边缘上方延伸到底部介电层(211)上。

Description

用于晶体管的键合焊盘堆叠
技术领域
本发明总体涉及集成电路，并且具体地涉及用于晶体管的键合焊盘堆叠。
背景技术
自引入半导体市场以来，铝就是用于半导体器件(半导体管芯)键合焊盘金属化的常用材料，包括用于离散晶体管和集成电路(IC)。然而，铝和高铝合金在表面上快速地形成耐火陶瓷氧化物，这要求特殊处理以在成功地与其焊接之前去除所述耐火陶瓷氧化物。该步骤被应用于从半导体管芯上的铝键合焊盘制造互连的大多数方法，所述半导体管芯被构建在半导体衬底上(通常在单晶硅上)。
半导体管芯被封装在气密密封的壳体中或非气密性塑料封壳中，其中引线从芯片上的键合焊盘延伸到引线框。在无电镀镍沉浸金(ENIG)下凸块金属化(UBM)工艺中，表面处理开始于表面清洁，以去除存在于铝键合焊盘表面上的任何污染物，随后是活化过程以激活键合焊盘用于更好的成核作用，以便随后通过微刻蚀铝氧化物进行处理。
通常使用被已知为锌酸盐处理(zincation)的预镀工艺。在锌酸盐处理工艺期间，铝氧化物被移除并由锌金属的薄层代替。锌保护铝不被再氧化，直至其准备好被电镀。在执行该工艺之后，涂覆锌的铝然后可以被无电镀地镀镍，随后是沉浸金。
发明内容
在所描述的示例中，键合焊盘被形成在半导体管芯上。衬底包括具有顶侧半导体表面的至少一个晶体管。晶体管的第一端子被连接到键合焊盘，该键合焊盘包括在顶侧半导体表面上的键合焊盘金属。形成包括底部介电层和顶部介电层的介电堆叠，该介电堆叠具有在键合焊盘上方穿过介电堆叠的接触孔。接触孔内的底部介电层的外边缘延伸超过顶部介电层的外边缘，以限定具有键合焊盘边缘的暴露的键合焊盘区域。第一金属层被沉积。第二金属层被沉积在第一金属层上。第一光刻胶层被完全地(exclusively)形成在接触孔内。第二金属层被湿法刻蚀，以使第二金属层从接触孔中的底部介电层的侧壁凹进。第二光刻胶层被完全地形成在接触孔内。第一金属层被湿法刻蚀，以使第一金属层从顶部介电层凹进。第一金属层在键合焊盘边缘上方延伸到底部介电层上。
附图说明
图1是根据示例实施例用于在半导体管芯上形成键合焊盘堆叠的示例形成方法的流程图。
图2A-F是用于图1的示例方法的处理进展的横截面视图。
图3是基于示例性完成的键合焊盘堆叠的扫描电子显微镜(SEM)测试的图表，该键合焊盘堆叠具有针对金属掩模1和金属掩模2的金属掩模边缘，其被添加以示出示例金属掩模特征和所得的刻蚀后金属层边缘。
具体实施方式
在图1的示例方法100中，步骤101包括提供衬底，该衬底包括具有顶侧半导体表面的至少一个晶体管。晶体管的第一端子连接到键合焊盘，该键合焊盘包括在顶侧半导体表面上的键合焊盘金属。在一个实施例中，键合焊盘金属可包括铝(Al)。然而，键合焊盘材料可以包括其他金属，诸如铜，并且还可以包括金属合金。
晶体管可以是功率垂直金属氧化物半导体(MOS)晶体管，其具有在衬底的顶侧半导体表面上的栅电介质上的栅电极。更一般地，该功率晶体管可以包括：包括晶闸管(紧密耦合的双极结型晶体管对，也被称为硅控整流器)的双极晶体管；包括结型栅场效应晶体管(JFET)的场效应晶体管(FET)；包括双扩散金属氧化物半导体(DMOS)的金属氧化物半导体场效应晶体管(MOSFET)；高电子迁移率晶体管(HEMT，诸如GaNHEMT)；以及绝缘栅双极晶体管(IGBT)。示例衬底包括硅和GaN，并且顶侧半导体表面可以与衬底材料相同或者不同。
步骤102包括在底部介电层上形成包括底部介电层和顶部介电层的介电堆叠，该介电堆叠具有在键合焊盘上方穿过介电堆叠的接触孔。在一个实施例中，底部介电层为介电堆叠，其包括在氧氮化硅层上的原硅酸四乙酯(TEOS)衍生的氧化硅层上的氮化硅层，并且第二介电层是比底部介电层更厚的聚酰亚胺层。接触孔内的底部介电层的外边缘延伸超过顶部介电层的外边缘，以限定具有键合焊盘边缘的暴露的键合焊盘区域。
图2A是具有部分完成的键合焊盘结构的半导体管芯200的横截面视图，其示出带有顶侧半导体表面206的衬底205，所述顶侧半导体表面206上具有包括底部介电层211和顶部介电层212的介电堆叠，该介电堆叠具有在键合焊盘215上方穿过介电堆叠的接触孔239。
晶体管被显示为示例性的n通道垂直双扩散MOS(VDMOS)功率晶体管220，其具有被示出为其栅电极221的第一端子，该栅电极在连接到键合焊盘215的栅电介质229上。晶体管220的漏极被示出为222且源极被示出为223，其中源极接触点223a在衬底205的底侧上。晶体管220包括p型主体224。漏极222通常连接到示例键合焊盘。接触孔239内的底部介电层211的外边缘延伸超过顶部介电层212的外边缘，以导致键合焊盘215具有带有键合焊盘边缘的暴露的键合焊盘区域。
步骤103a包括沉积第一金属层，并且步骤103b包括在第一金属层上沉积第二金属层。第一金属层的沉积和第二金属层的沉积都可以包括溅射。然而，镀覆(plating)也可以用于沉积这些金属层中的任一个。图2B为具有部分完成的键合焊盘结构的半导体管芯230的横截面视图，其示出第二金属层227在第一金属层226上，包括在键合焊盘215上方。第一金属层226可以包括镍(Ni)。如果第一金属层226包括Ni，则用于刻蚀第一金属层226的湿刻蚀剂可以包括硝酸(HNO3)。第二金属层227可以包括金属，诸如银和金。
步骤104包括完全地(exclusively)在接触孔239内形成第一光刻胶层。用于该步骤的掩模被命名为金属掩模1。金属掩模1边缘在底部介电层211上，但在顶部介电层212内，并且因此完全地在接触孔239内。使用金属掩模1的光刻法形成具有完全地在接触孔239内的第一光刻胶层的光刻胶图案。图2C是具有部分完成的键合焊盘结构的半导体管芯240的横截面视图，其示出第一光刻胶层233完全地在键合焊盘215上方的接触孔239内。
步骤105包括湿法刻蚀第二金属层227，以使第二金属层227从接触孔239中的底部介电层211的侧壁凹进。如果第二金属层包括Ag，则用于刻蚀第二金属层227的湿刻蚀剂可以包括硫酸(H2SO4)和磷酸(H3PO4)的混合物。
图2D是半导体管芯250的横截面视图，其示出在湿法刻蚀第二金属层227以使第二金属层227从接触孔239中的底部介电层211的侧壁凹进之后的部分完成的键合焊盘结构。步骤106包括完全地在接触孔内形成第二光刻胶层。用于该步骤的掩模被命名为金属掩模2。金属掩模2边缘在底部介电层211上，但在顶部介电层212内，并且因此完全地在接触孔239内。使用金属掩模2的光刻法形成具有完全地在接触孔239内的第二光刻胶层的光刻胶图案。图2E是具有部分完成的键合焊盘结构的半导体管芯260的横截面视图，其示出第二光刻胶层234完全地在接触孔239内。
步骤107包括湿法刻蚀第一金属层226以使第一金属层226从顶部介电层212凹进，其中第一金属层226在键合焊盘边缘上方延伸到底部介电层211上。图2F是具有完成的键合焊盘结构的半导体管芯270的横截面视图，其示出第一金属层226从顶部介电层212凹进并在键合焊盘215的键合焊盘边缘上方延伸到底部介电层211上，以及第二金属层227在第一金属层226的区域上和区域内。
该工艺通常继续添加后侧金属，然后继续进行划片和封装(其通常是随后的)。在一个实施例中，该封装包括两个(2个)NMOS功率垂直功率晶体管(诸如每个是图2A中的VDMOS功率晶体管220)的焊料居间堆叠，其中第一垂直功率晶体管的源极侧向下位于印刷电路板(PCB)上的引线框上，第一金属夹(clip)在连接到引线框的引线的第一垂直功率晶体管的漏极侧上，第二垂直功率晶体管的漏极侧向下位于第一金属夹上，并且第二金属夹在连接到引线框的引线的第二垂直功率晶体管的源极侧上。可以从连接到第一垂直功率晶体管和第二垂直功率晶体管的各自栅电极的示例键合焊盘到引线框的引线作出键合线连接。
在图3的图表300中，第二金属层被命名为Ag，并且第一金属层被命名为Ni。示出了底部介电层211和顶部介电层212。第二金属边缘(示出为具有标题“Ag停止线”的虚线)从底部介电层211的边缘凹进一定距离。该距离由在底部介电层211上示出的金属掩模1图案边缘与来自湿法刻蚀工艺的Ag层的横向刻蚀一起确定。不同的湿法刻蚀时间导致基本上相同的Ag停止线位置，直到刻蚀时间超过大约3分钟，这导致横向刻蚀速率的迅速增大，从而导致Ag层被刻蚀到键合焊盘的中心，这是不可接受的结果。为了左右移动Ag停止线，可以移动金属掩模1边缘。
对于用于刻蚀Ni层的金属掩模2，已经发现掩模图案以确定Ni层所得(resulting)轮廓，因此可以通过增加或减少湿法刻蚀时间来控制所得Ni层边缘停止时的所得轮廓。然而，已经发现在金属掩模1的边缘和顶部介电层212之间示出的间隙对所得Ni轮廓具有显著影响。随着间距增大，横向刻蚀速率增大。因此，基于图案尺寸，间隔可以被改变以增大或减小刻蚀速率，这实现更好的工艺控制，特别是在较小的图案上。
基于测试，示例实施例已经被发现有助于避免被称为步进镀覆(stepplating)的缺陷，该缺陷可能发生在Al键合焊盘上方的常规金属镀覆工艺中，其中Ni不在所有键合焊盘金属边缘上方延伸。缺少沿着任一键合焊盘边缘的Ni通常由于键合焊盘上暴露的Al而导致晶圆废料。由于已经发现导致不同侧壁位置处的不同Ni轮廓(即使在一个键合焊盘上)，因此常规金属镀覆工艺的挑战在于难以控制Al键合焊盘上的Ni的良好均匀性。已经发现金属溅射提供更好的均匀性控制并且在湿法刻蚀之后为每个管芯提供基本相同的Ni轮廓。
对于键合焊盘尺寸，由于通过键合焊盘上方的接触孔和湿法刻蚀形成示例凹部的掩模容差，实际上加工的最小键合焊盘尺寸为大约1mm乘以0.7mm。然而，示例实施例适合于低至至少大约0.5mm乘以0.5mm的键合焊盘尺寸。
示例实施例可以用于形成包括离散器件(诸如功率晶体管)或IC的半导体管芯，其可以被集成到多种组装流中以形成多种不同的器件和相关产品。半导体管芯可以包括在其中的各种元件和/或在其上的层，包括势垒层、介电层、器件结构、有源元件和无源元件，诸如源极区、漏极区、位线、基极、发射极、集电极、导电线和导电通孔。此外，半导体管芯可以由各种工艺形成，包括双极型、CMOS、BICMOS和MEMS。
在权利要求的范围内，在所描述的实施例和其他实施例中进行修改是可能的。

Claims (10)

1.一种在半导体管芯上形成键合焊盘的方法，所述方法包括：
提供衬底，所述衬底包括具有顶侧半导体表面的至少一个晶体管，其中所述晶体管的第一端子连接到键合焊盘，所述键合焊盘包括在所述顶侧半导体表面上的键合焊盘金属；
形成包括底部介电层和顶部介电层的介电堆叠，所述介电堆叠具有在所述键合焊盘上方穿过所述介电堆叠的接触孔，其中所述接触孔内的所述底部介电层的外边缘延伸超过所述顶部介电层的外边缘，以限定具有键合焊盘边缘的暴露的键合焊盘区域；
沉积第一金属层；
在所述第一金属层上沉积第二金属层；
完全地在所述接触孔内形成第一光刻胶层；
湿法刻蚀所述第二金属层，以使所述第二金属层从所述接触孔中的所述底部介电层的侧壁凹进；
完全地在所述接触孔内形成第二光刻胶层；以及
湿法刻蚀所述第一金属层，以使所述第一金属层从所述顶部介电层凹进，其中所述第一金属层在所述键合焊盘边缘上方延伸到所述底部介电层上。
2.根据权利要求1所述的方法，其中所述键合焊盘金属包括铝，并且所述第一金属层包括镍。
3.根据权利要求2所述的方法，其中所述第二金属层包括银。
4.根据权利要求3所述的方法，其中所述湿法刻蚀所述第二金属层包括使用H2SO4和H3PO4的混合物，并且其中所述湿法刻蚀所述第一金属层包括使用HNO3。
5.根据权利要求1所述的方法，其中沉积所述第一金属层包括溅射，并且沉积所述第二金属层包括溅射。
6.根据权利要求1所述的方法，其中所述晶体管包括垂直金属氧化物半导体功率晶体管即垂直MOS功率晶体管。
7.一种晶体管，其包括：
具有顶侧半导体表面的衬底，其中所述晶体管的第一端子被连接到键合焊盘，所述键合焊盘包括在所述顶侧半导体表面上的键合焊盘金属；
包括底部介电层和顶部介电层的介电堆叠，所述介电堆叠具有在所述键合焊盘上方穿过所述介电堆叠的接触孔，其中所述接触孔内的所述底部介电层的外边缘延伸超过所述顶部介电层的外边缘，以限定具有键合焊盘边缘的暴露的键合焊盘区域，以及
在所述接触孔中的金属堆叠，所述金属堆叠包括在所述暴露的键合焊盘区域上方，其中所述金属堆叠包括：第一金属层；以及在所述第一金属层上的第二金属层；
其中在所述接触孔中，所述第二金属层从所述底部介电层的侧壁凹进，所述第一金属层从所述顶部介电层凹进，并且所述第一金属层在所述键合焊盘边缘上方延伸到所述底部介电层上。
8.根据权利要求7所述的晶体管，其中所述键合焊盘金属包括铝，并且所述第一金属层包括镍。
9.根据权利要求8所述的晶体管，其中所述第二金属层包括银。
10.根据权利要求7所述的晶体管，其中所述晶体管包括垂直金属氧化物半导体功率晶体管即垂直MOS功率晶体管。
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