CN105356935A - Cross board for realizing synchronous digital hierarchy high-order cross and realization method - Google Patents
Cross board for realizing synchronous digital hierarchy high-order cross and realization method Download PDFInfo
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- CN105356935A CN105356935A CN201510840726.0A CN201510840726A CN105356935A CN 105356935 A CN105356935 A CN 105356935A CN 201510840726 A CN201510840726 A CN 201510840726A CN 105356935 A CN105356935 A CN 105356935A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
- H04J3/1605—Fixed allocated frame structures
- H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
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Abstract
The invention relates to a cross board for realizing synchronous digital hierarchy high-order cross and a realization method. The cross board comprises a power supply module, a clock module, a maintenance and management module, a business processing module, a control module, and a communication module, the power supply module supplies power for devices and monitors voltage and current states of each power supply, the communication module receives a cross command of a host computer, analyzes the command, and sends the command to the control module, the control module receives the cross command, determines whether the command is correct, and sends cross information to the business processing module for cross processing if correct, the clock module duplicates received clock frequency multiplication for 4 channels and provides required reference clocks, and the maintenance and management module obtains voltage and current information of a board, reports to the host computer if there is anomaly, switches off the power supply of the board, and reports information such as version information, cross ship temperature, and FPGA temperature of the board to the host computer. The beneficial effects of the cross board and the method are that the 640 G*640 G cross capacity and 40 G*20 G high-order cross are realized, the operation is simple, and the cross switching is accurate, timely, and stable.
Description
Technical field
The present invention relates to a kind of optical fiber communication cross board, particularly a kind of cross board and implementation method realizing SDH (Synchronous Digital Hierarchy) high order cross.
Technical background
Optical fiber communication is because transmission capacity is large, loss is little, lightweight, volume is little, anti-electromagnetic interference capability is strong and the advantage such as good confidentiality, in an increasingly wide range of applications in the communications, not only backbone network, metropolitan area network all adopt Optical Fiber Transmission, and Access Network also generally adopts optical fiber to realize converging.Problem brought thus is, carrying out to vast as the open sea optical-fiber network information the difficulty that technology intercepts and scout increasing, when especially realizing when Large Copacity accesses intersecting, is very large challenge to hardware circuit design.
Summary of the invention
In view of present technology Problems existing, the invention provides a kind of cross board realizing SDH high order cross, cross chips is utilized to achieve the cross-capacity of 640G × 640G, and utilize FPGA to achieve the high order cross of 40G × 20G, concrete technical scheme is, a kind of cross board realizing SDH (Synchronous Digital Hierarchy) high order cross, comprise supply module, clock module, safeguard and administration module, Service Processing Module, control module and communication module six functional modules, it is characterized in that: hot plug module connects supply module with 48V Voltage rails, supply module is powered to whole circuit, hot plug module is also powered to maintenance and administration module with 3.3V Voltage rails, clock module respectively with Service Processing Module, the unidirectional connection of communication module, Service Processing Module and control module are bi-directionally connected by parallel port, control module and communication module are bi-directionally connected by I2C interface, control module and maintenance and administration module are bi-directionally connected by serial ports, maintenance and administration module are bi-directionally connected by SPI interface and commmunication module, also by 485 interfaces, 12C interface and ZD connector are bi-directionally connected, communication module is bi-directionally connected by LVDS interface and ZD connector, ZD connector sends 19.44M clock to clock module, and be bi-directionally connected by differential lines and Service Processing Module, described supply module comprises optical coupling chip, DC/DC power module, digital power module, power supply chip, optical coupling chip unidirectional connection DC/DC power module, the unidirectional connection of DC/DC power module seven digital power modules, obtain seven Voltage rails needed for board, wherein 3.3V power rail connects two power supply chips and produces two and do not need configuration electric sequence Voltage rails, described communication module is made up of FPGA and FLASH, be bi-directionally connected by configuration bus, described clock module is composed in series by a MLVDS driving chip and two clock chips, described Service Processing Module comprises cross chips, FPGA, SFP+ optical module, sub-miniature A connector, cross chips is connected with ZD connector is unidirectional by input port, cross chips is bi-directionally connected by parallel interface and control module, cross chips by delivery outlet and ZD connector, FPGA, sub-miniature A connector is unidirectional is connected, FPGA is by the unidirectional connection of SERDES and SFP+ optical module.
A kind of method realizing SDH (Synchronous Digital Hierarchy) high order cross, it is characterized in that: according to the intersection instruction of host computer, cross chips is utilized to carry out cross processing to the high-speed SDH signal received, via ZD connector access backboard, pass out to two optical modules of this plate via FPGA simultaneously, carry out poll process, wherein supply module is responsible for power supply and the voltage detecting of whole plate device, clock module is responsible for providing the reference clock needed for communication module and Service Processing Module, to safeguard and administration module is responsible for the monitor message process of this plate and warning information reports, Service Processing Module is responsible for the 128 route circuit-switched data received to intersect according to intersection instruction, and the SDH data that 8 circuit-switched data copied synthesize two-way 10G by FPGA are exported, control module is responsible for cross-over control and the adjustment of balanced preemphasis of cross chips, communication module is responsible for the intersection order that reception host computer is sent, Service Processing Module is handed down to after parsing.
Technique effect of the present invention is, achieves the cross-capacity of 640G × 640G and the high order cross of 40G × 20G, to complete intersection poll, simple to operate, and the switching that intersects is accurate, real-time, stable.
Accompanying drawing explanation
Fig. 1. system module circuit block diagram.
Fig. 2. supply module circuit block diagram.
Fig. 3. communication module circuit block diagram.
Fig. 4. clock module circuit block diagram.
Fig. 5. Service Processing Module circuit block diagram.
Embodiment
As shown in Figure 1, system function division is six functional modules, supply module, communication module, control module, Service Processing Module, clock module and maintenance and administration module.Hot plug module connects supply module with 48V Voltage rails, supply module is powered to whole circuit, hot plug module is also powered to maintenance and administration module with 3.3V Voltage rails, clock module respectively with Service Processing Module, the unidirectional connection of communication module, Service Processing Module and control module are bi-directionally connected by parallel port, control module and communication module are bi-directionally connected by I2C interface, control module and maintenance and administration module are bi-directionally connected by serial ports, maintenance and administration module are bi-directionally connected by SPI interface and commmunication module, also by 485 interfaces, 12C interface and ZD connector are bi-directionally connected, communication module is bi-directionally connected by LVDS interface and ZD connector, ZD connector sends 19.44M clock to clock module, and be bi-directionally connected by differential lines and Service Processing Module,
All devices of system works main-process stream to be supply module be board are powered and monitor the electric current and voltage of all power supplys, to ensure the normal operation of board, the intersection order that communication module is issued by LVDS bus reception host computer, control module is handed down to by I2C bus after parsing, control module first checks after receiving intersection instruction that whether order is correct, if correctly intersection information will be handed down to Service Processing Module by parallel port to carry out cross processing.The 19.44M line clock frequency multiplication received is copied as 4 tunnels to 155.52M by clock module, 1 tunnel to communication module, 3 tunnels to Service Processing Module, for they provide required reference clock, to ensure the clock synchronous of system.Maintenance and administration module obtain the electric current and voltage information of board by PMBUS bus, if electric current and voltage has extremely report host computer by I2C bus, and close this plate power supply, this module also reports the version information of this plate, cross chips temperature information and FPGA temperature information by 485 buses simultaneously.
As shown in Figure 2, supply module comprises optical coupling chip, DC/DC power module, digital power module, power supply chip, the unidirectional connection power module of optical coupling chip, the unidirectional connection of power module seven digital power modules, obtain seven Voltage rails needed for board, wherein 3.3V Voltage rails connects two power supply chips and produces two and do not need configuration electric sequence Voltage rails, supply module major function is for board is powered, this plate is by 48V Power supply, support hot plug, support the real-time monitoring of voltage, electric current, can control to power on and power down order.Hot plug uses the PIM4328 hot plug module of Ericsson, except exporting 48V Voltage rails, also provide separately the Voltage rails of 3.3V, ensure that other power supplys of maintenance and administration module and board are completely isolated, even if the supply module of board breaks down like this, maintenance and administration module also can normally run, and the electric current and voltage information of each power supply of board is read by PMBUS bus, host computer is reported by IC2 bus after gathering, so that quick position fault, by controlling optocoupler TLP291, business supply module is turned off simultaneously.First business supply module uses the DC/DC power module EBVW020A0B641Z of GE to obtain 12V Voltage rails, re-use each Voltage rails that the digital power module BMR464 of Ericsson and BMR461 obtains needed for board, this digital power supports the setting of electric sequence and power down order, and can give maintenance and administration module by PMBUS bus by the state reporting of power supply.Simultaneously in order to reduce the cost of board, the LDO power supply chip TPS74401 employing TI produces not to be needed to configure electric sequence and the less Voltage rails of power consumption.
As shown in Figure 3, communication module is made up of FPGA and FLASH, be bi-directionally connected by configuration bus, the major function of communication module is handed down to control module after the intersection instructions parse of reception host computer, reports the information such as communications status and crossing condition to maintenance and administration module simultaneously.The model of FPGA is the XC6SLX25 of XILINX, and the model of FLASH is M25P128, and configuration bus is spi bus.The reference clock that XC6SLX25 uses is from clock module, ensure that the clock synchronous of system, XC6SLX25 receives the intersection instruction from host computer by LVDS bus, is handed down to control module after parsing by I2C bus, and reads the crossing condition after configuration by I2C bus.XC6SLX25 also monitors the communications status of LVDS simultaneously, and by contrasting the intersection information issuing and read back, judges that whether intersection is successful.The monitor messages such as LVDS communications status and crossing condition report maintenance and administration module by spi bus.
As shown in Figure 4, clock module is serially connected by DS176, SI5322 and SI5330 tri-chips and forms, and the FPGA that clock module primary responsibility is business module and the FPGA of communication module provides reference clock, to ensure the clock synchronous of system.The workflow of clock module is that the 19.44M differential clocks that backboard ZD connector enters exports 19.44M single ended clock to SI5322 chip through MLVDS driving chip DS176, the filtering of SI5322 chip primary responsibility clock, debounce and frequency multiplication.The clock of 155.52M is copied into 4 tunnels to clock chip SI5330, SI5330 by the differential clocks that clock exports 155.52M after SI5322 frequency multiplication, 1 tunnel to the FPGA of communication module as with reference to clock, 3 tunnels to the FPGA of Service Processing Module as with reference to clock.
The chip that control module adopts is single-chip microcomputer, and model is C8051F020, and main external interface is I2C interface, serial ports and parallel interface.The function that single chip control module mainly completes: (1) by I2C interface and commmunication module communication, the interleaving route information that received communication module issues and balanced preemphasis information.(2) communicated with Service Processing Module by parallel interface, be handed down to Service Processing Module after being resolved by the routing iinformation received, and read the crossing condition of current business processing module by this port.(3) communicated with maintenance and administration module by serial ports, the monitor messages such as intersection errors number and cross chips temperature are reported maintenance and administration module.
The chip that maintenance and administration module adopt is ARM7, and model is LPC2378, and main external interface is I2C interface, RS485 interface, SPI interface and PMBUS interface.To safeguard and the power supply of administration module is independently, with other isolated from power, even if like this other module for power supply abnormal it also can normally work, and by PMBUS bus, abnormal information to be read, is convenient to investigation fault.The function that ARM safeguards and administration module mainly completes: (1) is communicated with power module by PMBUS interface, reads the electric current and voltage information of each power module, and electric sequence and the power down order of passing through this each power module of Interface Controller.(2) be connected with backboard ZD connector by I2C interface, when the cross chips temperature of board is too high or power module breaks down, by I2C interface, warning information reported host computer.(3) by SPI interface and commmunication module communication, the monitor messages such as the LVDS bus state that reading communication module reports and optical module luminous power.(4) be connected with backboard ZD connector by 485 interfaces, by information reportings such as the version information of board, optical module luminous power and cross chips temperature to host computer.
As shown in Figure 5, Service Processing Module comprises cross chips, FPGA, SFP+ optical module, sub-miniature A connector, cross chips is connected with ZD connector is unidirectional by input port, cross chips is bi-directionally connected by parallel interface and control module, cross chips by delivery outlet and ZD connector, FPGA, sub-miniature A connector is unidirectional is connected, FPGA is by the unidirectional connection of SERDES and SFP+ optical module.Cross chips model is VSC3144, FPGA model is XC7K325T, the function that Service Processing Module specifically completes is as follows: (1) cross chips (VSC3144) is connected with control module by parallel interface, receive the intersection order that control module issues, ZD connector is beamed back after the 128 road 5G signal cross that ZD connector is received, copy 8 road 5G signals wherein to FPGA, for poll simultaneously.(2) FPGA(XC7K325T) be connected with cross chips by SERDES, receive the 8 road 5G signals copied from cross chips, through high order cross, again synthesize the signal of two-way 10G and sent by SFP+ optical module.(3) high speed signal can be deteriorated by signal quality after ZD connector, pass through parallel interface, control module can arrange equilibrium and the pre-emphasis parameters of cross chips, with conditioning signal quality, and is connected to by sub-miniature A connector the eye pattern that current demand signal checked by high-speed oscilloscope.
Claims (2)
1. one kind realizes the cross board of SDH (Synchronous Digital Hierarchy) high order cross, comprise supply module, clock module, safeguard and administration module, Service Processing Module, control module and communication module six functional modules, it is characterized in that: hot plug module connects supply module with 48V Voltage rails, supply module is powered to whole circuit, hot plug module is also powered to maintenance and administration module with 3.3V Voltage rails, clock module respectively with Service Processing Module, the unidirectional connection of communication module, Service Processing Module and control module are bi-directionally connected by parallel port, control module and communication module are bi-directionally connected by I2C interface, control module and maintenance and administration module are bi-directionally connected by serial ports, maintenance and administration module are bi-directionally connected by SPI interface and commmunication module, also by 485 interfaces, 12C interface and ZD connector are bi-directionally connected, communication module is bi-directionally connected by LVDS interface and ZD connector, ZD connector sends 19.44M clock to clock module, and be bi-directionally connected by differential lines and Service Processing Module, described supply module comprises optical coupling chip, DC/DC power module, digital power module, power supply chip, optical coupling chip unidirectional connection DC/DC power module, the unidirectional connection of DC/DC power module seven digital power modules, obtain seven Voltage rails needed for board, wherein 3.3V power rail connects two power supply chips and produces two and do not need configuration electric sequence Voltage rails, described communication module is made up of FPGA and FLASH, be bi-directionally connected by configuration bus, described clock module is composed in series by a MLVDS driving chip and two clock chips, described Service Processing Module comprises cross chips, FPGA, SFP+ optical module, sub-miniature A connector, cross chips is connected with ZD connector is unidirectional by input port, cross chips is bi-directionally connected by parallel interface and control module, cross chips by delivery outlet and ZD connector, FPGA, sub-miniature A connector is unidirectional is connected, FPGA is by the unidirectional connection of SERDES and SFP+ optical module.
2. one kind realizes the method for SDH (Synchronous Digital Hierarchy) high order cross, it is characterized in that: according to the intersection instruction of host computer, cross chips is utilized to carry out cross processing to the high-speed SDH signal received, via ZD connector access backboard, pass out to two optical modules of this plate via FPGA simultaneously, carry out poll process, wherein supply module is responsible for power supply and the voltage detecting of whole plate device, clock module is responsible for providing the reference clock needed for communication module and Service Processing Module, to safeguard and administration module is responsible for the monitor message process of this plate and warning information reports, Service Processing Module is responsible for the 128 route circuit-switched data received to intersect according to intersection instruction, and the SDH data that 8 circuit-switched data copied synthesize two-way 10G by FPGA are exported, control module is responsible for cross-over control and the adjustment of balanced preemphasis of cross chips, communication module is responsible for the intersection order that reception host computer is sent, Service Processing Module is handed down to after parsing.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107528635A (en) * | 2017-08-17 | 2017-12-29 | 北京广利核系统工程有限公司 | Communicator and method based on SFP optical modules |
| CN108023839A (en) * | 2017-12-13 | 2018-05-11 | 天津光电通信技术有限公司 | One kind is applied to Tb/s grades of optical network signal switching equipment and its control system |
| CN108933971A (en) * | 2018-04-13 | 2018-12-04 | 电信科学技术第五研究所有限公司 | More equipment cross exchange control methods |
| CN109861782A (en) * | 2018-12-07 | 2019-06-07 | 天津光电通信技术有限公司 | A kind of SDH protocol signal analysis platform based on PCIE analog input card |
| CN111092361A (en) * | 2019-12-06 | 2020-05-01 | 华东师范大学重庆研究院 | Optical comb time-frequency intelligent control method and system |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107528635A (en) * | 2017-08-17 | 2017-12-29 | 北京广利核系统工程有限公司 | Communicator and method based on SFP optical modules |
| CN107528635B (en) * | 2017-08-17 | 2024-03-19 | 北京广利核系统工程有限公司 | Communication device and method based on SFP optical module |
| CN108023839A (en) * | 2017-12-13 | 2018-05-11 | 天津光电通信技术有限公司 | One kind is applied to Tb/s grades of optical network signal switching equipment and its control system |
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| US11664635B2 (en) | 2019-12-06 | 2023-05-30 | Chongqing Institute Of East China Normal University | Time and frequency method and system for optical comb |
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