CN105334084A - Preparation method of integrated circuit chip failure analysis sample - Google Patents
Preparation method of integrated circuit chip failure analysis sample Download PDFInfo
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- CN105334084A CN105334084A CN201410308089.8A CN201410308089A CN105334084A CN 105334084 A CN105334084 A CN 105334084A CN 201410308089 A CN201410308089 A CN 201410308089A CN 105334084 A CN105334084 A CN 105334084A
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Abstract
The invention relates to a preparation method of an integrated circuit chip failure analysis sample. The method includes the following steps: smearing a packaging glue on the integrated circuit chip sample to cover the part required for failure analysis by the packaging glue; heat-curing the sample with packaging glue; and polishing the cured sample until part requiring failure analysis. The method uses cured packaging glue to strengthen the part requiring failure analysis, so as to avoid deformation in the polishing process, and preserve the original appearance. The preparation process does not need expensive equipment and the preparation conditions can be met easily.
Description
Technical field
The present invention relates to semiconductor devices, particularly relate to a kind of preparation method of integrated circuit (IC) chip failure analysis sample.
Background technology
For the consideration of manufacturing cost, in integrated circuit (IC) chip lead bonding technology, copper cash adopt by increasing company.But the characteristic that the intrinsic hardness of copper cash is corroded greatly and easily makes the requirement of copper wire bonding technique to the aluminium thickness of chip higher, also easily occurs the failure phenomenon such as (peeling), crater, cracking that comes off in bonding process.Therefore, the failure analysis demand lost efficacy for copper wire bonding also gets more and more.Section morphology analysis is conventional analytical approach, and a kind of traditional solution is that pattern is observed in polishing after die package.
But generally only have encapsulation factory to have the ability chip package, the failure analysis laboratory of WaferFoundry unspecial sealed in unit.
Summary of the invention
Based on this, be necessary to provide a kind of preparation method preparing the integrated circuit (IC) chip failure analysis sample that required condition easily meets.
A preparation method for integrated circuit (IC) chip failure analysis sample, comprises the following steps: to smear packaging plastic on integrated circuit (IC) chip sample, makes packaging plastic cover the position needing to carry out failure analysis; The sample coating packaging plastic is heating and curing; Sample after solidification is polished to the described position needing to carry out failure analysis.
Wherein in an embodiment, described on integrated circuit (IC) chip sample, smear the step of packaging plastic before, be also included in the described position of carrying out failure analysis that needs and carry out the step marked; Described by solidification after sample be polished to the described step needing the position of carrying out failure analysis, be according to marker for judgment polishing institute to position.
Wherein in an embodiment, described mark is laser labelling.
Wherein in an embodiment, describedly needing the position of carrying out failure analysis to carry out the step marked, is at the described laser labelling needing the both sides at the position of carrying out failure analysis respectively to stamp a perpendicular strip.
Wherein in an embodiment, described step of smearing packaging plastic on integrated circuit (IC) chip sample is placed on slide glass by integrated circuit (IC) chip sample to smear packaging plastic again; The described step be heating and curing to the sample coating packaging plastic is heating and curing together with described slide glass; Described by solidification after sample be polished to the described step needing the position of carrying out failure analysis, be polishing together with described slide glass.
Wherein in an embodiment, described slide glass is silicon chip.
Wherein in an embodiment, described packaging plastic is black glue.
Wherein in an embodiment, the described step be heating and curing to the sample coating packaging plastic is that sample is heated to 125 degrees Celsius.
Wherein in an embodiment, described sample after solidification is polished to described need the step at the position of carrying out failure analysis before, also comprise the step at room temperature naturally cooled by the sample after being heating and curing.
Wherein in an embodiment, describedly the position of carrying out failure analysis is needed to be pad.
Said integrated circuit chip failure analyzes the preparation method of sample, being reinforced, avoiding its stress deformation in polishing process, thus can retain primary morphology by the packaging plastic of solidification to needing the position of carrying out failure analysis.Preparation process does not need to use expensive equipment, and preparation condition is easy to be satisfied.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will become more clear.Reference numeral identical in whole accompanying drawing indicates identical part, and does not deliberately draw accompanying drawing by physical size equal proportion convergent-divergent, focuses on purport of the present invention is shown.
Fig. 1 is the process flow diagram of the preparation method of integrated circuit (IC) chip failure analysis sample in an embodiment;
Fig. 2 is the schematic diagram respectively stamping the laser labelling of a perpendicular strip in the both sides of pad;
Fig. 3 is the integrated circuit (IC) chip sample be placed in an embodiment on slide glass, and gluing and solidification after schematic diagram.
Embodiment
For enabling object of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Fig. 1 is the process flow diagram of the preparation method of integrated circuit (IC) chip failure analysis sample in an embodiment.
S10, packaging plastic smeared by integrated circuit (IC) chip sample, makes packaging plastic cover the position needing to carry out failure analysis.
For sample more greatly and do not need the situation of positioning analysis, during follow-up polishing, operating personnel do not need to rely on mark just can be polished to desired location more exactly, therefore directly can smear appropriate packaging plastic on sample.The gluing tool that writing brush, needle tubing etc. are common can be adopted during gluing.
S20, is heating and curing to the sample coating packaging plastic.
Heat with the heating arrangement of band function of temperature control, packaging plastic is solidified.The simple heating arrangement such as temp. Control electric stove, baking oven can be adopted.Sample self-heating apparatus can be taken out after being heating and curing, treat that it cools naturally.
S30, is polished to the sample after solidification the position needing to carry out failure analysis.
Just can observe with microscope (such as SEM) after polishing completes and need the pattern at the position of carrying out failure analysis.
In the present embodiment, the position of carrying out failure analysis is needed to be pad (PAD).Due to pad and copper ball surface unprotect layer, before plastic packaging, metal directly exposes, if directly carry out polishing, due to the ductility of metal, must cause metal extrusion and destroy its primary morphology.Said integrated circuit chip failure analyzes the preparation method of sample, being reinforced, avoiding its stress deformation in polishing process, thus can retain primary morphology by the packaging plastic of solidification to needing the position of carrying out failure analysis.Preparation process does not need to use expensive equipment, and preparation condition is easy to meet.And materials are few, expense is low, simple to operate.
In the present embodiment, packaging plastic adopts black glue (Blackadhesive) conventional in Soft Roll envelope (chiponboard, COB) technology, and it is a kind of thermosets, principal ingredient is epoxy resin, and the difference according to manufacturer and model can add hardening agent and filler.Inventor, by the trial to lot of materials, finds that the polishing effect of the hardness after the mobility of the black glue of COB, solidification and reality can meet demand preferably.
Little for sample, need the situation positioning analysis, can the position of carrying out failure analysis needed to mark before step S10.So in step s 30, just the position of carrying out failure analysis can whether be polished to according to marker for judgment.Wherein in an embodiment, be the laser labelling respectively stamping a perpendicular strip in the both sides of target land 42, as shown in Figure 2 (follow-up polishing is from the top of Fig. 2 toward below polishing).When polishing to laser labelling, mark can expose, and operating personnel judge whether that polishing is to desired location accordingly.After traditional encapsulation, the technology of pattern is observed in polishing, because plastic-sealed body is nontransparent, be difficult to accurately locate, therefore the preparation method that the said integrated circuit chip failure adopting laser labelling to position analyzes sample can be polished to desired position more accurately.
Wherein in an embodiment, for the situation of small sample, integrated circuit (IC) chip sample 40 can be placed on slide glass 50 and smear packaging plastic again by step S10, as shown in Figure 3.In step S20, be heating and curing by slide glass 50 together with integrated circuit (IC) chip sample 40, integrated circuit (IC) chip sample 40 covers and is fixed on slide glass 50 by the packaging plastic 60 after having solidified.In step s 30, related slide glass 50 carries out polishing together.
Wherein in an embodiment, slide glass 50 adopts thin silicon wafer.Relative to use metal substrate, thin silicon wafer is less to the loss of consumptive material when polishing, can be cost-saving.
Inventor finds through long period of experiments research, and when packaging plastic adopts black glue, the temperature be heating and curing in step S20 is advisable sample to be heated to 125 degrees centigrade.Start can to take off sample after solidification until black glue at room temperature naturally to cool.It should be noted that when using temp. Control electric stove, the temperature of equipment display and the actual temperature of sample have certain error, and when such as showing 160 degrees Celsius, the temperature of sample only has 125 degrees Celsius.
The preparation method of integrated circuit (IC) chip failure analysis sample of the present invention, can be widely used in the chip sample not carrying out CP (Chipprobe) test, carry out CP test, bonding.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a preparation method for integrated circuit (IC) chip failure analysis sample, comprises the following steps:
Packaging plastic smeared by integrated circuit (IC) chip sample, makes packaging plastic cover the position needing to carry out failure analysis;
The sample coating packaging plastic is heating and curing;
Sample after solidification is polished to the described position needing to carry out failure analysis.
2. the preparation method of integrated circuit (IC) chip failure analysis sample according to claim 1, it is characterized in that, described on integrated circuit (IC) chip sample, smear the step of packaging plastic before, be also included in the described position of carrying out failure analysis that needs and carry out the step marked; Described by solidification after sample be polished to the described step needing the position of carrying out failure analysis, be according to marker for judgment polishing institute to position.
3. the preparation method of integrated circuit (IC) chip failure analysis sample according to claim 2, is characterized in that, described mark is laser labelling.
4. the preparation method of integrated circuit (IC) chip failure analysis sample according to claim 3, it is characterized in that, describedly needing the position of carrying out failure analysis to carry out the step marked, is at the described laser labelling needing the both sides at the position of carrying out failure analysis respectively to stamp a perpendicular strip.
5. the preparation method of integrated circuit (IC) chip failure analysis sample according to claim 1, is characterized in that, described step of smearing packaging plastic on integrated circuit (IC) chip sample, is to be placed on slide glass by integrated circuit (IC) chip sample to smear packaging plastic again; The described step be heating and curing to the sample coating packaging plastic is heating and curing together with described slide glass; Described by solidification after sample be polished to the described step needing the position of carrying out failure analysis, be polishing together with described slide glass.
6. the preparation method of integrated circuit (IC) chip failure analysis sample according to claim 5, is characterized in that, described slide glass is silicon chip.
7. the preparation method of integrated circuit (IC) chip failure analysis sample according to claim 1, is characterized in that, described packaging plastic is black glue.
8. the preparation method of integrated circuit (IC) chip failure analysis sample according to claim 1, is characterized in that, the described step be heating and curing to the sample coating packaging plastic is that sample is heated to 125 degrees Celsius.
9. the preparation method of integrated circuit (IC) chip failure analysis sample according to claim 1, it is characterized in that, described sample after solidification is polished to described need the step at the position of carrying out failure analysis before, also comprise the step at room temperature naturally cooled by the sample after being heating and curing.
10. according to the preparation method of the integrated circuit (IC) chip failure analysis sample in claim 1-9 described in any one, it is characterized in that, describedly need the position of carrying out failure analysis to be pad.
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| CN201410308089.8A CN105334084B (en) | 2014-06-30 | 2014-06-30 | The preparation method of IC chip failure analysis sample |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107170676A (en) * | 2017-05-26 | 2017-09-15 | 武汉新芯集成电路制造有限公司 | A kind of method for improving semiconductor structure side section flatness |
| CN107894359A (en) * | 2017-12-13 | 2018-04-10 | 武汉电信器件有限公司 | Chip of laser failure positioning analysis sample preparation methods and middleware |
| CN109725246A (en) * | 2017-10-31 | 2019-05-07 | 无锡华润上华科技有限公司 | The failure analysis method and system of integrated circuit |
| CN112798931A (en) * | 2020-12-31 | 2021-05-14 | 苏州日月新半导体有限公司 | Novel integrated circuit failure analysis and detection method |
| CN114088982A (en) * | 2021-11-24 | 2022-02-25 | 胜科纳米(苏州)股份有限公司 | Method and system for SCM section sample nondestructive positioning |
| WO2022227339A1 (en) * | 2021-04-28 | 2022-11-03 | 长鑫存储技术有限公司 | Wafer grinding method and wafer failure analysis method |
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| US20030022603A1 (en) * | 2001-03-13 | 2003-01-30 | Schlumberger Technologies, Inc. | Method for global die thinning and polishing of flip-chip packaged integrated circuits |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107170676A (en) * | 2017-05-26 | 2017-09-15 | 武汉新芯集成电路制造有限公司 | A kind of method for improving semiconductor structure side section flatness |
| CN107170676B (en) * | 2017-05-26 | 2019-08-30 | 武汉新芯集成电路制造有限公司 | A method of improving semiconductor structure side section flatness |
| CN109725246A (en) * | 2017-10-31 | 2019-05-07 | 无锡华润上华科技有限公司 | The failure analysis method and system of integrated circuit |
| CN109725246B (en) * | 2017-10-31 | 2021-05-11 | 无锡华润上华科技有限公司 | Failure analysis method and system for integrated circuit |
| CN107894359A (en) * | 2017-12-13 | 2018-04-10 | 武汉电信器件有限公司 | Chip of laser failure positioning analysis sample preparation methods and middleware |
| CN112798931A (en) * | 2020-12-31 | 2021-05-14 | 苏州日月新半导体有限公司 | Novel integrated circuit failure analysis and detection method |
| WO2022227339A1 (en) * | 2021-04-28 | 2022-11-03 | 长鑫存储技术有限公司 | Wafer grinding method and wafer failure analysis method |
| CN114088982A (en) * | 2021-11-24 | 2022-02-25 | 胜科纳米(苏州)股份有限公司 | Method and system for SCM section sample nondestructive positioning |
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| CN105334084B (en) | 2018-06-12 |
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Effective date of registration: 20170926 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Applicant after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Applicant before: Wuxi CSMC Semiconductor Co., Ltd. |
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