CN112798931A - Novel integrated circuit failure analysis and detection method - Google Patents
Novel integrated circuit failure analysis and detection method Download PDFInfo
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- CN112798931A CN112798931A CN202011624839.4A CN202011624839A CN112798931A CN 112798931 A CN112798931 A CN 112798931A CN 202011624839 A CN202011624839 A CN 202011624839A CN 112798931 A CN112798931 A CN 112798931A
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- Prior art keywords
- integrated circuit
- film
- curing agent
- resin
- circuit assembly
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- 238000004458 analytical method Methods 0.000 title claims abstract description 19
- 238000001514 detection method Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000005498 polishing Methods 0.000 claims abstract description 9
- 238000012360 testing method Methods 0.000 claims abstract description 9
- 239000003795 chemical substances by application Substances 0.000 claims description 49
- 239000011347 resin Substances 0.000 claims description 21
- 229920005989 resin Polymers 0.000 claims description 21
- -1 aliphatic amines Chemical class 0.000 claims description 9
- 239000004925 Acrylic resin Substances 0.000 claims description 7
- 229920000178 Acrylic resin Polymers 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 7
- 229920000647 polyepoxide Polymers 0.000 claims description 7
- 150000001412 amines Chemical class 0.000 claims description 6
- 239000004952 Polyamide Substances 0.000 claims description 5
- 229920002647 polyamide Polymers 0.000 claims description 5
- 150000008065 acid anhydrides Chemical group 0.000 claims description 3
- 150000008064 anhydrides Chemical class 0.000 claims description 3
- 150000004982 aromatic amines Chemical class 0.000 claims description 3
- WPYMKLBDIGXBTP-UHFFFAOYSA-N benzoic acid Chemical compound OC(=O)C1=CC=CC=C1 WPYMKLBDIGXBTP-UHFFFAOYSA-N 0.000 claims description 3
- QGBSISYHAICWAH-UHFFFAOYSA-N dicyandiamide Chemical compound NC(N)=NC#N QGBSISYHAICWAH-UHFFFAOYSA-N 0.000 claims description 3
- LZFQGEMBQPYJJJ-UHFFFAOYSA-N ethanamine;trichloroborane Chemical compound CCN.ClB(Cl)Cl LZFQGEMBQPYJJJ-UHFFFAOYSA-N 0.000 claims description 3
- 150000002460 imidazoles Chemical class 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000001723 curing Methods 0.000 description 44
- 239000003292 glue Substances 0.000 description 24
- 239000000853 adhesive Substances 0.000 description 12
- 230000001070 adhesive effect Effects 0.000 description 12
- 239000000084 colloidal system Substances 0.000 description 8
- 238000007789 sealing Methods 0.000 description 8
- WVDDGKGOMKODPV-UHFFFAOYSA-N Benzyl alcohol Chemical compound OCC1=CC=CC=C1 WVDDGKGOMKODPV-UHFFFAOYSA-N 0.000 description 6
- 239000002390 adhesive tape Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002904 solvent Substances 0.000 description 3
- VILCJCGEZXAXTO-UHFFFAOYSA-N 2,2,2-tetramine Chemical compound NCCNCCNCCN VILCJCGEZXAXTO-UHFFFAOYSA-N 0.000 description 2
- RNLHGQLZWXBQNY-UHFFFAOYSA-N 3-(aminomethyl)-3,5,5-trimethylcyclohexan-1-amine Chemical compound CC1(C)CC(N)CC(C)(CN)C1 RNLHGQLZWXBQNY-UHFFFAOYSA-N 0.000 description 2
- IMUDHTPIFIBORV-UHFFFAOYSA-N aminoethylpiperazine Chemical compound NCCN1CCNCC1 IMUDHTPIFIBORV-UHFFFAOYSA-N 0.000 description 2
- 235000019445 benzyl alcohol Nutrition 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2898—Sample preparation, e.g. removing encapsulation, etching
Abstract
The embodiment of the application relates to a novel integrated circuit failure analysis and detection method, which comprises the following steps of: forming a first film; placing an integrated circuit assembly on the first film; and forming a second film over the integrated circuit element and the first film to obtain a film-sealed integrated circuit element; wherein the first film and the second film enclose an entire outer surface of the integrated circuit assembly. According to another embodiment of the present application, a lapping method for integrated circuit device testing includes providing a sealed film integrated circuit device obtained according to the novel integrated circuit failure analysis detection method described above; and polishing in a direction toward one surface of the encapsulated integrated circuit assembly. The novel integrated circuit failure analysis and detection method provided by the embodiment of the application can effectively solve the problems encountered in the traditional technology.
Description
Technical Field
Embodiments of the present application relate generally to the field of semiconductors, and more particularly, to a novel integrated circuit failure analysis detection method.
Background
In a test for failure analysis of an integrated circuit device, a sealing process is first performed on the integrated circuit device. The conventional film sealing process may use a positioning clip or a double-sided tape to fix the ic package, then pour the glue into a mold/container containing the fixed ic package, stand for a certain time to cure the glue, and finally grind the cured glue pillar containing the ic package to test the specific part of the ic package. The use of the positioning clamp easily causes the damage of the line arc of the fixed part, and the bonding surface of the integrated circuit assembly and the double-sided adhesive tape is small and not firmly bonded, so that the problem that the integrated circuit assembly is easy to topple due to the impact of fluid in the process of pouring the solvent is solved.
Therefore, the existing integrated circuit failure analysis detection method needs to be further improved.
Disclosure of Invention
It is an object of the embodiments of the present application to provide a novel method for analyzing and detecting failure of an integrated circuit, which effectively solves some problems of the conventional techniques.
An embodiment of the present application provides a novel integrated circuit failure analysis and detection method, which includes: forming a first film; placing an integrated circuit assembly on the first film; and forming a second film over the integrated circuit element and the first film to obtain a film-sealed integrated circuit element; wherein the first film and the second film enclose an entire outer surface of the integrated circuit assembly.
According to another embodiment of the present application, wherein at least one of the first film and the second film is formed by curing.
According to another embodiment of the present application, wherein the curing agent comprises an amine-based curing agent, an anhydride-based curing agent, or a latent curing agent.
According to another embodiment of the present application, wherein the amine curing agent comprises polyamides, aliphatic amines, aromatic amines, polyetheramines or imidazoles; the acid anhydride curing agent comprises aromatic acid anhydride, aliphatic acid anhydride or alicyclic acid anhydride; latent curatives include dicyandiamide, 594,596 curative or boron trichloride-monoethylamine complex.
According to another embodiment of the present application, at least one of the first film and the second film is composed of a resin and a curing agent. Wherein the resin comprises acrylic resin or epoxy resin, and the weight ratio of the resin to the curing agent is about 1:1 to 4: 1.
according to another embodiment of the present application, wherein the weight ratio of the acrylic resin to the curing agent is about 5: 2.
according to another embodiment of the present application, wherein the weight ratio of the epoxy resin to the curing agent is about 3: 1.
according to another embodiment of the present application, wherein at least one of the first film and the second film is composed of a photo-curable resin.
Another embodiment of the present application further provides a polishing method for integrated circuit device testing, which comprises providing a sealed integrated circuit device obtained by the above-mentioned sealing method; and polishing in a direction toward one surface of the encapsulated integrated circuit assembly.
Compared with the prior art, the novel integrated circuit failure analysis and detection method provided by the embodiment of the application effectively solves the problem that the line arc at the fixed part is damaged due to the fact that the positioning clamp is used in the traditional method, also avoids the problem that the integrated circuit assembly is easy to collapse in the grinding process due to the fact that the integrated circuit assembly is directly attached to the base, and can meet the grinding requirements of multiple directions and multiple positions.
Drawings
Drawings necessary for describing embodiments of the present application or the prior art will be briefly described below in order to describe the embodiments of the present application. It is to be understood that the drawings in the following description are only some of the embodiments of the present application. It will be apparent to those skilled in the art that other embodiments of the drawings can be obtained from the structures illustrated in these drawings without the need for inventive work.
Fig. 1A to fig. 1C are schematic diagrams illustrating a conventional integrated circuit failure analysis and detection method.
FIG. 2 is a schematic diagram of another conventional integrated circuit failure analysis detection method.
Fig. 3A-3C are illustrations of a novel integrated circuit failure analysis detection method according to some embodiments of the present application.
Fig. 4A-4B are illustrations of a novel integrated circuit failure analysis detection method for integrated circuit device testing according to some embodiments of the present application.
Detailed Description
In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.
Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.
As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.
In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.
Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.
Fig. 1A to fig. 1C are schematic diagrams illustrating a conventional integrated circuit failure analysis and detection method. As shown in fig. 1A, the integrated circuit assembly 10 is erected on the base 110 of the container by using the retaining clip 112. To further secure the integrated circuit assembly 10, the bottom thereof may be adhered to the base 110 using double-sided adhesive; as shown in fig. 1B, the prepared solvent is poured into a container, and the curing is completed after standing for a certain period of time. Finally, after demolding, a glue pillar containing integrated circuit devices, such as glue pillar 12 shown in fig. 1C, can be obtained, and then glue pillar 12 can be polished.
When the glue pillar 12 is polished, the integrated circuit device 10 inside the glue pillar may be polished at different positions, for example, in the direction of arrow a in fig. 1C.
Secondly, in the conventional film sealing method, the use of the positioning clip 112 can not prevent some parts of the ic device from being sealed, and the wire loop of the ic device contacting the positioning clip is easily damaged. Moreover, since the bonding area between the positioning clip and the double-sided adhesive tape is small after the positioning clip fixes the integrated circuit assembly, the bonding is not firm, the integrated circuit assembly is easy to topple due to the impact of the adhesive in the process of toppling the solvent, so that the integrated circuit assembly in the adhesive column 12 has a certain inclination angle relative to the side surface of the adhesive column, and therefore, the adhesive column 12 obtained by the conventional film sealing method needs to be grinded in an inclined state, so that the grinding of the adhesive column 12 is not easy to control, and the specific implementation is also difficult.
To address the above problems, the current common solution is to fix the ic package on the mold/container base horizontally by using the double-sided adhesive tape instead of using the positioning clip. FIG. 2 is a schematic diagram of another conventional sealing film and polishing method for testing an integrated circuit device. As shown in fig. 2, since the way of fixing the ic package by the positioning clip is removed, the ic package 10 is directly attached to the mold/container base by the double-sided adhesive tape, the bonding surface is large, the risk of falling of the ic package due to small bonding surface is avoided, and the ic package is convenient to hold by hand during grinding. Meanwhile, the integrated circuit assembly is horizontally arranged in the rubber column, so that the grinding direction of the integrated circuit assembly is consistent with the grinding direction of the rubber column, and the requirement of multi-directional grinding positions of the integrated circuit assembly can be met. However, since the adhesive is not completely wrapped, i.e., one side of the ic device (the side attached to the double-sided tape) is exposed outside the cured adhesive pillar, a bottom surface of the ic device cannot be completely wrapped by the adhesive, and the adhesive pillar needs to lie on one side for grinding in the subsequent side grinding process, which is likely to cause the ic device to fall off the adhesive pillar due to the driving of the grinding machine turntable.
Therefore, the application provides a novel integrated circuit failure analysis and detection method. Fig. 3A-3C are illustrations of a sealing film and polishing method for integrated circuit device testing according to some embodiments of the present application.
As shown in fig. 3A, the integrated circuit device 20 is placed over the formed first film 210, and a second film 220 is formed over the integrated circuit device 20 and the first film 210, as shown in fig. 3B. This layered curing process allows the first film 210 and the second film 220 to enclose the entire outer surface of the integrated circuit assembly 20, such as the post-demolded glue pillars 22 in fig. 3C.
Through the stepped curing mode of the above layering, the periphery of the integrated circuit assembly 20 in the glue column 22 is completely wrapped by the cured glue, so that the problem that the integrated circuit assembly is easy to collapse due to the fact that the bottom surface of the integrated circuit assembly cannot be completely wrapped by the glue and the turntable drives in the grinding process is solved.
According to some embodiments of the present application, the forming of the first film 210 or the second film 220 may include the steps of:
1. mixing the resin A and the curing agent B according to a certain proportion, and preparing a container to fill the mixed colloid of the resin A and the curing agent B;
2. pouring a part of mixed colloid of the resin A and the curing agent B into a container, standing for about a period of time, and curing the mixed colloid to form a first film 210;
3. placing the integrated circuit assembly 20 on the first film 210;
4. pouring the rest mixed colloid of the resin A and the curing agent B into a container in which the cured first film 210 and the integrated circuit assembly 20 are placed, standing for about a period of time, and finishing secondary curing after the integrated circuit assembly 20 and the first film 210 are combined with the later poured mixed colloid of the resin A and the curing agent B to form a second film 220 covering the first film 210 and the integrated circuit assembly 20; and
5. the cured integrated circuit assembly 20, the first film 210 and the second film 220 are removed from the container to obtain a film-sealed integrated circuit assembly, i.e., to form the glue pillars 22.
According to another embodiment of the present application, the resin a in the above step may be an acrylic resin, and the weight ratio of the acrylic resin to the curing agent B may be about 1:1 to 4: 1. The curing agent B can be one of polyamide curing agents and specifically comprises the following components in parts by weight: benzyl alcohol about 25%, N-aminoethylpiperazine about 25%, isophorone diamine about 25%, and triethylenetetramine about 25%. When the weight ratio of the acrylic resin to the curing agent B is about 5:2, the standing time required for curing is about 10min to 20min at room temperature, so that the cured colloid has good definition.
According to another embodiment of the present application, the curing agent B in the above step includes an amine curing agent including: polyamides, aliphatic amines, aromatic amines, polyetheramines, imidazoles or the like; curing agent B may also include anhydride-based curing agents, including: aromatic acid anhydrides, aliphatic acid anhydrides, alicyclic acid anhydrides, or the like; and curing agent B may also include latent curing agents including: dicyandiamide, 594,596 curative, boron trichloride-monoethylamine complex or the like.
According to another embodiment of the present application, the resin a in the above step may be an epoxy resin, and the weight ratio of the epoxy resin to the curing agent B may be about 2:1 to 4: 1. The curing agent B can be one of polyamide curing agents and specifically comprises the following components in parts by weight: benzyl alcohol about 25%, N-aminoethylpiperazine about 25%, isophorone diamine about 25%, and triethylenetetramine about 25%. When the weight ratio of the epoxy resin to the curing agent B is about 3:1, the standing time required by curing is about 4 hours at room temperature, so that the cured colloid has excellent adhesive force and low viscosity, and can permeate into small slits/holes, thereby better combining the colloid with an integrated circuit assembly and increasing the fitting degree.
According to another embodiment of the present disclosure, the first film 210 and/or the second film 220 may also be formed by using a photo-curable resin, the glue column cured by using the photo-curable resin has high hardness, fast curing speed, high energy utilization rate, a required curing time of about 30min of ultraviolet irradiation, and is simple to operate, economical, practical, low in organic volatile compounds (VOC), and environment-friendly. For example, the first film 210 is formed using a mixed gel of the resin a and the curing agent B, and the second film 220 is formed using a photo-curable resin. For another example, the first film 210 is formed using a photo-curable resin, and the second film 220 is formed using a mixed gel of the resin a and the curing agent B.
Fig. 4A and 4B are illustrations of a novel integrated circuit failure analysis detection method for integrated circuit device testing according to some embodiments of the present application.
Fig. 4A is a side view of the glue pillar 22, in the layered stepwise curing manner in the embodiment of the present application, since the integrated circuit assembly 20 is wrapped in the glue pillar 22 in a lying manner, i.e., the upper and lower surfaces of the integrated circuit assembly 20 are parallel to the upper and lower surfaces of the glue pillar 22. If the lower surface of the integrated circuit device 20 needs to be polished, the glue pillar 22 is only laid down and polished since the upper and lower surfaces of the integrated circuit device 20 are parallel to the surface of the first film 210 or the surface of the second film 220. As shown in fig. 4A, the polishing direction b is perpendicular to the lower surface of the integrated circuit assembly 20, and the glue pillar 22 is very convenient to hold for polishing.
By adopting the novel integrated circuit failure analysis and detection method in the embodiment of the application, the integrated circuit assembly can be placed according to the grinding position when being positioned, so that the grinding position of the glue column containing the integrated circuit assembly formed after the film sealing is convenient to control, and the grinding requirements of multiple directions and multiple positions, such as grinding wire arcs, a welding spot and the like, are met.
Fig. 4B is a top view of the glue column 22. as shown in fig. 4B, the glue column 22 can be polished along the entering direction d according to the polishing position c.
The layered stepped curing method can solve the problem that the positioning clamp easily causes the line arc of the fixed part to be damaged when the integrated circuit assembly is positioned in the traditional technology, can avoid the risk of toppling over the integrated circuit assembly during glue pouring and curing, and can also solve the problem that the integrated circuit assembly is easily broken down from glue in the grinding process due to incomplete package of the integrated circuit assembly in the current optimization method.
The technical content and technical features of the present application have been disclosed as above, however, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present application without departing from the spirit of the present application. Therefore, the protection scope of the present application should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the scope of the present application, which is covered by the claims of the present patent application.
Claims (10)
1. A novel integrated circuit failure analysis detection method comprises the following steps:
forming a first film;
placing the integrated circuit assembly on the first film; and
forming a second film over the integrated circuit device and the first film to obtain a film-sealed integrated circuit device;
wherein the first film and the second film enclose an entire outer surface of the integrated circuit component.
2. The method of claim 1, wherein at least one of the first film and the second film is formed upon curing.
3. The method of claim 1, wherein at least one of the first film and the second film is comprised of a resin and a curing agent.
4. The method of claim 3, wherein the curing agent comprises an amine curing agent, an anhydride curing agent, or a latent curing agent.
5. The method of claim 4, wherein when the curing agent is an amine curing agent, the amine curing agent comprises polyamides, aliphatic amines, aromatic amines, polyetheramines, or imidazoles; when the curing agent is an acid anhydride-based curing agent, the acid anhydride-based curing agent includes an aromatic acid anhydride, an aliphatic acid anhydride, or an alicyclic acid anhydride; when the curing agent is a latent curing agent, the latent curing agent includes dicyandiamide, 594,596 curing agent or boron trichloride-monoethylamine complex.
6. The method of claim 3, wherein the resin comprises acrylic resin or epoxy resin, and the weight ratio of the resin to the curing agent is 1:1 to 4: 1.
7. the method of claim 6, wherein the weight ratio of the acrylic resin to the curing agent is 5: 2.
8. the method of claim 6, wherein the weight ratio of the epoxy resin to the curing agent is 3: 1.
9. the method of claim 1, wherein at least one of the first film and the second film is comprised of a light curable resin.
10. A lapping method for integrated circuit device testing, comprising:
providing the encapsulated integrated circuit assembly obtained by the method of claim 1; and
the polishing is performed in a direction toward one surface of the encapsulated integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011624839.4A CN112798931A (en) | 2020-12-31 | 2020-12-31 | Novel integrated circuit failure analysis and detection method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011624839.4A CN112798931A (en) | 2020-12-31 | 2020-12-31 | Novel integrated circuit failure analysis and detection method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101075580A (en) * | 2007-06-01 | 2007-11-21 | 日月光半导体制造股份有限公司 | Method for cutting crystal wafer |
| CN101859692A (en) * | 2009-04-02 | 2010-10-13 | 日东电工株式会社 | Pressure-sensitive adhesive sheet for semiconductor wafer protection and method of attaching thereof |
| CN105334084A (en) * | 2014-06-30 | 2016-02-17 | 无锡华润上华半导体有限公司 | Preparation method of integrated circuit chip failure analysis sample |
| CN110396384A (en) * | 2019-05-07 | 2019-11-01 | 络合高新材料(上海)有限公司 | A kind of non-treated PVC high bonding in surface uses epoxy resin component |
-
2020
- 2020-12-31 CN CN202011624839.4A patent/CN112798931A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101075580A (en) * | 2007-06-01 | 2007-11-21 | 日月光半导体制造股份有限公司 | Method for cutting crystal wafer |
| CN101859692A (en) * | 2009-04-02 | 2010-10-13 | 日东电工株式会社 | Pressure-sensitive adhesive sheet for semiconductor wafer protection and method of attaching thereof |
| CN105334084A (en) * | 2014-06-30 | 2016-02-17 | 无锡华润上华半导体有限公司 | Preparation method of integrated circuit chip failure analysis sample |
| CN110396384A (en) * | 2019-05-07 | 2019-11-01 | 络合高新材料(上海)有限公司 | A kind of non-treated PVC high bonding in surface uses epoxy resin component |
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