CN109725246A - The failure analysis method and system of integrated circuit - Google Patents
The failure analysis method and system of integrated circuit Download PDFInfo
- Publication number
- CN109725246A CN109725246A CN201711050345.8A CN201711050345A CN109725246A CN 109725246 A CN109725246 A CN 109725246A CN 201711050345 A CN201711050345 A CN 201711050345A CN 109725246 A CN109725246 A CN 109725246A
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- electrical
- test data
- charge trap
- electrical test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present invention proposes the failure analysis method and system of a kind of integrated circuit, by carrying out electrical testing to integrated circuit, and obtain the first electrical test data, then charge trap Processing for removing is carried out to the integrated circuit, electrical testing is carried out to the integrated circuit, and the second electrical test data is obtained, if the difference of first electrical test data and second electrical test data is more than preset range, determine that the integrated circuit is the failure as caused by charge trap.
Description
Technical field
The present invention relates to Integrated circuit failure analysis technical field more particularly to a kind of failure analysis methods of integrated circuit
And system.
Background technique
Integrated circuit can form electricity in integrated circuit surface because of defective workmanships such as plasma thin-film deposition, plasma etchings
Lotus trap, is easy to cause ic failure.Charge trap is one of the influence factor of integrated circuit surface effect failure mechanism.
Failure point mainly is carried out to integrated circuit using failure analysis (Failure Analysis, abbreviation FA) method at present
Analysis, but failure analysis method can not directly analyze integrated circuit surface that there are charge traps to lead to ic failure
Reason.
Summary of the invention
Based on this, it is necessary to provide a kind of failure analysis method of integrated circuit.
A kind of failure analysis method of integrated circuit, comprising the following steps:
Electrical testing is carried out to integrated circuit, and obtains the first electrical test data；
Charge trap Processing for removing is carried out to the integrated circuit；
Electrical testing is carried out to the integrated circuit, and obtains the second electrical test data；
If the difference of first electrical test data and second electrical test data is more than preset range, determine
The integrated circuit is the failure as caused by charge trap.
The failure analysis method of said integrated circuit, obtain integrated circuit before carrying out charge trap Processing for removing and
Electrical test data later can analyze integrated circuit if the difference of the electrical test data of front and back is more than preset difference value
Surface is the reason of leading to ic failure there are charge trap.
Also propose a kind of failure analysis system of integrated circuit, comprising:
First device of testing electrical properties for carrying out electrical testing to integrated circuit, and obtains the first electrical test data；
Charge trap eliminates equipment, for carrying out charge trap Processing for removing to the integrated circuit；
Second device of testing electrical properties for carrying out electrical testing to the integrated circuit, and obtains the second electrical testing number
According to；
Failure analysis apparatus is connect with the first device of testing electrical properties, the second device of testing electrical properties respectively, if for described the
The difference of one electrical test data and second electrical test data is more than preset difference value, then determine the integrated circuit be by
Failure caused by charge trap.
The failure analysis system of said integrated circuit is obtained by the first device of testing electrical properties and the second device of testing electrical properties
Electrical test data of the integrated circuit before carrying out charge trap Processing for removing and later, if failure analysis apparatus analyzes
The electrical test data of front and back has differences, then can determine that integrated circuit surface there are charge trap is to lead to ic failure
The reason of.
Detailed description of the invention
Fig. 1 is the flow diagram of one of one embodiment failure analysis method；
Fig. 2 is the signal of the electrical test results of the integrated circuit in a specific embodiment before charge trap Processing for removing
Figure；
Fig. 3 is the flow diagram of one of another embodiment failure analysis method；
Fig. 4 is the schematic diagram of the electrical test results of the integrated circuit in a specific embodiment under the conditions of different-energy；
Fig. 5 is the flow diagram of one of further embodiment failure analysis method.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Referring to Fig. 1, Fig. 1 is the flow diagram of one of one embodiment failure analysis method of integrated circuit.
The failure analysis method of the integrated circuit of the present embodiment, it may include following steps:
S11: electrical testing is carried out to integrated circuit, and obtains the first electrical test data.
Integrated circuit can be semiconductor integrated circuit, i.e., interconnects classes of semiconductors device according to circuit, be integrated in half
On conductor chip.The integrated circuit that integrated circuit can be no longer valid, has concretely suspected that charge trap occur causes
Integrated circuit.Charge trap can be positive charge trap or negative electrical charge trap, and there are positive charge in positive charge trap, negative electrical charge is fallen into
There are negative electrical charges in trap.Charge trap concretely grid oxygen charge trap, dielectric charge trap etc..
For the integrated circuit of failure, if having excluded other kinds failure cause, the mistake for suspecting integrated circuit is had reason
Effect is that charge trap causes, and subsequent step then verifies this inference.
In one embodiment, before the step of carrying out electrical testing to integrated circuit, comprising:
Obtain other fail messages in addition to charge trap failure of integrated circuit；
If judging, other fail messages are not the reason of causing ic failure, and recognition integrated circuit is to need to test
Card whether there is the integrated circuit of charge trap.
S12: charge trap Processing for removing is carried out to integrated circuit.
If integrated circuit surface is implicitly present in charge trap, after carrying out charge trap Processing for removing, integrated circuit
Electrical property can change.Electrical testing, the second test data of acquisition are carried out to the integrated circuit again so in subsequent step
It can then have any different with the first test data, then can determine that there are charge traps for the integrated circuit.
Step S12, which can be, carries out positive charge trap Processing for removing to integrated circuit, or bears to integrated circuit
Charge trap Processing for removing.Charge trap neutralisation treatment specifically is carried out to integrated circuit surface using electron beam, to change collection
At the voltage-current characteristic of circuit.
In one embodiment, the step of carrying out charge trap Processing for removing to integrated circuit includes: control scanning electron microscope
The electron beam of preset energy condition, is scanned integrated circuit.Scanning process is integrated in scanning electron microscope board to being put into
Circuit controls electron beam from left to right, scanning at the uniform velocity from top to bottom.The electron beam of preset energy condition is controlled to integrated circuit
It is scanned, belongs to lossless process, integrated circuit will not be caused to damage.
Preset energy condition is the energy condition greater than 1KeV in one of the embodiments,.EV, i.e. electron-volt, refer to
The kinetic energy that one electronics obtains after being accelerated by 1 volt of voltage.
Preset energy condition should be arranged greatly, positive charge trap Processing for removing can be carried out to integrated circuit, for example, can set
It is set to 30KeV, the as beam energy under setting 30KV scanning electron microscope acceleration voltage, if because preset energy condition is arranged
It is too small, do not simply fail to the positive charge trap for neutralizing integrated circuit surface, integrated circuit can be made to escape more electronics instead.
The present invention can also carry out charge trap Processing for removing to integrated circuit using other charge trap removing methods.
In another embodiment, the step of carrying out charge trap Processing for removing to integrated circuit includes: (ultraviolet using UV
Line) illumination technique or again alloying technology to integrated circuit carry out charge trap Processing for removing.
Comprising the concrete steps that for charge trap Processing for removing is carried out to integrated circuit using UV illumination technique, light appropriate is set
Intensity and optical wavelength make the charge trap of integrated circuit surface generate transition, using the surface of UV light irradiation integrated circuit to disappear
Except the charge trap of integrated circuit surface.
It is appropriate in setting that comprising the concrete steps that for charge trap Processing for removing is carried out to integrated circuit using alloying technology again
Temperature enables the charge trap transition of integrated circuit surface using high temperature, then utilizes the protium and integrated circuit table in boiler tube
The chemical bond that face is not reacted completely is reacted, to eliminate the charge trap of integrated circuit surface.
S13: electrical testing is carried out to integrated circuit, and obtains the second electrical test data.
After carrying out charge trap Processing for removing to integrated circuit, then electrical testing is carried out to integrated circuit.
S14: if the difference of the first electrical test data and the second electrical test data is more than preset difference value, determine integrated
Circuit is the failure as caused by charge trap.Assuming that integrated circuit is the failure as caused by charge trap, show that charge trap disappears
After the inconsistent result of electrical test data before and after the processing, so that it may confirm that integrated circuit surface there are charge trap is to lead
Cause the immediate cause of ic failure.
The difference can subtract the value of the second electrical test data for the first electrical test data, or can electrically survey for second
Examination data subtract the value of the first electrical test data.If the size of the first electrical test data is greater than the second electrical test data
Size then determines that integrated circuit is the failure as caused by positive charge trap；If the size of the first electrical test data is less than second
The size of electrical test data then determines that integrated circuit is the failure as caused by negative electrical charge trap, and preset difference value may be greater than
The value of 100nA can also be arranged according to specific requirements, be not limited to the above protection scope.First electrical test data and second is electrically
Test data can be leakage data.For example, referring to Fig. 2, measuring integrated circuit in 10V before charge trap Processing for removing
Leakage current under test voltage is 1.64 μ A, and measuring leakage current of the integrated circuit under 10V test voltage after processing is
18.4nA, it is clear that less than 1.64 μ A, 1 μ A=1000nA, it is seen that neutralized a large amount of positive charge, illustrating integrated circuit, there are positive electricity
Lotus trap.As shown in Fig. 2, test voltage, which can be from -1V, is gradually increased to 10V, it can preferably find that charge trap is eliminated
Before and after the processing, the variation tendency of the leakage current of integrated circuit.
In one embodiment, if the first electrical test data is greater than preset normal specimens electrical leakage threshold value, illustrate electricity
Integrated circuit before lotus trap Processing for removing shows there is positive charge trap, and the second electrical test data is less than or equal to default
Normal specimens electrical leakage threshold value, illustrate that the positive charge trap on the integrated circuit is eliminated, then validation integrated circuit be by
Failure caused by positive charge trap.Preset normal specimens electrical leakage threshold value can be integrated circuit and failure conditions do not occurring
Under, the electrical leakage that device of testing electrical properties measures under 10V operating voltage can be any electrical leakage in 10nA~20nA.It is default
Normal specimens electrical leakage threshold value can also be specific according to specific integrated circuit and the specific operating voltage of device of testing electrical properties
Setting, is not limited to above range.
In one of the embodiments, referring to Fig. 3, the step of carrying out charge trap Processing for removing to integrated circuit is pair
Integrated circuit carries out positive charge trap Processing for removing, specifically includes the following steps:
S121: control scanning electron microscope (scanning electron microscope, abbreviation SEM) first preset energy item
First electron beam of part, is scanned integrated circuit；
S122: electrical testing is carried out to the integrated circuit after the first electronics beam scanning, and obtains first and refers to electrical testing
Data；
S123: if first is greater than preset normal specimens electrical leakage threshold value with reference to electrical test data, scanning electricity is controlled
Second electron beam of mirror the second preset energy condition, is scanned integrated circuit；Wherein the second preset energy condition is greater than the
One preset energy condition；
Electrical testing is carried out to the integrated circuit, and the step of obtaining the second electrical test data includes:
S124: electrical testing is carried out to the integrated circuit after the second electronics beam scanning, and obtains second and refers to electrical testing
Data；
S125: if second is less than or equal to preset normal specimens electrical leakage threshold value with reference to electrical test data, by the
Two reference electrical test datas are no longer scanned processing to integrated circuit as the second electrical test data.If the second ginseng
It examines electrical test data and is also greater than preset normal specimens electrical leakage range, the electronics of higher energy condition can be utilized again
Beam continues to scan on, until the electrical test data measured is less than or equal to preset normal specimens electrical leakage range, or can set
Set preset scanning times, after scanning times reach preset scanning times, though electrical test data whether be less than it is preset
Normal specimens electrical leakage range, terminates to scan, wherein is greater than for the preset energy condition in rear scanning for formerly scanning
Preset energy condition.
For example, referring to Fig. 4, before the scan, measuring collection for the integrated circuit to be verified with the presence or absence of charge trap
Electric current at circuit is 1.64 μ A, and as the first electrical test data, scanning utilizes the electronics beam scanning of 10KeV energy for the first time
The integrated circuit, and measuring electric current is 358nA, but 358nA does not reach preset normal sample electrical leakage range, then increases
The energy of big electron beam, continues to scan on the integrated circuit using the electron beam of 30KeV energy, then measures the electric current of integrated circuit
It is 18.4nA, as the second electrical test data, is in normal specimens electrical leakage range, and well below 1.64 μ A, it is clear that can
Proving the integrated circuit, there are positive charge traps.
In one of the embodiments, after step s 11, judge whether the first electrical test data is greater than default threshold
Value just executes step S12 if the first electrical test data is greater than preset normal specimens electrical leakage threshold value.For example, charge trap
Before Processing for removing, the electric current for measuring integrated circuit is significantly larger than preset normal specimens electrical leakage range, then more it is necessary to verify
Whether the integrated circuit there is positive charge trap.If the electric current for measuring integrated circuit leaks electricity approaching or at preset normal specimens
Be worth range, then may the integrated circuit do not fail or other reasons caused by failure, then without executing subsequent step.
In another embodiment, if suspecting, there is negative electrical charge trap in integrated circuit, then step S12 is to the collection
Negative electrical charge trap Processing for removing is carried out at circuit, if then step S14 includes: first electrical test data less than preset
Normal specimens electric leakage threshold value, and second electrical test data is greater than or equal to the preset normal specimens electric leakage threshold
Value, then determine that the integrated circuit is the failure as caused by negative electrical charge trap.Specifically, can be less than by the way that scanning electron microscope is arranged
The electron beam of 1KeV preset energy condition, is scanned the integrated circuit, to realize negative electrical charge trap Processing for removing.Cause
When lower for the beam energy of scanning electron microscope, integrated circuit surface runaway electron can be made, to eliminate the negative electricity of integrated circuit
Lotus trap.Can also by UV (ultraviolet light) illumination technique or again alloying technology to integrated circuit carry out the elimination of negative electrical charge trap at
Reason.
In one of the embodiments, referring to Fig. 5, the step of carrying out charge trap Processing for removing to integrated circuit is pair
Integrated circuit carries out negative electrical charge trap Processing for removing, specifically includes the following steps:
S1211: the third electron beam of control scanning electron microscope third preset energy condition is scanned integrated circuit；
S1221: carrying out electrical testing to the integrated circuit after third electronics beam scanning, and obtains third with reference to electrical testing
Data；
S1231: if third is less than preset normal specimens electrical leakage threshold value with reference to electrical test data, scanning electricity is controlled
4th electron beam of the 4th preset energy condition of mirror, is scanned integrated circuit；Wherein the 4th preset energy condition is less than
Three preset energy conditions；
Electrical testing so is carried out to integrated circuit, and the step of obtaining the second electrical test data includes:
S1241: electrical testing is carried out to the integrated circuit after the 4th electronics beam scanning, and obtains the 4th and refers to electrical testing
Data；
S1251: if the 4th is greater than or equal to preset normal specimens electrical leakage threshold value with reference to electrical test data, by the
Four reference electrical test datas are as the second electrical test data.If the 4th reference electrical test data is also less than preset
Normal specimens electrical leakage range can utilize the electron beam of more low energy condition, continue to scan on, again until the electrical testing measured
Data are greater than or equal to preset normal specimens electrical leakage range or settable preset scanning times, scanning times reach
After preset scanning times, no matter whether electrical test data is greater than preset normal specimens electrical leakage range, terminate to scan,
Wherein, the preset energy condition for formerly scanning is less than for the preset energy condition in rear scanning.
For example, before the scan, the leakage current for measuring integrated circuit is 1nA, as the first electrical test data, lower than just
Normal sample electrical leakage range suspects that there are negative electrical charge traps, first uses the electron beam of 800eV, sweep to the integrated circuit
It retouches, the leakage current for measuring integrated circuit is 5nA, is then scanned, is measured to the integrated circuit using the electron beam of 100eV
The leakage current of integrated circuit is 15nA, as the second electrical test data, is in normal specimens electrical leakage range, and be higher than 1nA,
There are negative electrical charge traps for obvious provable integrated circuit.
The failure analysis method of said integrated circuit, obtain integrated circuit before carrying out charge trap Processing for removing and
Electrical test data later can analyze integrated circuit surface and there is electricity if the electrical test data of front and back has differences
Lotus trap is the reason of leading to ic failure.
The present invention also proposes a kind of failure analysis system of integrated circuit.
The failure analysis system at chip in one embodiment, it may include:
First device of testing electrical properties for carrying out electrical testing to integrated circuit, and obtains the first electrical test data.
Charge trap eliminates equipment, for carrying out charge trap Processing for removing to integrated circuit；Charge trap eliminates equipment
It can be scanning electron microscope.
Second device of testing electrical properties for carrying out electrical testing to integrated circuit, and obtains the second electrical test data；The
One device of testing electrical properties and the second device of testing electrical properties can be the same device of testing electrical properties.
Failure analysis apparatus is connect with the first device of testing electrical properties, the second device of testing electrical properties respectively, if for the first electricity
Property test data and the second electrical test data difference exceed preset difference value, then determine that integrated circuit is caused by charge trap
Failure.Failure analysis apparatus can be the computer for having data-handling capacity.First device of testing electrical properties, the second electrical testing
Equipment and failure analysis apparatus can be the same equipment, which had both had electrical testing function, analyze function but also with data
Energy.
The failure analysis system of said integrated circuit is obtained by the first device of testing electrical properties and the second device of testing electrical properties
Electrical test data of the integrated circuit before carrying out charge trap Processing for removing and later, if failure analysis apparatus analyzes
The difference of the electrical test data of front and back exceeds preset range, then can determine that integrated circuit surface there are charge trap is to cause to collect
The reason of at circuit malfunction.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
The each technical characteristic all possible combinations applied in example are all described, as long as however lance is not present in the combination of these technical characteristics
Shield all should be the range that this specification is recorded.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but not
Limitations on the scope of the patent of the present invention therefore can be interpreted as.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of failure analysis method of integrated circuit, which comprises the following steps:
Electrical testing is carried out to integrated circuit, and obtains the first electrical test data；
Charge trap Processing for removing is carried out to the integrated circuit；
Electrical testing is carried out to the integrated circuit, and obtains the second electrical test data；
If the difference of first electrical test data and second electrical test data is more than preset difference value, determine described in
Integrated circuit is the failure as caused by charge trap.
2. the failure analysis method of integrated circuit according to claim 1, which is characterized in that described to the integrated circuit
Carry out charge trap Processing for removing the step of include:
The electron beam for controlling scanning electron microscope preset energy condition, is scanned the integrated circuit, utilizes the electron beam pair
The integrated circuit carries out charge trap neutralisation treatment, to change the voltage-current characteristic of the integrated circuit.
3. the failure analysis method of integrated circuit according to claim 2, which is characterized in that
The preset energy condition is the energy condition greater than 1KeV.
4. the failure analysis method of integrated circuit according to claim 1, which is characterized in that if described first is electrical
Test data and the difference of second electrical test data are more than preset difference value, then determine that the integrated circuit is fallen by charge
The step of failure caused by trap includes:
If first electrical test data is greater than preset normal specimens electric leakage threshold value, and second electrical test data
Less than or equal to the preset normal specimens electric leakage threshold value, then determine that the integrated circuit is the mistake as caused by positive charge trap
Effect.
5. the failure analysis method of integrated circuit according to claim 4, which is characterized in that described to the integrated circuit
Carry out charge trap Processing for removing the step of include:
The first electron beam for controlling the first preset energy of scanning electron microscope condition, is scanned the integrated circuit；
Electrical testing is carried out to the integrated circuit after the first electronics beam scanning, and obtains first and refers to electrical testing number
According to；
If described first is greater than preset normal specimens electrical leakage threshold value with reference to electrical test data, scanning electron microscope second is controlled
Second electron beam of preset energy condition, is scanned the integrated circuit；Wherein the second preset energy condition is greater than first
Preset energy condition；
It is described that electrical testing is carried out to the integrated circuit, and the step of obtaining the second electrical test data includes:
Electrical testing is carried out to the integrated circuit after the second electronics beam scanning, and obtains second and refers to electrical testing number
According to；
If described second is less than or equal to preset normal specimens electrical leakage threshold value with reference to electrical test data, by described second
With reference to electrical test data as second electrical test data.
6. the failure analysis method of integrated circuit according to claim 1, which is characterized in that
Described pair is to carry out negative electrical charge to the integrated circuit the step of carrying out charge trap Processing for removing to the integrated circuit
Trap Processing for removing；
If the difference of first electrical test data and second electrical test data is more than preset difference value, determine
If it includes: first electrical test data less than preset that the integrated circuit, which is the step of failure as caused by charge trap,
Normal specimens electric leakage threshold value, and second electrical test data is greater than or equal to the preset normal specimens electric leakage threshold
Value, then determine that the integrated circuit is the failure as caused by negative electrical charge trap.
7. the failure analysis method of integrated circuit according to claim 1, which is characterized in that described to the integrated circuit
Carry out charge trap Processing for removing the step of include:
Using UV illumination technique or again alloying technology to the integrated circuit carry out charge trap Processing for removing.
8. the failure analysis method of integrated circuit according to claim 1-7, which is characterized in that described pair integrated
Circuit carried out before the step of electrical testing, comprising:
Obtain other fail messages in addition to charge trap failure of the integrated circuit；
If judging, other described fail messages are not to identify the integrated circuit the reason of causing the ic failure
For the integrated circuit for needing to judge whether there is charge trap.
9. according to the failure analysis method of the described in any item integrated circuits of claim 4-5, which is characterized in that described to obtain the
After the step of one electrical test data, if first electrical test data is greater than preset normal specimens electrical leakage threshold value,
Just execute described the step of charge trap Processing for removing is carried out to the integrated circuit.
10. a kind of failure analysis system of integrated circuit characterized by comprising
First device of testing electrical properties for carrying out electrical testing to integrated circuit, and obtains the first electrical test data；
Charge trap eliminates equipment, for carrying out charge trap Processing for removing to the integrated circuit；
Second device of testing electrical properties for carrying out electrical testing to the integrated circuit, and obtains the second electrical test data；
Failure analysis apparatus is connect with the first device of testing electrical properties, the second device of testing electrical properties respectively, for according to described first
Whether the difference of electrical test data and second electrical test data is more than preset difference value, whether judges the integrated circuit
It is the failure as caused by charge trap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711050345.8A CN109725246B (en) | 2017-10-31 | 2017-10-31 | Failure analysis method and system for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711050345.8A CN109725246B (en) | 2017-10-31 | 2017-10-31 | Failure analysis method and system for integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109725246A true CN109725246A (en) | 2019-05-07 |
| CN109725246B CN109725246B (en) | 2021-05-11 |
Family
ID=66293597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711050345.8A Active CN109725246B (en) | 2017-10-31 | 2017-10-31 | Failure analysis method and system for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109725246B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110208684A (en) * | 2019-07-08 | 2019-09-06 | 西安太乙电子有限公司 | A kind of lifetime estimation method in CMOS type integrated circuit life extension test |
| CN113514753A (en) * | 2021-04-15 | 2021-10-19 | 筏渡(上海)科技有限公司 | Method and device for determining relation of wafer failure functions |
| CN114089171A (en) * | 2022-01-19 | 2022-02-25 | 北京软件产品质量检测检验中心 | Chip measurement and control system and test method for integrated circuit electrical failure analysis |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155333A (en) * | 1994-06-22 | 1997-07-23 | 伊美申公司 | System and method for conditioning radiation detector |
| CN101988909A (en) * | 2009-08-06 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Failure analysis method of low k dielectric material |
| CN102054872A (en) * | 2009-11-06 | 2011-05-11 | 英飞凌科技股份有限公司 | Semiconductor devices and methods |
| CN102237288A (en) * | 2010-04-28 | 2011-11-09 | 中国科学院微电子研究所 | Method for detecting surface passivation effect of GaN field effect transistor |
| CN102346152A (en) * | 2010-07-30 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Sample failure analysis method |
| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
| CN103021897A (en) * | 2012-11-12 | 2013-04-03 | 上海华力微电子有限公司 | Method for detecting semiconductor device electrical property failure |
| CN103680620A (en) * | 2012-08-28 | 2014-03-26 | 飞思卡尔半导体公司 | Non-volatile memory (NVM) that uses soft programming |
| CN103926519A (en) * | 2014-04-26 | 2014-07-16 | 中国科学院新疆理化技术研究所 | Quantitative test method used for cross NPN transistor ionizing radiation damage |
| CN104485875A (en) * | 2014-12-17 | 2015-04-01 | 常州天合光能有限公司 | Failure analysis method for judging failed photovoltaic component and photovoltaic component structure using failure analysis method |
| CN105334084A (en) * | 2014-06-30 | 2016-02-17 | 无锡华润上华半导体有限公司 | Preparation method of integrated circuit chip failure analysis sample |
-
2017
- 2017-10-31 CN CN201711050345.8A patent/CN109725246B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155333A (en) * | 1994-06-22 | 1997-07-23 | 伊美申公司 | System and method for conditioning radiation detector |
| CN101988909A (en) * | 2009-08-06 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Failure analysis method of low k dielectric material |
| CN102054872A (en) * | 2009-11-06 | 2011-05-11 | 英飞凌科技股份有限公司 | Semiconductor devices and methods |
| CN102237288A (en) * | 2010-04-28 | 2011-11-09 | 中国科学院微电子研究所 | Method for detecting surface passivation effect of GaN field effect transistor |
| CN102346152A (en) * | 2010-07-30 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Sample failure analysis method |
| CN102376600A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Evaluation method for failure of contact hole |
| CN103680620A (en) * | 2012-08-28 | 2014-03-26 | 飞思卡尔半导体公司 | Non-volatile memory (NVM) that uses soft programming |
| US8760923B2 (en) * | 2012-08-28 | 2014-06-24 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) that uses soft programming |
| CN103021897A (en) * | 2012-11-12 | 2013-04-03 | 上海华力微电子有限公司 | Method for detecting semiconductor device electrical property failure |
| CN103926519A (en) * | 2014-04-26 | 2014-07-16 | 中国科学院新疆理化技术研究所 | Quantitative test method used for cross NPN transistor ionizing radiation damage |
| CN105334084A (en) * | 2014-06-30 | 2016-02-17 | 无锡华润上华半导体有限公司 | Preparation method of integrated circuit chip failure analysis sample |
| CN104485875A (en) * | 2014-12-17 | 2015-04-01 | 常州天合光能有限公司 | Failure analysis method for judging failed photovoltaic component and photovoltaic component structure using failure analysis method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110208684A (en) * | 2019-07-08 | 2019-09-06 | 西安太乙电子有限公司 | A kind of lifetime estimation method in CMOS type integrated circuit life extension test |
| CN110208684B (en) * | 2019-07-08 | 2021-04-06 | 西安太乙电子有限公司 | Life evaluation method for CMOS integrated circuit life prolonging test |
| CN113514753A (en) * | 2021-04-15 | 2021-10-19 | 筏渡(上海)科技有限公司 | Method and device for determining relation of wafer failure functions |
| CN114089171A (en) * | 2022-01-19 | 2022-02-25 | 北京软件产品质量检测检验中心 | Chip measurement and control system and test method for integrated circuit electrical failure analysis |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109725246B (en) | 2021-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109725246A (en) | The failure analysis method and system of integrated circuit | |
| US6847038B2 (en) | Scanning electron microscope | |
| US6646262B1 (en) | Scanning electron microscope | |
| US4706018A (en) | Noncontact dynamic tester for integrated circuits | |
| CN110824316A (en) | XLPE cable trap parameter measuring method based on polarization-depolarization current test | |
| CN112640026A (en) | Time-dependent defect inspection apparatus | |
| US5045783A (en) | Method for testing a printed circuit board with a particle probe | |
| JPH11154695A (en) | Method for locating faulty point on integrated circuit and apparatus for locating faulty point | |
| EP0404970A1 (en) | Method and system for contactless testing of electronic activity in an integrated circuit chip-to-test after passivation thereof | |
| CN116057392A (en) | Delay time measurement method and system | |
| JPH1187451A (en) | Method and apparatus for inspection of semiconductor device | |
| CN114068694B (en) | Method and system for testing charge collection resistance of germanium-silicon heterojunction bipolar transistor | |
| US6870379B1 (en) | Indirect stimulation of an integrated circuit die | |
| TW202405468A (en) | Methods and apparatuses for identifying defective electrical connections, and methods for generating a trained computational model | |
| Wong et al. | Charging identification and compensation in the scanning electron microscope | |
| TW202407364A (en) | Methods and apparatuses for testing electrical connections of a substrate | |
| CN117501401A (en) | Charged particle beam device | |
| CN115996506A (en) | Method for controlling surface potential of insulating material under high vacuum | |
| WO2023217355A1 (en) | Methods and apparatuses for identifying defective electrical connections of a substrate | |
| KR100912847B1 (en) | Reliability of vias and diagnosis by e-beam probing | |
| Sayil et al. | Electron Beam and Photoemission Probing | |
| JPH02302679A (en) | Continuity inspecting apparatus | |
| EP2091068A1 (en) | A sensor, a monitoring system and a method for detecting a substance in a gas sample | |
| Khiam et al. | Electrochemical wet etching in KOH: H20 solution and secondary/ion image passive voltage contrast as a complementary technique in failure analysis | |
| JP2018041920A (en) | Blanking aperture array device, charged particle beam drawing apparatus, and electrode test method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |