CN105321832A - 封装基板的加工方法 - Google Patents

封装基板的加工方法 Download PDF

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Publication number
CN105321832A
CN105321832A CN201510423873.8A CN201510423873A CN105321832A CN 105321832 A CN105321832 A CN 105321832A CN 201510423873 A CN201510423873 A CN 201510423873A CN 105321832 A CN105321832 A CN 105321832A
Authority
CN
China
Prior art keywords
packaging
base plate
laser light
along
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510423873.8A
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English (en)
Chinese (zh)
Inventor
高桥邦光
藤原诚司
出岛信和
竹内雅哉
相川力
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
Original Assignee
Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Corp filed Critical Disco Corp
Publication of CN105321832A publication Critical patent/CN105321832A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Laser Beam Processing (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
CN201510423873.8A 2014-07-29 2015-07-17 封装基板的加工方法 Pending CN105321832A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-153646 2014-07-29
JP2014153646A JP2016030277A (ja) 2014-07-29 2014-07-29 パッケージ基板の加工方法

Publications (1)

Publication Number Publication Date
CN105321832A true CN105321832A (zh) 2016-02-10

Family

ID=55248959

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510423873.8A Pending CN105321832A (zh) 2014-07-29 2015-07-17 封装基板的加工方法

Country Status (4)

Country Link
JP (1) JP2016030277A (ko)
KR (1) KR20160014524A (ko)
CN (1) CN105321832A (ko)
TW (1) TW201606938A (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108281347A (zh) * 2017-01-06 2018-07-13 株式会社迪思科 树脂封装基板的加工方法
CN111432978A (zh) * 2017-09-13 2020-07-17 诚解电子私人有限公司 用于以聚合物树脂铸模化合物为基底的基板的切割方法及其系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004526335A (ja) * 2001-05-24 2004-08-26 クリック・アンド・ソッファ・インベストメンツ・インコーポレイテッド ウェハーの二段式レーザー切断
JP2010021507A (ja) * 2007-10-11 2010-01-28 Hitachi Chem Co Ltd 光半導体素子搭載用基板及びその製造方法、並びに光半導体装置及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420245B1 (en) * 1999-06-08 2002-07-16 Kulicke & Soffa Investments, Inc. Method for singulating semiconductor wafers
JP5166929B2 (ja) 2008-03-18 2013-03-21 株式会社ディスコ 光デバイスの製造方法
DE102011054891B4 (de) * 2011-10-28 2017-10-19 Osram Opto Semiconductors Gmbh Verfahren zum Durchtrennen eines Halbleiterbauelementverbunds

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004526335A (ja) * 2001-05-24 2004-08-26 クリック・アンド・ソッファ・インベストメンツ・インコーポレイテッド ウェハーの二段式レーザー切断
JP2010021507A (ja) * 2007-10-11 2010-01-28 Hitachi Chem Co Ltd 光半導体素子搭載用基板及びその製造方法、並びに光半導体装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108281347A (zh) * 2017-01-06 2018-07-13 株式会社迪思科 树脂封装基板的加工方法
CN111432978A (zh) * 2017-09-13 2020-07-17 诚解电子私人有限公司 用于以聚合物树脂铸模化合物为基底的基板的切割方法及其系统

Also Published As

Publication number Publication date
TW201606938A (zh) 2016-02-16
KR20160014524A (ko) 2016-02-11
JP2016030277A (ja) 2016-03-07

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