CN105304117B - Memory self-refreshing device and method - Google Patents
Memory self-refreshing device and method Download PDFInfo
- Publication number
- CN105304117B CN105304117B CN201410243626.5A CN201410243626A CN105304117B CN 105304117 B CN105304117 B CN 105304117B CN 201410243626 A CN201410243626 A CN 201410243626A CN 105304117 B CN105304117 B CN 105304117B
- Authority
- CN
- China
- Prior art keywords
- wordline
- signal
- refreshing
- self
- line drive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Dram (AREA)
Abstract
It includes choosing module and self-refreshing controller with the first wordline of the first main word-line signal enable that the present invention provides a kind of memory self-refreshing device and methods for including the memory array of memory cell.It includes that the first selection element of the first wordline is chosen according to the first word line drive signal that first wordline, which chooses module, with the second selection element for choosing the second wordline according to the second word line drive signal.Self-refreshing controller generates the first word line drive signal, the second word line drive signal and the first main word-line signal, to select the first wordline or the corresponding memory cell of the second wordline to carry out self-refreshing action.When switching to the second wordline from the first wordline, the first main word-line signal is maintained identity logic level by self-refreshing controller.The present invention can reach the consumption electric current for reducing self-refreshing to promote the power saving purpose of dynamic ram.
Description
Technical field
The present invention relates to depositing for a kind of memory self-refreshing device and method, especially a kind of effective reduction standby current
Reservoir self-refreshing device and method.
Background technology
In dynamic ram, storage element includes a transistor and a capacitor to store a position
Data.Due to there are the paths of various leakage currents, storage element around capacitor must be regular when standby mode
Refresh the data of its storage, the reason of this is also to be referred to as " dynamic " why.
However, the consumption electric current of standby mode is a critically important technical indicator of dynamic ram, and it is current
The mode for reducing the consumption electric current in standby mode focuses on that reduction is static and consumes electric current mostly, also had significantly at
Effect.And the self-refreshing action of dynamic ram is also implemented in standby mode, it is therefore necessary to be brushed for self is reduced
New consumption electric current is to promote the power saving purpose of dynamic ram.
Invention content
In view of this, the technical problem to be solved by the present invention is to：It is proposed a kind of memory self-refreshing device and method, it should
Device can reduce the consumption electric current of self-refreshing to promote the purpose of the power saving of dynamic ram.
The first technical solution of the present invention is a kind of memory self-refreshing device, is suitable for a memory array, wherein
Above-mentioned memory array includes multiple memory cells, including one first wordline choose module, a bit line sense amplifier and
One self-refreshing controller.
Above-mentioned first wordline chooses module, the enable according to one first main word-line signal, including one first selection element
And one second selection element.Above-mentioned first selection element chooses one first wordline according to one first word line drive signal.On
The second selection element is stated according to one second word line drive signal, and chooses one second wordline.Above-mentioned bit line sense amplifier according to
One refresh signal, the above-mentioned memory cell corresponding to above-mentioned first wordline and above-mentioned second wordline to selection carry out one
Self-refreshing acts.Above-mentioned self-refreshing controller generate above-mentioned first word line drive signal, above-mentioned second word line drive signal,
Above-mentioned first main word-line signal and above-mentioned refresh signal, to select one of above-mentioned first wordline and above-mentioned second wordline
Corresponding above-mentioned memory cell carries out above-mentioned self-refreshing action, wherein when switching to above-mentioned second from above-mentioned first wordline
When wordline, the above-mentioned first main word-line signal is maintained identity logic level by above-mentioned self-refreshing controller.
An embodiment according to the present invention, the memory self-refreshing device further include that one second wordline chooses module.On
It states the second wordline and chooses module, receive one second main word-line signal, including a third selection element and one the 4th selection member
Part.Above-mentioned third selection element chooses a third wordline according to above-mentioned first word line drive signal.Above-mentioned 4th selection element
According to above-mentioned second word line drive signal, and choose one the 4th wordline.When switching to above-mentioned third wordline from above-mentioned second wordline
When, above-mentioned self-refreshing controller stops generating above-mentioned first main word-line signal and above-mentioned second word line drive signal, according to
Sequence generates above-mentioned second main word-line signal and above-mentioned first word line drive signal, above-mentioned when being switched to from above-mentioned third wordline
When four wordline, the above-mentioned second main word-line signal is maintained identity logic level by above-mentioned self-refreshing controller.
An embodiment according to the present invention, wherein above-mentioned first selection element is one first phase inverter, above-mentioned first reverse phase
Device includes one first supply power end, a first input end and one first output end, above-mentioned first word line drive signal via
Above-mentioned first supply power end is provided to above-mentioned first phase inverter, and above-mentioned first main word-line signal is via above-mentioned first input end
Selecting above-mentioned first phase inverter so that above-mentioned first phase inverter selects above-mentioned first wordline via above-mentioned first output end, wherein
Above-mentioned second selection element is one second phase inverter, and above-mentioned second phase inverter includes one second supply power end, one second input
End and a second output terminal, above-mentioned second word line drive signal supply power end via above-mentioned second and are provided to above-mentioned second instead
Phase device, above-mentioned first main word-line signal select above-mentioned second phase inverter via above-mentioned first input end so that above-mentioned second is anti-
Phase device selects above-mentioned second wordline via above-mentioned second output terminal.
An embodiment according to the present invention, which further includes a command decoder.Mentioned order
Decoder exports an enable signal, wherein above-mentioned self-refreshing controller generates above-mentioned first wordline according to above-mentioned enable signal
Drive signal, above-mentioned second word line drive signal, above-mentioned first main word-line signal and above-mentioned refresh signal.
An embodiment according to the present invention, wherein above-mentioned self-refreshing controller further include a self-refreshing control module,
One self-refreshing timing module and a self-refreshing counting module.Above-mentioned self-refreshing control module is according to above-mentioned enable signal
And a self-refreshing signal, above-mentioned first word line drive signal and above-mentioned second word line drive signal are sequentially generated, and defeated
Go out a status signal and above-mentioned refresh signal.Above-mentioned self-refreshing timing module receives above-mentioned status signal and controls above-mentioned the
The time interval of one word line drive signal and above-mentioned second word line drive signal, and send out a time signal.Self above-mentioned brush
New count module generates above-mentioned self-refreshing signal and above-mentioned first main word-line signal according to above-mentioned time signal, and
And before above-mentioned second word line drive signal switches to above-mentioned first word line drive signal, by the above-mentioned first main word-line signal
Maintain identical logic level.
The second technical solution of the present invention is to propose a kind of memory self-refreshing method, is suitable for a memory array,
Wherein above-mentioned memory array includes multiple memory cells, including：According to one first main word-line signal enable, one first word
Line selection modulus block, and sequentially choose one first wordline and one second wordline；And to above-mentioned first wordline of selection and on
It states the above-mentioned memory cell corresponding to the second wordline and carries out a self-refreshing action, wherein being switched to when from above-mentioned first wordline
When above-mentioned second wordline, above-mentioned first main word-line signal maintains identity logic level.
An embodiment according to the present invention, the memory self-refreshing method further include：According to one second main wordline letter
Number one second wordline of enable chooses module, and sequentially chooses a third wordline and one the 4th wordline；And to the above-mentioned of selection
Above-mentioned memory cell corresponding to third wordline and above-mentioned 4th wordline carries out a self-refreshing action, wherein when from above-mentioned
When third wordline switches to above-mentioned four wordline, above-mentioned second main word-line signal maintains identity logic level.
An embodiment according to the present invention, wherein above-mentioned first selection element is one first phase inverter, above-mentioned first reverse phase
Device includes one first supply power end, a first input end and one first output end, above-mentioned first word line drive signal via
Above-mentioned first supply power end is provided to above-mentioned first phase inverter, and above-mentioned first main word-line signal is via above-mentioned first input end
Selecting above-mentioned first phase inverter so that above-mentioned first phase inverter selects above-mentioned first wordline via above-mentioned first output end, wherein
Above-mentioned second selection element is one second phase inverter, and above-mentioned second phase inverter includes one second supply power end, one second input
End and a second output terminal, above-mentioned second word line drive signal supply power end via above-mentioned second and are provided to above-mentioned second instead
Phase device, above-mentioned first main word-line signal select above-mentioned second phase inverter via above-mentioned first input end so that above-mentioned second is anti-
Phase device selects above-mentioned second wordline via above-mentioned second output terminal.
An embodiment according to the present invention, the memory self-refreshing method further include：It is exported according to a command decoder
One of enable signal and generate above-mentioned first character drive signal, above-mentioned second word line drive signal, above-mentioned first main wordline
Signal and above-mentioned refresh signal.
An embodiment according to the present invention, the memory self-refreshing method further include：According to above-mentioned enable signal and
One self-refreshing signal sequentially generates above-mentioned first word line drive signal and above-mentioned second word line drive signal, and exports one
Status signal and above-mentioned refresh signal；According to above-mentioned status signal, above-mentioned first character drive signal and above-mentioned the are controlled
The time interval of two word line drive signals and send out a time signal；And above-mentioned self-refreshing is generated according to above-mentioned time signal
Signal and above-mentioned first main word-line signal, wherein switching to above-mentioned first wordline driving in above-mentioned second word line drive signal
Before signal, the above-mentioned first main word-line signal is maintained into identical logic level.
Technical solution in summary, the present invention can reduce the consumption electric current of self-refreshing, be deposited to further promote dynamic
The power saving purpose of access to memory.
Description of the drawings
Fig. 1 is the block diagram for showing the memory self-refreshing device described in an embodiment according to the present invention；
Fig. 2 is to show that the first wordline described in an embodiment according to the present invention chooses module and the second wordline selection mould
The circuit diagram of block；
Fig. 3 is the block diagram for showing the self-refreshing controller described in an embodiment according to the present invention；And
Fig. 4 is the flow chart for showing the memory self-refreshing method described in an embodiment according to the present invention.
Symbol description in figure：
100 memory self-refreshing devices；
110 memory arrays；
120,210 first wordline choose module；
121 first selection elements；
122 second selection elements；
130,220 second wordline choose module；
131 third selection elements；
132 the 4th selection elements；
140 sensing amplifiers；
150 address decoders；
160 self-refreshing controllers；
111~116 memory cells；
211 first phase inverters；
212 second phase inverters；
213 first N-type semiconductors；
214 second N-type semiconductors；
221 third phase inverters；
222 the 4th phase inverters；
223 third N-type semiconductors；
224 the 4th N-type semiconductors；
310 self-refreshing controllers；
311 self-refreshing control modules；
312 self-refreshing timing modules；
313 self-refreshing counting modules；
320 command decoders；
WL<0>First wordline；
WL<1>Second wordline；
WL<2>Third wordline；
WL<3>4th wordline；
SMWL1First main word-line signal；
SMWL2Second main word-line signal；
SWLDV1First word line drive signal；
SWLDV2Second word line drive signal；
SADRSRefreshing address signal；
SRRefresh signal；
SEEnable signal；
SSFSelf-refreshing signal；
SSTStatus signal；
STTime signal；
SWLRST1First bit line reset signal；
SWLRST2Second bit line reset signal.
Specific implementation mode
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, hereafter especially exemplified by a preferred embodiment, and
Coordinate institute's accompanying drawings, to be described below in detail：
Described below is preferred embodiment according to the present invention.It must be noted that the present invention provides permitted
Mostly applicable concept of the invention, disclosed specific embodiment herein, be only for explanation reach with of the invention specific
Mode, without can be used to limit to the scope of the present invention.
Fig. 1 is the block diagram for showing the memory self-refreshing device described in an embodiment according to the present invention.Such as Fig. 1 institutes
Show, memory self-refreshing device 100 includes memory array 110, the first wordline chooses module 120, the second wordline chooses mould
Block 130, sensing amplifier 140, address decoder 150 and self-refreshing controller 160.Memory array 110 includes multiple
Memory cell 111~116 is respectively coupled to the first wordline WL<0>, the second wordline WL<1>, third wordline WL<2>And the
Four wordline WL<3>.
It includes the first selection element 121 and the second selection element 122, the choosing of the second wordline that first wordline, which chooses module 120,
Modulus block 130 includes third selection element 131 and the 4th selection element 132.Self-refreshing controller 160 utilizes refresh signal
SREnable address decoder 150, the refreshing address signal S that address decoder 150 is sent out according to self-refreshing controller 160ADRS
And utilize the first main word-line signal SMWL1The first wordline of enable chooses module 120, recycles the first word line drive signal SWLDV1
Start the first selection element 121 and chooses the first wordline WL<0>, or utilize the second word line drive signal SWLDV2Start the second choosing
It takes element 122 and chooses the second wordline WL<1>.
Address decoder 150 more utilizes the second main word-line signal SMWL2The second wordline of enable chooses module 130, recycles
First word line drive signal SWLDV1Start third selection element 131 and chooses third wordline WL<2>, or utilize the drive of the second wordline
Dynamic signal SWLDV2Start the 4th selection element 132 and selects the 4th wordline WL<3>.
The refresh signal S that bit line sense amplifier 140 is sent out according to self-refreshing controller 160R, for selected
First wordline WL<0>, the second wordline WL<1>, third wordline WL<2>And the 4th wordline WL<3>One on corresponding deposit
Storage unit 111~116 carries out self-refreshing action.
The refreshing address signal S that address decoder 150 is sent out according to self-refreshing controller 160ADRS, is generated respectively
One main word-line signal SMWL1, the second word line drive signal SWLDV2, the first word line drive signal SWLDV1And the second main wordline
Signal SMWL2The sequence for carrying out 111~116 self-refreshing of control memory unit utilizes refresh signal SRControl bit line sensing amplification
Device 140 executes self-refreshing action.In addition, as the first wordline WL<0>Switch to the second wordline WL<1>When, self-refreshing control
Device 160 controls address decoder 150 by the first main word-line signal SMWL1Identity logic level is maintained, reduces by the first main wordline
Signal SMWL1Power attenuation caused by charge and discharge, and then quiescent current when reduction standby mode.
Similarly, as third wordline WL<2>Switch to the 4th wordline WL<3>When, self-refreshing controller 160 controls address solution
Code device 150 is by the second main word-line signal SMWL2Maintain identity logic level.According to another embodiment of the present invention, when from second
Wordline WL<1>Switch to third wordline WL<2>When, self-refreshing controller 160, which controls address decoder 150, to be stopped generating first
Main word-line signal SMWL1And the second word line drive signal SWLDV2, and sequentially generate the second main word-line signal SMWL2And the
One word line drive signal SWLDV1。
According to another embodiment of the present invention, self-refreshing controller 160 can directly generate the first main word-line signal
SMWL1, the second word line drive signal SWLDV2, the first word line drive signal SWLDV1And the second main word-line signal SMWL2To control
The sequence of 111~116 self-refreshing of memory cell, without utilizing address decoder 150 to refreshing address signal SADRSInto
Row decoding.
Fig. 2 is to show that the first wordline described in an embodiment according to the present invention chooses module and the second wordline selection mould
The circuit diagram of block.As shown in Fig. 2, the first wordline selection module 210 is identical as the first wordline of Fig. 1 selection module 120, the second word
Line selection modulus block 220 is identical as the second wordline of Fig. 1 selection module 130.
An embodiment according to the present invention, the first selection element 121, the second selection element 122, the third of Fig. 1 choose member
Part 131 and the 4th selection element 132 are phase inverter, and therefore, the first selection element 121 of Fig. 1 is corresponded to the first phase inverter
211, Fig. 1 the second selection element 122 is corresponded to the second phase inverter 212, and the correspondence of third selection element 131 of Fig. 1 is anti-to third
4th selection element 132 of phase device 221, Fig. 1 is corresponded to the 4th phase inverter 222.
As shown in Fig. 2, the supply power end of the first phase inverter 211 and third phase inverter 221 is both coupled to the first wordline
Drive signal SWLDV1, the input terminal of the first phase inverter 211 and third phase inverter 221 is then coupled to the first main word-line signal
SMWL1.When the first phase inverter 211 selects the first wordline WL<0>When, the first word line drive signal SWLDV1For high logic level
One main word-line signal SMWL1For low logic level, so that the first wordline WL<0>As high logic level, that is, represent selection
The memory cell 111 of Fig. 1 carries out self-refreshing action.
When due to executing self-refreshing, the sequence of selected wordline can be controlled by self-refreshing controller 160, according to
One embodiment of the invention, according to the first wordline WL<0>, the second wordline WL<1>, third wordline WL<2>And the 4th wordline WL<
3>Sequence, sequentially be directed to corresponding memory cell 111~116 carry out self-refreshing action.
When from the first wordline WL<0>Switch to the second wordline WL<1>When, the first main word-line signal SMWL1Remain identical
Low logic level, the first word line drive signal SWLDV1Low logic level is converted by high logic level, and the driving of the second wordline is believed
Number SWLDV2High logic level is converted by low logic level.As the first word line drive signal SWLDV1For low logic level when, first
Wordline WL<0>Via the first bit line reset signal SWLRST1First N-type semiconductor 213 of control is changed into low logic level, and the
Two wordline WL<1>Also because of the second word line drive signal S of high logic levelWLDV2And it is selected.
In addition, the second wordline WL ought not be chosen<1>, third wordline WL<2>And the 4th wordline WL<3>When, the second N-type half
Conductor 214, third N-type semiconductor 223 and the 4th N-type semiconductor 224 are respectively by the second wordline WL<1>, third wordline WL<2>
And the 4th wordline WL<3>It is pulled down to low logic level.
As the second wordline WL<1>Switch to third wordline WL<2>When, the self-refreshing controller 160 of Fig. 1 controls address solution
Code device 150 is by the first main word-line signal SMWL1Be converted to high logic level, the second main word-line signal SMWL2Be converted to low logic
Level and the first word line drive signal S for high logic levelWLDV1To choose third wordline WL<2>, and utilize with second
Bit line reset signal SWLRST2Second N-type semiconductor 214 of control is counter to choose the second wordline WL<1>.
Likewise, working as third wordline WL<2>Switch to the 4th wordline WL<3>When, the second main word-line signal SMWL2It maintains
Identical low logic level, the first word line drive signal SWLDV1Low logic level is converted by high logic level, and the second wordline
Drive signal SWLDV2High logic level is converted by low logic level, and is utilized with the first bit line reset signal SWLRST1Control
Third N-type semiconductor 223 by third wordline WL<2>It is pulled down to low logic level.
As the 4th wordline WL<3>When not being selected, also with the second bit line reset signal SWLRST24th N of control
Type semiconductor 224 is by the 4th wordline WL<3>It is pulled down to low logic level.An embodiment according to the present invention, the resetting of the first bit line
Signal SWLRST1For the first word line drive signal SWLDV1Inversion signal, the second bit line reset signal SWLRST2It is driven for the second wordline
Signal SWLDV2Inversion signal.
Fig. 3 is the block diagram for showing the self-refreshing controller described in an embodiment according to the present invention.As shown in figure 3,
Self-refreshing controller 310 is identical as the self-refreshing controller 160 of Fig. 1, and self-refreshing controller 310 receives order solution
The enable signal S that code device 320 is exportedEAnd carry out self-refreshing action.An embodiment according to the present invention, user is to order
Decoder 320 is programmed, to set the relevant parameter and flow of self-refreshing action.
As shown in figure 3, self-refreshing controller 310 includes self-refreshing control module 311, self-refreshing counting module
313 and self-refreshing timing module 312.Self-refreshing control module 311 is believed according to enable caused by command decoder 320
Number SEAnd self-refreshing signal S caused by self-refreshing counting module 313SF, sequentially generate the first word line drive signal
SWLDV1, the second word line drive signal SWLDV2, refresh signal SRAnd status signal SST.As shown in Figure 1, refresh signal SRWith so that
Energy bit line sense amplifier 140 is directed to the first word line drive signal SWLDV1, the second word line drive signal SWLDV2With the first main word
Line signal SMWL1, the second main word-line signal SMWL2Combination selected by memory cell 111~116 to carry out self-refreshing dynamic
Make, and controls and generate the first word line drive signal SWLDV1And the second word line drive signal SWLDV2Time.It is according to the present invention
One embodiment, the first word line drive signal SWLDV1And the second word line drive signal SWLDV2High logic is held in 30nsec
Level is changed into low logic level immediately later.
Self-refreshing timing module 312 receives the status signal S that self refreshing control module 311 is sent outSTAfter start to count
Several time spans and send out time signal ST, to control the first word line drive signal SWLDV1And second word line drive signal
SWLDV2Time interval.An embodiment according to the present invention, the first word line drive signal SWLDV1And second word line drive signal
SWLDV2Between time interval be 7.8 μ sec.
Self-refreshing counting module 313 is sequentially choosing each wordline in memory array.Self-refreshing counts
313 receiving time signal S of moduleTAnd generate self refresh signal SSF, first is generated to control self-refreshing control module 311
Word line drive signal SWLDV1And the second word line drive signal SWLDV2Time interval.
Meanwhile self-refreshing counting module 313 more exports according to the storage address of its self-refreshing recorded
One main word-line signal SMWL1And the second main word-line signal SMWL2, and in the first word line drive signal SWLDV1And second word
Line drive signal SWLDV2Before completing a cycle, by the first main word-line signal SMWL1And the second main word-line signal SMWL2Dimension
It is held in identical logic level.The self-refreshing action of an embodiment according to the present invention, memory array must be in 64msec
Middle completion.
An embodiment according to the present invention, when with the first word line drive signal SWLDV1And second word line drive signal
SWLDV2When, in the second word line drive signal SWLDV2Switch to the first word line drive signal SWLDV1Before, the first main word-line signal
SMWL1And the second main word-line signal SMWL2It is maintained at identity logic level, as the second word line drive signal SWLDV2Switch to
One word line drive signal SWLDV1When, empty the first main word-line signal SMWL1And the second main word-line signal SMWL2One,
And generate the first main word-line signal SMWL1And the second main word-line signal SMWL2Another one to choose next wordline.
According to another embodiment of the present invention, self-refreshing controller 310 exports refreshing address signal SADRSIt is solved to address
Code device (in Fig. 3 not show), address decoder is by refreshing address signal SADRSIt is converted into the first word line drive signal SWLDV1,
Two word line drive signal SWLDV2, the first main word-line signal SMWL1And the second main word-line signal SMWL2, and when in first
Word line drive signal SWLDV1And the second word line drive signal SWLDV2Before completing a cycle, self-refreshing controller 310 controls
Address decoder is by the first main word-line signal SMWL1And the second main word-line signal SMWL2It is maintained at identical logic level.
Fig. 4 is the flow chart for showing the memory self-refreshing method described in an embodiment according to the present invention.Following figure 4
Flow chart by the block diagram for the Fig. 1 that arranges in pairs or groups, to be described in detail.
First, according to the first main word-line signal SMWL1The first wordline of enable chooses module 120, and sequentially chooses the first word
Line WL<0>And the second wordline WL<1>(step S41).
To the first wordline WL of selection<0>And the second wordline WL<1>Corresponding memory cell 111~113 carries out
Self-refreshing acts, wherein when switching to the second wordline from the first wordline, the first main word-line signal maintains identity logic electricity
Flat (step S42).
According to the second main word-line signal SMWL2The second wordline of enable chooses module 130, and sequentially chooses third wordline WL<
2>And the 4th wordline WL<3>(step S43).
To the third wordline WL of selection<2>And the 4th wordline WL<3>Corresponding memory cell 114~116 carries out
Self-refreshing acts, wherein when from third wordline WL<2>Switch to the 4th wordline WL<3>When, the second main word-line signal SMWL2
Maintain identity logic level (step S44).
Using the memory self-refreshing device and memory self-refreshing method of the present invention, it can reduce by the first main word
Line signal SMWL1And the second main word-line signal SMWL2Switching caused by power attenuation, and then reduce dynamic memory in
Quiescent current when standby mode, and achieve the purpose that power saving.
The feature of many embodiments described above, makes the technical staff in the technical field clearly understood that this explanation
The form of book.The technical staff in the technical field it will be appreciated that its using based on disclosure of the present invention with design or
It changes other manufacturing process and structure and completes the purpose for being identical to above-described embodiment or reach to be identical to the excellent of above-described embodiment
Point.The technical staff in the technical field is not also it will be appreciated that the equivalent constructions for not departing from the spirit and scope of the present invention can be
It is detached from the arbitrary change of work in the spirit and scope of the present invention, substitutes and retouches.
Claims (10)
1. a kind of memory self-refreshing device, which is suitable for a memory array, and feature exists
In the memory array includes multiple memory cells, and the memory self-refreshing device includes：
One first wordline chooses module, the enable according to one first main word-line signal, and first wordline chooses module and includes：
One first selection element chooses one first wordline according to one first word line drive signal；And
One second selection element chooses one second wordline according to one second word line drive signal；
One bit line sense amplifier, according to a refresh signal, first wordline and second wordline institute to selection are right
Each memory cell answered carries out a self-refreshing action；And
One self-refreshing controller generates first word line drive signal, second word line drive signal, first master
Word-line signal and the refresh signal are wanted, to select corresponding to the one of first wordline and second wordline
The memory cell carries out the self-refreshing action, wherein when switching to second wordline from first wordline,
Described first main word-line signal is maintained identity logic level by the self-refreshing controller.
2. memory self-refreshing device according to claim 1, which is characterized in that the memory self-refreshing device
Further include：
One second wordline chooses module, and for receiving one second main word-line signal, second wordline chooses module and includes：
One third selection element chooses a third wordline according to first word line drive signal；And
One the 4th selection element chooses one the 4th wordline according to second word line drive signal；
Wherein when switching to the third wordline from second wordline, the self-refreshing controller stops generating described the
One main word-line signal and second word line drive signal sequentially generate the described second main word-line signal and described
One word line drive signal, when switching to four wordline from the third wordline, the self-refreshing controller will be described
Second main word-line signal maintains identity logic level.
3. memory self-refreshing device according to claim 1, which is characterized in that first selection element is one the
One phase inverter, first phase inverter includes one first supply power end, a first input end and one first output end, described
First word line drive signal supplies power end via described first and is provided to first phase inverter, the first main wordline letter
Number select first phase inverter via the first input end so that first phase inverter is selected via first output end
First wordline is selected, wherein second selection element is one second phase inverter, second phase inverter includes one second confession
Power end, one second input terminal and a second output terminal are answered, second word line drive signal is via the second supply electricity
Source is provided to second phase inverter, and the first main word-line signal is anti-via first input end selection described second
Phase device so that second phase inverter selects second wordline via the second output terminal.
4. memory self-refreshing device according to claim 3, which is characterized in that the memory self-refreshing device
Further include：
One command decoder exports an enable signal, wherein the self-refreshing controller generates institute according to the enable signal
State the first word line drive signal, second word line drive signal, the first main word-line signal and the refresh signal.
5. memory self-refreshing device according to claim 4, which is characterized in that the memory self-refreshing control
Device further includes：
One self-refreshing control module sequentially generates first word according to the enable signal and a self-refreshing signal
Line drive signal and second word line drive signal, and export a status signal and the refresh signal；
One self-refreshing timing module receives the status signal and controls first word line drive signal and described second
The time interval of word line drive signal and send out a time signal；And
One self-refreshing counting module generates the self-refreshing signal and described first according to the time signal mainly
Word-line signal, and before second word line drive signal switches to first word line drive signal, by described first
Main word-line signal maintains identical logic level.
6. a kind of memory self-refreshing method, the memory self-refreshing method is suitable for a memory array, feature
It is, wherein the memory array includes multiple memory cells, the memory self-refreshing method includes：
Module is chosen according to one first main word-line signal enable, one first wordline, and sequentially one first selection element is utilized to choose
One first wordline and one second selection element of utilization choose one second wordline；And
Each memory cell corresponding to first wordline and second wordline to selection carries out self brush
New element, wherein when switching to second wordline from first wordline, the first main word-line signal remains identical
Logic level.
7. memory self-refreshing method according to claim 6, which is characterized in that the memory self-refreshing method
Further include：
Module is chosen according to one second main word-line signal enable, one second wordline, and sequentially chooses a third wordline and one the
Four wordline；And
The memory cell corresponding to the third wordline and the 4th wordline to selection carries out a self-refreshing
Action, wherein when switching to four wordline from the third wordline, the second main word-line signal remains identical and patrols
Collect level.
8. memory self-refreshing method according to claim 6, which is characterized in that first selection element is one the
One phase inverter, first phase inverter include one first supply power end, a first input end and one first output end, and one the
One word line drive signal supplies power end via described first and is provided to first phase inverter, the first main word-line signal
First phase inverter is selected via the first input end so that first phase inverter is selected via first output end
First wordline, wherein second selection element is one second phase inverter, second phase inverter includes one second supply
Power end, one second input terminal and a second output terminal, one second word line drive signal supply power end via described second
It is provided to second phase inverter, the first main word-line signal selects second reverse phase via the first input end
Device so that second phase inverter selects second wordline via the second output terminal.
9. memory self-refreshing method according to claim 8, which is characterized in that the memory self-refreshing method
Further include：
First word line drive signal is generated according to an enable signal of command decoder output, second wordline is driven
Dynamic signal, the first main word-line signal and the refresh signal.
10. memory self-refreshing method according to claim 9, which is characterized in that the memory self-refreshing side
Method further includes：
According to the enable signal and a self-refreshing signal, first word line drive signal and described are sequentially generated
Two word line drive signals, and export a status signal and the refresh signal；
According to the status signal, between the time for controlling first word line drive signal and second word line drive signal
Every and send out a time signal；And the self-refreshing signal and the first main word are generated according to the time signal
Line signal is led wherein before second word line drive signal switches to first word line drive signal by described first
Word-line signal is wanted to maintain identical logic level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410243626.5A CN105304117B (en) | 2014-06-03 | 2014-06-03 | Memory self-refreshing device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410243626.5A CN105304117B (en) | 2014-06-03 | 2014-06-03 | Memory self-refreshing device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105304117A CN105304117A (en) | 2016-02-03 |
| CN105304117B true CN105304117B (en) | 2018-09-07 |
Family
ID=55201279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410243626.5A Active CN105304117B (en) | 2014-06-03 | 2014-06-03 | Memory self-refreshing device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105304117B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6592126B2 (en) * | 2018-02-09 | 2019-10-16 | 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． | Bit line power supply device |
| JP6894459B2 (en) * | 2019-02-25 | 2021-06-30 | 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． | Pseudo-static random access memory and how it works |
| CN111261213B (en) * | 2020-04-30 | 2020-09-01 | 深圳市芯天下技术有限公司 | Erasing method of NOR Flash |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1403923A (en) * | 2002-10-21 | 2003-03-19 | 威盛电子股份有限公司 | DRAM data maintaining method and relative device |
| CN101000798A (en) * | 2007-01-12 | 2007-07-18 | 威盛电子股份有限公司 | Memory updating method |
| CN102855925A (en) * | 2011-06-29 | 2013-01-02 | 爱思开海力士有限公司 | Self-refresh control circuit and memory comprising self-refresh control circuit |
| US8659928B1 (en) * | 2011-12-13 | 2014-02-25 | Michael C. Stephens, Jr. | Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements |
-
2014
- 2014-06-03 CN CN201410243626.5A patent/CN105304117B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1403923A (en) * | 2002-10-21 | 2003-03-19 | 威盛电子股份有限公司 | DRAM data maintaining method and relative device |
| CN101000798A (en) * | 2007-01-12 | 2007-07-18 | 威盛电子股份有限公司 | Memory updating method |
| CN102855925A (en) * | 2011-06-29 | 2013-01-02 | 爱思开海力士有限公司 | Self-refresh control circuit and memory comprising self-refresh control circuit |
| US8659928B1 (en) * | 2011-12-13 | 2014-02-25 | Michael C. Stephens, Jr. | Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105304117A (en) | 2016-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109727624A (en) | Memory device and its method for refreshing with twin cell mode | |
| CN106157867B (en) | Shift register cell, driving method, gate driving circuit and display device | |
| CN103000223B (en) | Pseudo static random access memory operation method and related memory device | |
| CN105304117B (en) | Memory self-refreshing device and method | |
| CN108231105A (en) | Word line driver | |
| CN105654984A (en) | Static random access memory and method thereof | |
| JPH09180448A (en) | Boosted voltage generator of semiconductor memory device | |
| JPH10144072A (en) | Semiconductor having refresh device | |
| KR20100029484A (en) | Circuit and method for wordline driving | |
| US9299414B1 (en) | Devices for self-refreshing memories, and methods thereof | |
| CN108255751A (en) | For the memory device for controlling refresh operation and include its self-refresh controller | |
| CN105304128B (en) | Value data is stored in the method and memory of storage unit | |
| US8107310B2 (en) | Semiconductor memory device and method for operating the same | |
| CN1989569A (en) | Dram with half and full density operation | |
| CN104464676A (en) | Clock generation circuit of liquid crystal display device and operation method thereof | |
| CN102855930B (en) | The programmable control method and device of memory, storage array | |
| CN102467972A (en) | Dynamic shift register unit and dynamic shift register | |
| US10818335B2 (en) | Memory storage apparatus and operating method with multiple modes for refresh operation | |
| CN105304119A (en) | Refresh circuit | |
| CN103000221A (en) | Semiconductor apparatus | |
| CN101399538B (en) | FPGA chip | |
| KR100798772B1 (en) | Semiconductor memory device | |
| JP4984759B2 (en) | Semiconductor memory device | |
| JP2007220233A (en) | Semiconductor memory device and semiconductor device and electronic device | |
| TWI826524B (en) | Memory performing refresh operation and operation method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |