CN105304117A - Memory self-refresh apparatus and method - Google Patents

Memory self-refresh apparatus and method Download PDF

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CN105304117A
CN105304117A CN 201410243626 CN201410243626A CN105304117A CN 105304117 A CN105304117 A CN 105304117A CN 201410243626 CN201410243626 CN 201410243626 CN 201410243626 A CN201410243626 A CN 201410243626A CN 105304117 A CN105304117 A CN 105304117A
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word line
signal
self
refresh
memory
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CN 201410243626
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Chinese (zh)
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林哲民
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华邦电子股份有限公司
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Abstract

The present invention provides a memory self-refresh apparatus and method, and is used for a memory array comprising memory cells. The apparatus comprises a first word line selecting module enabled by a first main word line signal and a self-refresh controller. The first word line selecting module comprises a first selecting element that selects a first word line according to a first word line drive signal and a second selecting element that selects a second word line according to a second word line drive signal. The self-refresh controller generates the first word line drive signal, the second word line drive signal, and the first main word line signal, for selecting a memory cell corresponding to the first word line or the second word line to perform a self-refresh operation. When the first word line is switched to the second word line, the self-refresh controller maintains a same logic level of the first main word line signal. According to the present invention, a purpose of saving electricity of a dynamic access memory can be achieved by reducing current consumption of self-refresh can be achieved.

Description

存储器自我刷新装置及方法 Self refresh memory device and method

技术领域 FIELD

[0001] 本发明涉及一种存储器自我刷新装置及方法,尤其是一种有效降低待机电流的存储器自我刷新装置及方法。 [0001] The present invention relates to apparatus and method for self-refreshing a memory, in particular a device and method for effectively reducing the standby current of the memory self-refresh.

背景技术 Background technique

[0002] 在动态存取存储器中,储存单元包括一个晶体管以及一个电容器来储存一个位的资料。 [0002] In the dynamic random access memory storage cell comprises one transistor and one capacitor to store a data bit. 由于电容器的周围存在各种漏电电流的路径,因此储存单元必须于待机模式时定期刷新其储存的资料,这也是为何称之为“动态”的原因。 Due to various leakage current path around the capacitor, and therefore must be periodically refreshed a storage unit storing data in the standby mode, which is the reason why the call "dynamic".

[0003] 然而,待机模式的消耗电流为动态存取存储器的一项很重要的技术指标,而目前降低待机模式中的消耗电流的方式大多着重于降低静态消耗电流,也已经有了显著的成效。 [0003] However, current consumption standby mode is a very important technical indicators dynamic access memory, and most of the current to reduce current consumption in standby mode in a manner that focuses on reducing the static current consumption, but also have significant results . 而动态存取存储器的自我刷新动作也执行于待机模式中,因此有必要针对降低自我刷新的消耗电流以增进动态存取存储器的省电目的。 The dynamic access memory self-refresh operation is also performed in the standby mode, it is necessary to reduce consumption current for the self-refresh power saving purposes to improve dynamic access memory.

发明内容 SUMMARY

[0004] 有鉴于此,本发明要解决的技术问题是:提出一种存储器自我刷新装置及方法,该装置能够降低自我刷新的消耗电流以增进动态存取存储器的省电的目的。 [0004] Accordingly, the present invention is to solve the technical problem: propose an apparatus and method of self-refresh memory, which means the current consumption can be reduced to improve the self-refresh to save power dynamic access memory.

[0005] 本发明的第一技术方案是,一种存储器自我刷新装置,适用于一存储器阵列,其中上述存储器阵列包括多个存储器单元,包括一第一字线选取模块、一位线感测放大器以及一自我刷新控制器。 [0005] The first aspect of the present invention is a self-refreshing memory means for use in a memory array, wherein the memory array comprises a plurality of memory cells, comprising a first word line selection module, a line sense amplifier and a self-refresh controller.

[0006] 上述第一字线选取模块,根据一第一主要字线信号而致能,包括一第一选取元件以及一第二选取兀件。 [0006] The first word line selection module, can be caused, comprising selecting a first member and a second member according to a first selected Wu main word line signal. 上述第一选取兀件根据一第一字线驱动信号,而选取一第一字线。 Selecting the first driving signal Wu member according to a first word line and a selected first word line. 上述第二选取元件根据一第二字线驱动信号,而选取一第二字线。 Said second select signal according to a driving element of the second word line and a second selection word line. 上述位线感测放大器根据一刷新信号,对选取的上述第一字线以及上述第二字线所对应的上述存储器单元,进行一自我刷新动作。 Said bit line sense amplifier in accordance with a refresh signal for selecting the memory cells in the first word and the second word line corresponding to the line, performing a self-refresh operation. 上述自我刷新控制器产生上述第一字线驱动信号、上述第二字线驱动信号、上述第一主要字线信号以及上述刷新信号,用以选择上述第一字线以及上述第二字线之一所对应的上述存储器单元进行上述自我刷新动作,其中当自上述第一字线切换至上述第二字线时,上述自我刷新控制器将上述第一主要字线信号维持相同逻辑电平。 The above-described self-refresh controller generating the first word line drive signal, said second word line drive signal, the first main word line signal and the refresh signal for selecting the first word line and one of said second word line said memory means corresponding to the above-described self-refresh operation, wherein when switching from said first word line to the second word line above the self-refresh controller of the first main word line signal to maintain the same logic level.

[0007] 根据本发明的一实施例,该存储器自我刷新装置还包括一第二字线选取模块。 [0007] According to an embodiment of the present invention, the memory self-refresh means further comprises a second word line selection module. 上述第二字线选取模块,接收一第二主要字线信号,包括一第三选取元件以及一第四选取元件。 The second word line selection module, receives a second main word line signal, comprising selecting a third element and a fourth element selected. 上述第三选取元件根据上述第一字线驱动信号,而选取一第三字线。 The third element drive signal according to the selected first word line, and a third word line selected. 上述第四选取元件根据上述第二字线驱动信号,而选取一第四字线。 The fourth element driving signal according to the selected second word line, and a fourth word line selected. 当自上述第二字线切换至上述第三字线时,上述自我刷新控制器停止产生上述第一主要字线信号以及上述第二字线驱动信号,依序产生上述第二主要字线信号以及上述第一字线驱动信号,当自上述第三字线切换至上述第四字线时,上述自我刷新控制器将上述第二主要字线信号维持相同逻辑电平。 When the word line is switched from said second to said third word line, the above-described self-refresh controller stops generating said first main word line signal and said second word line drive signal, sequentially generating the second main word line signal and said first word line drive signal when switching from said third word line to the fourth word line, the above-described self-refresh controller and the second main word line signal to maintain the same logic level.

[0008] 根据本发明的一实施例,其中上述第一选取元件为一第一反相器,上述第一反相器包括一第一供应电源端、一第一输入端以及一第一输出端,上述第一字线驱动信号经由上述第一供应电源端提供至上述第一反相器,上述第一主要字线信号经由上述第一输入端选择上述第一反相器,使得上述第一反相器经由上述第一输出端选择上述第一字线,其中上述第二选取元件为一第二反相器,上述第二反相器包括一第二供应电源端、一第二输入端以及一第二输出端,上述第二字线驱动信号经由上述第二供应电源端提供至上述第二反相器,上述第一主要字线信号经由上述第一输入端选择上述第二反相器,使得上述第二反相器经由上述第二输出端选择上述第二字线。 [0008] According to one embodiment of the present invention, wherein the first selected element is a first inverter, said first inverter includes a first power supply terminal, a first input terminal and a first output terminal the first word line drive signal supplied via the first power supply terminal of said first inverter to said first main word line signal for selecting the first inverter via the first input terminal, such that the first anti phase selects the first word line via the first output terminal, wherein said second selected element is a second inverter, said second inverter includes a second power supply terminal, a second input terminal, and a a second output terminal, said second word line drive signal supplied via the second power supply terminal of the second inverter to the first main word line signal selecting said second inverter via said first input terminal, such that said second inverter selects the second word line via the second output terminal.

[0009] 根据本发明的一实施例,该存储器自我刷新装置还包括一命令解码器。 [0009] According to an embodiment of the present invention, the memory means further comprises a self-refresh command decoder. 上述命令解码器,输出一致能信号,其中上述自我刷新控制器根据上述致能信号产生上述第一字线驱动信号、上述第二字线驱动信号、上述第一主要字线信号以及上述刷新信号。 The above command decoder, an output enable signal, wherein said self-refresh controller aforementioned enable signal is generated based on the first word line drive signal, said second word line drive signal, the first main word line signal and the refresh signal.

[0010] 根据本发明的一实施例,其中上述自我刷新控制器还包括一自我刷新控制模块、一自我刷新计时模块以及一自我刷新计数模块。 [0010] According to one embodiment of the present invention, wherein said self-refresh controller further comprises a self-refresh control module, a self-refresh and a self-refresh timing module counting module. 上述自我刷新控制模块根据上述致能信号以及一自我刷新信号,依序产生上述第一字线驱动信号以及上述第二字线驱动信号,并输出一状态信号以及上述刷新信号。 The above-described self-refresh control module based on the enable signal and a self-refresh signal, sequentially generating the first word line drive signal and the second word line driving signal, and outputs a state signal and the refresh signal. 上述自我刷新计时模块接收上述状态信号并控制上述第一字线驱动信号以及上述第二字线驱动信号的时间间隔,而发出一时间信号。 The above-described self-refresh timer module receives the status signal and controls the time of the first word line drive signal and the second word line driving signal interval, while issuing a time signal. 上述自我刷新计数模块根据上述时间信号,而产生上述自我刷新信号以及上述第一主要字线信号,并且在上述第二字线驱动信号切换至上述第一字线驱动信号之前,将上述第一主要字线信号维持相同的逻辑电平。 The above-described self-refresh signal from the time counting module, but before the above-mentioned self-refresh signal and the first main word line signal, and the drive signal is switched to the first word line drive signal generated in the second word line, said first main word line signal maintaining the same logic level.

[0011] 本发明的第二技术方案是,提出一种存储器自我刷新方法,适用于一存储器阵列,其中上述存储器阵列包括多个存储器单元,包括:根据一第一主要字线信号致能一第一字线选取模块,并依序选取一第一字线以及一第二字线;以及对选取的上述第一字线以及上述第二字线所对应的上述存储器单元进行一自我刷新动作,其中当自上述第一字线切换至上述第二字线时,上述第一主要字线信号维持相同逻辑电平。 [0011] The second aspect of the present invention is to provide a memory self-refresh method, applicable to a memory array, wherein the memory array comprises a plurality of memory cells, comprising: a first actuator can according to a first main word line signal a word line selection module, and sequentially selecting a first word line and a second word line; and the memory cells in the selected first word line and the second word line corresponding to a self-refresh operation is performed, wherein when switching from said first word line to the second word line, said first main word line signal to maintain the same logic level.

[0012] 根据本发明的一实施例,该存储器自我刷新方法还包括:根据一第二主要字线信号致能一第二字线选取模块,并依序选取一第三字线以及一第四字线;以及对选取的上述第三字线以及上述第四字线所对应的上述存储器单元进行一自我刷新动作,其中当自上述第三字线切换至上述第四字线时,上述第二主要字线信号维持相同逻辑电平。 [0012] According to an embodiment of the present invention, the memory self-refresh method further comprising: according to a second main word line signal enabling a second word line selection module, and sequentially selecting a third and a fourth word line a word line; and when the memory cells of the selected word line and the third line corresponding to the fourth word is a self-refresh operation, wherein when switching from said third word line to the fourth word line, the second The main word line signal to maintain the same logic level.

[0013] 根据本发明的一实施例,其中上述第一选取元件为一第一反相器,上述第一反相器包括一第一供应电源端、一第一输入端以及一第一输出端,上述第一字线驱动信号经由上述第一供应电源端提供至上述第一反相器,上述第一主要字线信号经由上述第一输入端选择上述第一反相器,使得上述第一反相器经由上述第一输出端选择上述第一字线,其中上述第二选取元件为一第二反相器,上述第二反相器包括一第二供应电源端、一第二输入端以及一第二输出端,上述第二字线驱动信号经由上述第二供应电源端提供至上述第二反相器,上述第一主要字线信号经由上述第一输入端选择上述第二反相器,使得上述第二反相器经由上述第二输出端选择上述第二字线。 [0013] According to one embodiment of the present invention, wherein the first selected element is a first inverter, said first inverter includes a first power supply terminal, a first input terminal and a first output terminal the first word line drive signal supplied via the first power supply terminal of said first inverter to said first main word line signal for selecting the first inverter via the first input terminal, such that the first anti phase selects the first word line via the first output terminal, wherein said second selected element is a second inverter, said second inverter includes a second power supply terminal, a second input terminal, and a a second output terminal, said second word line drive signal supplied via the second power supply terminal of the second inverter to the first main word line signal selecting said second inverter via said first input terminal, such that said second inverter selects the second word line via the second output terminal.

[0014] 根据本发明的一实施例,该存储器自我刷新方法更包括:根据一命令解码器输出之一致能信号而产生上述第一字元驱动信号、上述第二字线驱动信号、上述第一主要字线信号以及上述刷新信号。 [0014] According to one embodiment of the present invention, the memory self-refresh method further comprising: generating a drive signal of said first character, the second word line drive signal, the first enable signal in accordance with a command output of the decoder The main word line signal and the refresh signal.

[0015] 根据本发明的一实施例,该存储器自我刷新方法更包括:根据上述致能信号以及一自我刷新信号,依序产生上述第一字线驱动信号以及上述第二字线驱动信号,并输出一状态信号以及上述刷新信号;根据上述状态信号,控制上述第一字元驱动信号以及上述第二字线驱动信号的时间间隔而发出一时间信号;以及根据上述时间信号产生上述自我刷新信号以及上述第一主要字线信号,其中在上述第二字线驱动信号切换至上述第一字线驱动信号之前,将上述第一主要字线信号维持相同的逻辑电平。 [0015] According to an embodiment of the present invention, the memory self-refresh method further comprising: based on the enable signal and a self-refresh signal, sequentially generating the first word line drive signal and the second word line drive signal, and a status output signal and the refresh signal; to emit a time signal of the state signal, controls the first driving signal and the time character of the second word line drive signal interval based; and self-refresh signal generated based on the above-described time signal and before the first main word line signal, wherein said first signal is switched to a word line drive signal in the second word line drive, said first main word line signal to maintain the same logic level.

[0016] 综上所述技术方案,本发明能降低自我刷新的消耗电流,从而进一步增进动态存取存储器的省电目的。 [0016] In summary aspect, the present invention can reduce the current consumption of the self-refresh, thereby further enhancing the dynamic access memory saving purposes.

附图说明 BRIEF DESCRIPTION

[0017] 图1是显示根据本发明的一实施例所述的存储器自我刷新装置的方块图; [0017] FIG. 1 is a block diagram showing a memory according to an embodiment of the present invention, the self-refresh means;

[0018] 图2是显示根据本发明的一实施例所述的第一字线选取模块以及第二字线选取模块的电路图; [0018] FIG. 2 is a circuit diagram of a selection word line selection module and a second module according to a first word line to an embodiment of the present invention;

[0019] 图3是显示根据本发明的一实施例所述的自我刷新控制器的方块图;以及 [0019] FIG. 3 is a block diagram showing a self-refresh controller according to an embodiment of the present invention; and

[0020] 图4是显示根据本发明的一实施例所述的存储器自我刷新方法的流程图。 [0020] FIG. 4 is a flowchart of the memory self-refresh method according to an embodiment of the present invention.

[0021 ] 图中符号说明: [0021] REFERENCE SIGNS:

[0022] 100 存储器自我刷新装置; [0022] Self-refresh memory means 100;

[0023] 110 存储器阵列; [0023] The memory array 110;

[0024] 120,210 第一字线选取模块; [0024] The first word line selection module 120, 210;

[0025] 121 第一选取元件; [0025] a first selection element 121;

[0026] 122 第二选取元件; [0026] The second selection element 122;

[0027] 130、220 第二字线选取模块; [0027] The second word line selection module 130, 220;

[0028] 131 第三选取元件; [0028] The third selection element 131;

[0029] 132 第四选取元件; [0029] The fourth selection element 132;

[0030] 140 感测放大器; [0030] The sense amplifier 140;

[0031] 150 地址解码器; [0031] The address decoder 150;

[0032] 160 自我刷新控制器; [0032] The self-refresh controller 160;

[0033] 111〜116存储器单元; [0033] 111~116 memory cells;

[0034] 211 第一反相器; [0034] 211 first inverter;

[0035] 212 第二反相器; [0035] The second inverter 212;

[0036] 213 第一N型半导体; [0036] The first N-type semiconductor 213;

[0037] 214 第二N型半导体; [0037] The second N-type semiconductor 214;

[0038] 221 第三反相器; [0038] The third inverter 221;

[0039] 222 第四反相器; [0039] The fourth inverter 222;

[0040] 223 第三N型半导体; [0040] 223 third N-type semiconductor;

[0041] 224 第四N型半导体; [0041] 224 of the fourth N-type semiconductor;

[0042] 310 自我刷新控制器; [0042] The self-refresh controller 310;

[0043] 311 自我刷新控制模块; [0043] The self-refresh control module 311;

[0044] 312 自我刷新计时模块; [0044] Self-refresh timing module 312;

[0045] 313 自我刷新计数模块; [0045] The self-refresh counter module 313;

[0046] 320 命令解码器; [0046] The command decoder 320;

[0047] WL<0> 第一字线; [0047] WL <0> first word line;

[0048] WL<1> 第二字线; [0048] WL <1> a second word line;

[0049] WL<2> 第三字线; [0049] WL <2> third word line;

[0050] WL<3> 第四字线; [0050] WL <3> fourth word line;

[0051] SmL1 第一主要字线信号; [0051] SmL1 first main word line signal;

[0052] S_ 第二主要字线信号; [0052] S_ second main word line signal;

[0053] SWLDV1 第一字线驱动信号; [0053] SWLDV1 first word line drive signal;

[0054] SWLDV2 第二字线驱动信号; [0054] SWLDV2 second word line drive signal;

[0055] SADRS 刷新地址信号; [0055] SADRS refresh address signal;

[0056] SR 刷新信号; [0056] SR refresh signal;

[0057] SE 致能信号; [0057] SE enable signal;

[0058] SSF 自我刷新信号; [0058] SSF self refresh signal;

[0059] SST 状态信号; [0059] SST state signal;

[0060] ST 时间信号; [0060] ST time signal;

[0061] SWLRST1 第一位线重置信号; [0061] SWLRST1 first bit line reset signal;

[0062] SWLRST2 第二位线重置信号。 [0062] SWLRST2 second bit line reset signal.

具体实施方式 detailed description

[0063] 为使本发明的上述目的、特征和优点能更明显易懂,下文特例举一较佳实施例,并配合所附图式,来做详细说明如下: [0063] For the above-described objects, features and advantages of the present invention can be more fully understood by referring to a preferred exemplified embodiments and with the accompanying drawings, do the following detailed description:

[0064] 以下将介绍是根据本发明所述的较佳实施例。 [0064] The following describes a preferred embodiment according to the present invention. 必须要说明的是,本发明提供了许多可应用的发明概念,在此所揭露的特定实施例,仅是用于说明达成与运用本发明的特定方式,而不可用以局限本发明的范围。 Must be noted that the present invention provides many applicable inventive concepts, in a particular embodiment disclosed herein, is illustrative only and application to achieve a specific embodiment of the present invention and are not used to limit the scope of the present invention.

[0065] 图1是显示根据本发明的一实施例所述的存储器自我刷新装置的方块图。 [0065] FIG. 1 is a block diagram showing a memory device according to the self refresh to an embodiment of the present invention. 如图1所示,存储器自我刷新装置100包括存储器阵列110、第一字线选取模块120、第二字线选取模块130、感测放大器140、地址解码器150以及自我刷新控制器160。 1, the self-refresh memory device 100 includes a memory array 110, a first word line selection module 120, the second word line selection module 130, sense amplifier 140, the address decoder 150 and the self-refresh controller 160. 存储器阵列110包括多个存储器单元111〜116,分别耦接至第一字线WL〈0>、第二字线WL〈1>、第三字线WL〈2>以及第四字线WL〈3>。 The memory array 110 includes a plurality of memory cells 111~116, respectively coupled to the first word line WL <0>, the second word line WL <1>, the third word line WL <2> and a fourth word line WL <3 >.

[0066] 第一字线选取模块120包括第一选取元件121以及第二选取元件122,第二字线选取模块130包括第三选取元件131以及第四选取元件132。 [0066] The first word line selection module 120 comprises a first selection element 121 and a second selection element 122, the second word line selection module 130 comprises a third selection element 131 and a fourth selection element 132. 自我刷新控制器160利用刷新信号&致能地址解码器150,地址解码器150根据自我刷新控制器160所发出的刷新地址信号SADRS而利用第一主要字线信号S_u致能第一字线选取模块120,再利用第一字线驱动信号Swli)V1启动第一选取兀件121而选取第一字线WL〈0>,或是利用第二字线驱动信号Swlim启动第二选取元件122而选取第二字线WL〈1>。 Self-refresh controller 160 can be activated using the refresh address signal & decoder 150, the address decoder 150 according to the self-refresh controller SADRS refresh address signal 160 emitted by the first main word line signal S_u enable first word line selection module 120, re-use the first word line drive signal Swli) V1 start selecting a first member 121 and Wu selecting the first word line WL <0>, or a second selection element Swlim start using a second word line drive signal selection section 122 the word line WL <1>.

[0067] 地址解码器150更利用第二主要字线信号S_2致能第二字线选取模块130,再利用第一字线驱动信号SMV1启动第三选取元件131而选取第三字线WL〈2>,或是利用第二字线驱动信号SMV2启动第四选取元件132而选择第四字线WL〈3>。 [0067] Address decoder 150 and more by the second main word line signal S_2 enabling the second word line selection module 130, and then a third word line WL selected by the first word line drive signal selecting element 131 to start the third SMV1 <2 >, or by the second word line drive signal SMV2 start fourth selection element 132 selects the fourth word line WL <3>.

[0068] 位线感测放大器140根据自我刷新控制器160所发出的刷新信号SR,针对所选取的第一字线WL〈0>、第二字线WL〈1>、第三字线WL〈2>以及第四字线WL〈3>之一者上所对应的存储器单元111〜116,进行自我刷新动作。 [0068] Bit line sense amplifier 140 in accordance with self-refresh refresh signal SR emitted from the controller 160, for the first selected word line WL <0>, the second word line WL <1>, the third word line WL < 2> and a fourth word line WL <3> corresponding to one of those memory cells 111~116, self refresh operation.

[0069] 地址解码器150根据自我刷新控制器160所发出的刷新地址信号SADRS,分别产生第一主要字线信号SMWU、第二字线驱动信号sMV2、第一字线驱动信号SMV1以及第二主要字线信号s_2来控制存储器单元111〜116自我刷新的顺序,利用刷新信号SR控制位线感测放大器140执行自我刷新动作。 [0069] Address decoder 150 refresh address signal according to self-refresh controller 160 SADRS emitted, generating a first main word line signal SMWU, the second word line drive signal sMV2, the first word line drive signal and a second main SMV1 s_2 word line signal to control the order of self-refreshing memory cells 111~116, using the refresh control signal SR bit line sense amplifier 140 performs a self-refresh operation. 此外,当第一字线WL〈0>切换至第二字线WL〈1>时,自我刷新控制器160控制地址解码器150将第一主要字线信号SMWU维持相同逻辑电平,减少第一主要字线信号SMWU充电与放电所造成的功率损耗,进而降低待机模式时的静态电流。 Further, when the first word line WL <0> is switched to the second word line WL <1>, self-refresh controller 160 controls the address decoders 150 of the first main word line signal SMWU maintain the same logic level, the first reduction the main word line signal SMWU charge and discharge caused by power loss, thereby reducing the static current for the standby mode.

[0070] 同理,当第三字线WL〈2>切换至第四字线WL〈3>时,自我刷新控制器160控制地址解码器150将第二主要字线信号Sm2维持相同逻辑电平。 [0070] Similarly, when the third word line WL <2> is switched to the fourth word line WL <3>, 160 controls the self-refresh address decoder 150 of the second main word line signal Sm2 controller maintains the same logic level . 根据本发明的另一实施例,当自第二字线WL〈1>切换至第三字线WL〈2>时,自我刷新控制器160控制地址解码器150停止产生第一主要字线信号S_u以及第二字线驱动信号SMV2,并依序产生第二主要字线信号Sm2以及第一字线驱动信号sWU)V1。 According to another embodiment of the present invention, since when the second word line WL <1> is switched to the third word line WL <2>, the self-refresh controller 160 controls the address decoder 150 stops generating the first main word line signal S_u and a second word line drive signal SMV2, and sequentially generating a second main word line signal Sm2 and the first word line drive signal sWU) V1.

[0071] 根据本发明的另一实施例,自我刷新控制器160可直接产生第一主要字线信号S_u、弟一子线驱动ί目号SWLDV2、弟一子线驱动彳目号SWLDV1以及弟一王要子线彳目号S_L2来te制存储器单元111〜116自我刷新的顺序,而不需利用地址解码器150对刷新地址信号SADRS进行解码。 [0071] According to another embodiment of the present invention, the self-refresh controller 160 may generate the first main word line signal S_u directly, a sub-line driving ί brother mesh number SWLDV2, a sub-line driving brother left foot SWLDV1 mesh number and a brother to Wang strand mesh sequence number S_L2 left foot to te memory cells 111~116 made self-refresh, without using the address decoder decodes the refresh address signal SADRS 150 pair.

[0072] 图2是显示根据本发明的一实施例所述的第一字线选取模块以及第二字线选取模块的电路图。 [0072] FIG. 2 is a circuit diagram of a selection word line selection module and a second module according to a first word line to an embodiment of the present invention. 如图2所示,第一字线选取模块210与图1的第一字线选取模块120相同,第二字线选取模块220与图1的第二字线选取模块130相同。 2, the first word line of the first word line selection module 210 of FIG. 1 and the same selection module 120, the second word line selection module 220 and the second word line in FIG. 1 130 selected the same module.

[0073] 根据本发明的一实施例,图1的第一选取元件121、第二选取元件122、第三选取元件131以及第四选取元件132为反相器,因此,图1的第一选取元件121对应至第一反相器211,图1的第二选取元件122对应至第二反相器212,图1的第三选取元件131对应至第三反相器221,图1的第四选取元件132对应至第四反相器222。 [0073] According to one embodiment, the first selection element 121 of FIG. 1, a second selection element 122, a third selection element 131 and a fourth selection element 132 is an inverter embodiment of the present invention, therefore, the first selection in FIG. 1 element 121 corresponds to the first selected element of the second inverter 211, 122 of FIG. 1 corresponds to a second inverter 212, a third selection element 131 of FIG. 1 corresponds to a third inverter 221, a fourth FIG. 1 select the element 132 corresponds to the fourth inverter 222.

[0074] 如图2所示,第一反相器211以及第三反相器221的供应电源端均耦接至第一字线驱动信号SMV1,第一反相器211以及第三反相器221的输入端则耦接至第一主要字线信号Smwli。 [0074] As shown, power supply terminal of the first inverter and a third inverter 211 2 221 are coupled to the first word line drive signal SMV1, a first inverter and a third inverter 211 an input terminal 221 is coupled to the first main word line signal Smwli. 当第一反相器211选择第一字线WL〈0>时,第一字线驱动信号Swli)V1为高逻辑电平而第一主要字线信号S_u为低逻辑电平,因而使得第一字线WL〈0>成为高逻辑电平,即代表选择图1的存储器单元111进行自我刷新动作。 When the first inverter 211 selects the first word line WL <0>, the first word line drive signal Swli) V1 is a high logic level of the first main word line signal S_u low logic level, so that the first the word lines WL <0> to the high logic level, which represents the selected memory cell 111 of FIG. 1 will be self-refresh operation.

[0075] 由于执行自我刷新时,能够由自我刷新控制器160控制所选择的字线的顺序,根据本发明的一实施例,依据第一字线WL〈0>、第二字线WL〈1>、第三字线WL〈2>以及第四字线WL<3>的顺序,依序针对对应的存储器单元111〜116进行自我刷新动作。 [0075] Since the self-refresh is performed, the sequence controller 160 controls the word line can be selected by the self-refresh, according to an embodiment of the present invention, according to a first word line WL <0>, the second word line WL <1 >, the third word line WL <2> and a fourth word line WL <3> sequence sequentially for the corresponding memory cells 111~116 self-refresh operation.

[0076] 当自第一字线WL〈0>切换至第二字线WL〈1>时,第一主要字线信号SMWU维持相同的低逻辑电平、第一字线驱动信号SMV1由高逻辑电平转换成低逻辑电平,而第二字线驱动信号SMV2由低逻辑电平转换成高逻辑电平。 [0076] When from the first word line WL <0> is switched to the second word line WL <1>, the first main word line signal SMWU maintaining the same low logic level, the first word line drive signal from a high logic SMV1 level is converted into a low logic level and the second word line drive signal SMV2 converted by the low logic level to a high logic level. 当第一字线驱动信号sMV1为低逻辑电平时,第一字线WL〈0>经由第一位线重置信号SMST1控制的第一N型半导体213转变为低逻辑电平,而第二字线WL〈1>也因为高逻辑电平的第二字线驱动信号SMV2而被选取。 When the first N-type semiconductor 213 transitions sMV1 first word line drive signal to a low logic level, the first word line WL <0> through the first bit line reset signal control SMST1 low logic level and the second word line WL <1> because the second word line driving high logic level signal is selected SMV2.

[0077] 此外,当不选取第二字线WL〈1>、第三字线WL〈2>以及第四字线WL〈3>时,第二N型半导体214、第三N型半导体223以及第四N型半导体224分别将第二字线WL〈1>、第三字线WL〈2>以及第四字线WL〈3>下拉至低逻辑电平。 [0077] Further, when the second word line is not selected WL <1>, the third word line WL <2> and a fourth word line WL <3>, the second N-type semiconductor 214, and the third N-type semiconductor 223 a fourth N-type semiconductor 224, respectively, the second word line WL <1>, the third word line WL <2> and a fourth word line WL <3> is pulled down to a low logic level.

[0078] 当第二字线WL〈1>切换至第三字线WL〈2>时,图1的自我刷新控制器160控制地址解码器150将第一主要字线信号Smwu转换为高逻辑电平、第二主要字线信号S_2转换为低逻辑电平以及为高逻辑电平的第一字线驱动信号SMV1来选取第三字线WL〈2>,并且利用以第二位线重置信号SMST2控制的第二N型半导体214来反选取第二字线WL〈1>。 [0078] When the second word line WL <1> is switched to the third word line WL <2>, the self-refresh controller 160 controls the address decoders 150 of the first main word line signal converted Smwu FIG. 1 is a high logic level flat, S_2 second main word line signal is converted to a low logic level and the driving signal for the first word line SMV1 the high logic level to select the third word line WL <2>, and with a second bit line reset signal SMST2 controlled second N-type semiconductor 214 to the second word line select trans WL <1>.

[0079] 同样的,当第三字线WL〈2>切换至第四字线WL〈3>时,第二主要字线信号Sm2维持相同的低逻辑电平、第一字线驱动信号SMV1由高逻辑电平转换成低逻辑电平,而第二字线驱动信号SMV2由低逻辑电平转换成高逻辑电平,并且利用以第一位线重置信号sMST1控制的第三N型半导体223来将第三字线WL〈2>下拉至低逻辑电平。 [0079] Similarly, when the third word line WL <2> is switched to the fourth word line WL <3>, the second main word line signal Sm2 maintaining the same low logic level, the first word line drive signal by a SMV1 converting the high logic level to a low logic level and the second word line drive signal SMV2 converted by the low logic level to a high logic level, and by the third N-type semiconductor to a first reset signal line 223 to control sMST1 to the third word line WL <2> is pulled down to a low logic level.

[0080] 当第四字线WL〈3>不被选取时,同样利用以第二位线重置信号SMST2控制的第四N型半导体224将第四字线WL〈3>下拉至低逻辑电平。 [0080] When a fourth word line WL <3> is not selected, the same with the fourth N-type semiconductor to the second bit line reset signal 224 to control SMST2 fourth word line WL <3> is pulled down to logic low level. 根据本发明的一实施例,第一位线重置信号SMST1为第一字线驱动信号SMV1的反相信号,第二位线重置信号SMST2为第二字线驱动信号Swli)V2的反相信号。 According to an embodiment of the present invention, the first bit line reset signal SMST1 SMV1 driving signal is inverted first word line, a second bit line reset signal SMST2 second word line drive signal SWLI) V2 is inverted signal.

[0081] 图3是显示根据本发明的一实施例所述的自我刷新控制器的方块图。 [0081] FIG. 3 is a block diagram showing a self-refresh controller in the embodiment of the present invention. 如图3所示,自我刷新控制器310与图1的自我刷新控制器160相同,并且自我刷新控制器310接收命令解码器320所输出的致能信号SE而进行自我刷新动作。 3, the self-refresh controller 310 refreshes itself with the same controller 160 in FIG. 1, and the self-refresh enable signal SE controller 310 receives a command decoder 320 outputs the self refresh operation is performed. 根据本发明的一实施例,使用者对命令解码器320进行编程,以设定自我刷新动作的相关参数与流程。 According to an embodiment of the present invention, a user command decoder 320 can be programmed to set the self refresh operation and process parameters.

[0082] 如图3所示,自我刷新控制器310包括自我刷新控制模块311、自我刷新计数模块313以及自我刷新计时模块312。 [0082] 3, the self-refresh controller 310 includes a self-refresh control module 311, self-refresh and self-refresh module 313 counts the timing module 312. 自我刷新控制模块311根据命令解码器320所产生的致能信号SE以及自我刷新计数模块313所产生的自我刷新信号SSF,依序产生第一字线驱动信号sWU)V1、第二字线驱动信号Swli)V2、刷新信号SR以及状态/[目号SST。 Self-refresh control module 311 of the second word line drive signal self-refresh signal SSF, sequentially generating a first word line drive signal sWU) V1, the counting module 313 according to the generated enable signal SE generated by the command decoder 320 and the self-refresh Swli) V2, and the refresh state signal SR / [log number SST. 如图1所不,刷新/[目号sR用以致能位线感测放大器140针对第一字线驱动信号SMV1、第二字线驱动信号SMV2与第一主要字线信号s_u、第二主要字线信号S_2的组合所选取的存储器单元111〜116进行自我刷新动作,并控制产生第一字线驱动信号SMV1以及第二字线驱动信号SMV2的时间。 1 do not refresh / [sR mesh number used to enable the bit line sense amplifier 140 for the first word line drive signal SMV1, SMV2 second word line drive signal to the first main word line signal S_U, the second main word signal line S_2 combination of selected memory cells 111~116 self-refresh operation, and controls the word line drive signal generating SMV1 first and a second time of the word line drive signal SMV2. 根据本发明的一实施例,第一字线驱动信号Swli)V1以及第二字线驱动信号Swli)V2于30nsec中保持于高逻辑电平,之后随即转变为低逻辑电平。 According to an embodiment of the present invention, a first word line drive signal Swli) V1 and a second word line drive signal Swli) V2 in 30nsec maintained at a high logic level, immediately after the transition to a low logic level.

[0083]自我刷新计时模块312接收自我刷新控制模块311所发出的状态信号SST后开始计数一时间长度而发出时间信号ST,用以控制第一字线驱动信号SMV1以及第二字线驱动信号SMV2的时间间隔。 [0083] Self-refresh timing module 312 receives the self-refresh state control module 311 starts counting the signal emitted by a length of time SST emit a time signal ST, for controlling the first word line drive signal SMV1 and the second word line drive signal SMV2 time interval. 根据本发明的一实施例,第一字线驱动信号sMV1以及第二字线驱动信号SMV2之间的时间间隔为7.8 μ sec。 According to an embodiment of the present invention, a first word line drive signal sMV1 and the second word line drive signal SMV2 time interval between 7.8 μ sec.

[0084]自我刷新计数模块313用以依序选取存储器阵列中的每一条字线。 [0084] The self-refresh counter module 313 is used for sequentially selecting each word line in the memory array. 自我刷新计数模块313接收时间信号ST而产生自我刷新信号SSF,用以控制自我刷新控制模块311产生第一字线驱动信号SMV1以及第二字线驱动信号SMV2的时间间隔。 Counting module 313 receives the self refresh timing signal ST generated by self refresh signal SSF, for controlling the self-refresh control module 311 generates a first word line drive signal SMV1 and a word line drive signal a second time interval SMV2.

[0085] 同时,自我刷新计数模块313更依据其所记录的自我刷新的存储器地址而输出第一主要字线信号SMWU以及第二主要字线信号sm2,并于第一字线驱动信号SMV1以及第二字线驱动信号SMV2完成一循环之前,将第一主要字线信号sMWU以及第二主要字线信号sm2维持于相同的逻辑电平。 [0085] Meanwhile, self-refresh counter module 313 is based on the self refresh memory address that is recorded in the output of the first main word line signal and a second SMWU main word line signal SM2, and a drive signal to the first and second SMV1 word line before the word line drive signal SMV2 complete a cycle, the first main word line signal and a second sMWU main word line signal sm2 is maintained at the same logic level. 根据本发明的一实施例,存储器阵列的自我刷新动作必须于64msec中完成。 According to an embodiment of the present invention, the self-refresh operation of the memory array must be completed in 64msec.

[0086] 根据本发明的一实施例,当具有第一字线驱动信号SMV1以及第二字线驱动信号SWLDV2时,在第二字线驱动信号SMV2切换至第一字线驱动信号SWU)V1之前,第一主要字线信号Smwli以及第二主要字线信号S_2维持于相同逻辑电平,当第二字线驱动信号3„„2切换至第一字线驱动信号SMV1时,清空第一主要字线信号S_u以及第二主要字线信号SM12之一者,并产生第一主要字线信号SMWU以及第二主要字线信号sm2的另一者以选取下一条字线。 [0086] According to an embodiment of the present invention, when the previous word line drive signal having a first and a second SMV1 SWLDV2 word line drive signal when the signal is switched to the first SMV2 word line drive signal SWU) V1 of the second word line drive The first main word line signal and a second Smwli S_2 main word line signal is maintained at the same logic level, when the second word line drive signal 3 "" 2 switched to the first word line drive signal SMV1, empty first main word S_u main line signals and a second word line signal by one of SM12, and generates a first main word line signal SMWU and the other second main word line signal sm2 is to select the next word line.

[0087] 根据本发明的另一实施例,自我刷新控制器310输出刷新地址信号SADRS至地址解码器(图3中并未显示),地址解码器将刷新地址信号SADRS转换成第一字线驱动信号SMV1、第二字线驱动信号SMV2、第一主要字线信号SMWU以及第二主要字线信号S_2,并且当于第一字线驱动信号SMV1以及第二字线驱动信号SMV2完成一循环之前,自我刷新控制器310控制地址解码器将第一主要字线信号SMWU以及第二主要字线信号S_2维持于相同的逻辑电平。 [0087] According to another embodiment of the present invention, the self-refresh controller 310 outputs the refresh address signal to the address decoder SADRS (not shown in FIG. 3), the address decoder converts a refresh address signal to a first word line drive SADRS SMV1 signal, SMV2 second word line drive signal, a first main word line signal and a second SMWU S_2 main word line signal, and when the word line drive signal to the first and second SMV1 SMV2 word line drive signal before a cycle is completed, self-refresh controller 310 controls the address decoder of the first main word line signal and a second SMWU S_2 main word line signal is maintained at the same logic level.

[0088] 图4是显示根据本发明的一实施例所述的存储器自我刷新方法的流程图。 [0088] FIG. 4 is a flowchart of the memory self-refresh method according to an embodiment of the present invention. 以下图4的流程图将搭配图1的方块图,以便详细说明。 The following flow chart of FIG. 4 with the block diagram of FIG. 1, to be described in detail.

[0089] 首先,根据第一主要字线信号SMWU致能第一字线选取模块120,并依序选取第一字线WL〈0>以及第二字线WL〈1> (步骤S41)。 [0089] First, the first word line enable selection module 120 according to the first main word line signal SMWU, and sequentially selecting the first word line WL <0> and the second word line WL <1> (step S41).

[0090] 对选取的第一字线WL〈0>以及第二字线WL〈1>所对应的存储器单元111〜113进行自我刷新动作,其中当自第一字线切换至第二字线时,第一主要字线信号维持相同逻辑电平(步骤S42)。 [0090] The first selected word line WL <0> and the second word line WL <1> corresponding memory cells 111~113 self-refresh operation, wherein when the word line is switched from the first to the second word line The first main word line signal to maintain the same logic level (step S42).

[0091] 根据第二主要字线信号S_2致能第二字线选取模块130,并依序选取第三字线WL<2>以及第四字线WL〈3> (步骤S43)。 [0091] enable the second word line selection module 130 according to the second main word line signal S_2, and sequentially select the third word line WL <2> and a fourth word line WL <3> (step S43).

[0092] 对选取的第三字线WL〈2>以及第四字线WL〈3>所对应的存储器单元114〜116进行自我刷新动作,其中当自第三字线WL〈2>切换至第四字线WL〈3>时,第二主要字线信号Smwlz维持相同逻辑电平(步骤S44)。 [0092] The third word line WL selected <2> and a fourth word line WL <. 3> corresponding memory cells 114~116 self-refresh operation, wherein when the word line WL from the third <2> is switched to the quadword line WL <3>, the second main word line signal Smwlz the same logic level is maintained (step S44).

[0093] 使用本发明的存储器自我刷新装置以及存储器自我刷新方法,可减少第一主要字线信号SMWU以及第二主要字线信号SM12的切换所造成的功率损耗,进而降低动态存储器于待机模式时的静态电流,而达到省电的目的。 When the [0093] present invention using the self-refresh a memory device and a memory self refresh method can reduce the first main word line signal SMWU switching power loss and the second main word line signal caused by SM12, thereby reducing the dynamic memory is in standby mode quiescent current, and to achieve the energy saving purpose.

[0094]以上叙述许多实施例的特征,使所属技术领域中的技术人员能够清楚理解本说明书的形态。 [0094] Many features of the embodiments described above, so Those of skill in the art can be clearly understood that the forms of the present specification. 所属技术领域中的技术人员能够理解其可利用本发明揭示内容为基础以设计或更动其他制造工艺及结构而完成相同于上述实施例的目的或达到相同于上述实施例的优点。 Those skilled in the art will appreciate that the present invention disclosure may be utilized to design or based on other manufacturing processes and structural modifiers completed object to the same embodiment or embodiments achieve the same advantages of the above embodiment. 所属技术领域中的技术人员亦能够理解不脱离本发明的精神和范围的等效构造可在不脱离本发明的精神和范围内作任意的更动、替代与润饰。 Those skilled in the art will also be appreciated without departing from the spirit and scope of the present invention may be made of any equivalent constructions that modifications, substitutions and alterations without departing from the scope and spirit of the invention.

Claims (10)

  1. 1.一种存储器自我刷新装置,该存储器自我刷新装置适用于一存储器阵列,其特征在于,所述存储器阵列包括多个存储器单元,所述存储器自我刷新装置包括: 一第一字线选取模块,根据一第一主要字线信号而致能,所述第一字线选取模块包括: 一第一选取元件,根据一第一字线驱动信号选取一第一字线;以及一第二选取元件,根据一第二字线驱动信号选取一第二字线; 一位线感测放大器,根据一刷新信号,对选取的所述第一字线以及所述第二字线所对应的各所述存储器单元,进行一自我刷新动作;以及一自我刷新控制器,产生所述第一字线驱动信号、所述第二字线驱动信号、所述第一主要字线信号以及所述刷新信号,用以选择所述第一字线以及所述第二字线之一者所对应的所述存储器单元进行所述自我刷新动作,其中当自所述第一字线切换至所述 A self-refreshing the memory means, the memory means for use in a self-refresh of the memory array, wherein the memory array comprises a plurality of memory cells, the memory self-refresh means comprising: a first word line selection module, those enabled, the first word line to select a first module comprising a main word line signal: selecting a first member, a first driving signal to select a word line according to a first word line; and a second selection element, selecting a second word line according to a second word line driving signal; a sense amplifier line, in accordance with a refresh signal for selecting the first word line and said second word line corresponding to each of said memory means for performing a self-refresh operation; and a self-refresh controller, generating the first word line drive signal, the second word line drive signal, the first main word line signal and the refresh signal for selecting the first word line and the second word line corresponding to said one of those memory cells of the self-refresh operation, wherein when switching from said first to said word lines 第二字线时,所述自我刷新控制器将所述第一主要字线信号维持相同逻辑电平。 The second word line, the self-refresh controller of the first main word line signal to maintain the same logic level.
  2. 2.根据权利要求1所述的存储器自我刷新装置,其特征在于,所述存储器自我刷新装置还包括: 一第二字线选取模块,用于接收一第二主要字线信号,所述第二字线选取模块包括: 一第三选取元件,根据所述第一字线驱动信号选取一第三字线;以及一第四选取元件,根据所述第二字线驱动信号选取一第四字线; 其中当自所述第二字线切换至所述第三字线时,所述自我刷新控制器停止产生所述第一主要字线信号以及所述第二字线驱动信号,依序产生所述第二主要字线信号以及所述第一字线驱动信号,当自所述第三字线切换至所述第四字线时,所述自我刷新控制器将所述第二主要字线信号维持相同逻辑电平。 2. The memory according to claim 1 self refresh means, characterized in that said self refresh memory device further comprising: a second word line selection means for receiving a second main word line signal, the second word line selection module comprising: a third selection element, the first word line drive signal in accordance with a third word line selected; and a fourth selection element, a drive signal is selected according to a fourth word line to the second word line ; wherein when the second switch to the third word line from the word line, the self-refresh controller stops generating said first main word line signal and the second word line driving signals in sequence to produce the said second main word line signal and the first word line drive signal when the word line is switched from the third to the fourth word line, the self-refresh controller, the second main word line signal maintain the same logic level.
  3. 3.根据权利要求1所述的存储器自我刷新装置,其特征在于,所述第一选取元件为一第一反相器,所述第一反相器包括一第一供应电源端、一第一输入端以及一第一输出端,所述第一字线驱动信号经由所述第一供应电源端提供至所述第一反相器,所述第一主要字线信号经由所述第一输入端选择所述第一反相器,使得所述第一反相器经由所述第一输出端选择所述第一字线,其中所述第二选取元件为一第二反相器,所述第二反相器包括一第二供应电源端、一第二输入端以及一第二输出端,所述第二字线驱动信号经由所述第二供应电源端提供至所述第二反相器,所述第一主要字线信号经由所述第一输入端选择所述第二反相器,使得所述第二反相器经由所述第二输出端选择所述第二字线。 3. The memory according to claim 1 self refresh means, characterized in that said first selecting element is a first inverter, said first inverter comprises a first power supply terminal, a first a first input terminal and an output terminal, the first word line drive signal to the first inverter via the first power supply terminal via the first input of the first main word line signal selecting said first inverter, the first inverter such that said first selected word line via the first output terminal, wherein the second element is selected a second inverter, said first two inverter includes a second power supply terminal, a second input terminal and a second output terminal, the second word line drive signal to said second inverter via said second power supply terminal, the first main word line signal to select the second inverter via said first input terminal, the second inverter such that said second selected word line via the second output terminal.
  4. 4.根据权利要求3所述的存储器自我刷新装置,其特征在于,所述存储器自我刷新装置还包括: 一命令解码器,输出一致能信号,其中所述自我刷新控制器根据所述致能信号产生所述第一字线驱动信号、所述第二字线驱动信号、所述第一主要字线信号以及所述刷新信号。 4. The memory according to claim 3, wherein the self refresh means, characterized in that said self refresh memory device further comprising: a command decoder, an output enable signal, wherein the self-refresh controller in accordance with the enable signal generating the first word line drive signal, the second word line drive signal, the first main word line signal and the refresh signal.
  5. 5.根据权利要求4所述的存储器自我刷新装置,其特征在于,所述存储器自我刷新控制器还包括: 一自我刷新控制模块,根据所述致能信号以及一自我刷新信号,依序产生所述第一字线驱动信号以及所述第二字线驱动信号,并输出一状态信号以及所述刷新信号; 一自我刷新计时模块,接收所述状态信号并控制所述第一字线驱动信号以及所述第二字线驱动信号的时间间隔而发出一时间信号;以及一自我刷新计数模块,根据所述时间信号而产生所述自我刷新信号以及所述第一主要字线信号,并且在所述第二字线驱动信号切换至所述第一字线驱动信号之前,将所述第一主要字线信号维持相同的逻辑电平。 5. The memory as claimed in claim 4, wherein the self refresh means, wherein the memory self-refresh controller further comprising: a self-refresh control module, according to the enable signal and a self-refresh signal, sequentially generates the said first word line drive signal and the second word line driving signal, and outputs a signal, and the refresh state signal; a first word line drive signal a self-refresh timing module that receives the signal and controls the state and the second word line driving signal a time interval to emit a time signal; and a self-refresh counting module, generates the self refresh signal and the first main word line signal, and the signal from the time the second word line drive signal is switched to the first word line before the drive signal, the first main word line signal to maintain the same logic level.
  6. 6.一种存储器自我刷新方法,所述存储器自我刷新方法适用于一存储器阵列,其特征在于,其中所述存储器阵列包括多个存储器单元,所述存储器自我刷新方法包括: 根据一第一主要字线信号致能一第一字线选取模块,并依序选取一第一字线以及一第二字线;以及对选取的所述第一字线以及所述第二字线所对应的各所述存储器单元进行一自我刷新动作,其中当自所述第一字线切换至所述第二字线时,所述第一主要字线信号维持相同逻辑电平。 6. A memory self-refresh method, the memory self-refresh method is applied to a memory array, wherein the memory array comprises a plurality of memory cells, the memory self-refresh method comprising: a main word in accordance with a first line signal enabling a first word line selection module, and sequentially selecting a first word line and a second word line; and that each of the first word line and the selected word line corresponding to the second said memory unit performs a self-refresh operation, wherein when switching from the first word line to the second word line, said first main word line signal to maintain the same logic level.
  7. 7.根据权利要求6所述的存储器自我刷新方法,其特征在于,所述存储器自我刷新方法还包括: 根据一第二主要字线信号致能一第二字线选取模块,并依序选取一第三字线以及一第四字线;以及对选取的所述第三字线以及所述第四字线所对应的所述存储器单元进行一自我刷新动作,其中当自所述第三字线切换至所述第四字线时,所述第二主要字线信号维持相同逻辑电平。 7. The memory according to claim 6 self-refresh method, wherein the memory self-refresh method further comprising: according to a second main word line signal enabling a second word line selection module, and to sequentially select one third word line and a fourth word line; and the memory cells of the selected word line and the third line corresponding to the fourth word is a self-refresh operation, wherein when said third word line from when switched to the fourth word line, said second main word line signal to maintain the same logic level.
  8. 8.根据权利要求6所述的存储器自我刷新方法,其特征在于,所述第一选取元件为一第一反相器,所述第一反相器包括一第一供应电源端、一第一输入端以及一第一输出端,一第一字线驱动信号经由所述第一供应电源端提供至所述第一反相器,所述第一主要字线信号经由所述第一输入端选择所述第一反相器,使得所述第一反相器经由所述第一输出端选择所述第一字线,其中所述第二选取元件为一第二反相器,所述第二反相器包括一第二供应电源端、一第二输入端以及一第二输出端,一第二字线驱动信号经由所述第二供应电源端提供至所述第二反相器,所述第一主要字线信号经由所述第一输入端选择所述第二反相器,使得所述第二反相器经由所述第二输出端选择所述第二字线。 8. The memory of claim 6, wherein the self-refresh method, wherein said first selecting element is a first inverter, said first inverter comprises a first power supply terminal, a first a first input terminal and an output terminal, a first word line drive signal supplied via the first power terminal to the first inverter, the first main word line signal via the first input of the selector said first inverter, the first inverter such that said first selected word line via the first output terminal, wherein the second element is selected a second inverter, said second a second inverter includes a power supply terminal, a second input terminal and a second output terminal, a second word line drive signal supplied via the second power supply terminal to the second inverter, the the first main word line signal to select the second inverter via said first input terminal, the second inverter such that said second selected word line via the second output terminal.
  9. 9.根据权利要求8所述的存储器自我刷新方法,其特征在于,所述存储器自我刷新方法还包括: 根据一命令解码器输出的一致能信号而产生所述第一字线驱动信号、所述第二字线驱动信号、所述第一主要字线信号以及所述刷新信号。 9. The memory of claim 8, wherein the self-refresh method, wherein the memory self-refresh method further comprising: generating the first word line drive signal in accordance with a command enable signal output from the decoder, the the second word line drive signal, the first main word line signal and the refresh signal.
  10. 10.根据权利要求9所述的存储器自我刷新方法,其特征在于,所述存储器自我刷新方法还包括: 根据所述致能信号以及一自我刷新信号,依序产生所述第一字线驱动信号以及所述第二字线驱动信号,并输出一状态信号以及所述刷新信号; 根据所述状态信号,控制所述第一字线驱动信号以及所述第二字线驱动信号的时间间隔而发出一时间信号;以及根据所述时间信号产生所述自我刷新信号以及所述第一主要字线信号,其中在所述第二字线驱动信号切换至所述第一字线驱动信号之前,将所述第一主要字线信号维持相同的逻辑电平。 10. The memory according to claim 9, said self-refresh method, wherein the memory self-refresh method further comprising: the first word line drive signal of the enable signal and a self-refresh signal sequentially generated in accordance with and the second word line driving signal, and outputs a signal, and the refresh state signal; according to the state signal, controls the first word line drive timing signal and the second word line drive signal sent intervals a time signal; and prior to the self refresh signal and the first main word line signal in accordance with said time signal generation, wherein the switching to the first word line drive signal in the second word line driving signal, the said first main word line signal to maintain the same logic level.
CN 201410243626 2014-06-03 2014-06-03 Memory self-refresh apparatus and method CN105304117A (en)

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