JP2007220233A - Semiconductor memory device and semiconductor device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor memory device which can switch refresh cycles more properly. <P>SOLUTION: The semiconductor memory device comprises a plurality of memory cells which need refresh, memory cell arrays 1A, 11B which can be activated by selecting a word line and a bit line, a plurality of temperature sensors 22A, 22B, 22C, and 22D which detect a temperature of a chip 10 and output the detection results, an operation circuit 31 for generating a selection signal by calculating pieces of output of a plurality of the temperature sensors, an oscillator 21 for generating a plurality of refresh request signals with different periods to suggest refresh timing, a selection circuit 32 for selecting one of the refresh request signals with different periods according to the selection signal, and a refresh circuit 24 for refreshing each memory cell of the memory cell arrays according to the selected refresh request signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a volatile semiconductor memory device that needs to be refreshed, and a semiconductor device and an electronic device having such a semiconductor memory device.

  A DRAM is a semiconductor memory having the highest degree of integration and a low unit price per bit, and is widely used. The DRAM includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells that need to be refreshed arranged corresponding to the intersections of the word lines and the bit lines, and select the word lines and the bit lines. It is activated by. In order to maintain the stored data, the DRAM needs to periodically perform a refresh operation for rewriting each memory cell. In order to perform the refresh operation, power is consumed because rewriting is performed on the memory cell. Therefore, a semiconductor memory such as a DRAM that requires a refresh operation needs to perform the refresh operation periodically even if the memory cell is not accessed, and consumes power.

  In recent years, high speed and low power consumption are strongly demanded for semiconductor memory devices (semiconductor memories), and particularly low power consumption is strongly demanded for semiconductor memories used in mobile phones. . Therefore, it is necessary to further reduce the power consumption of a semiconductor memory that is used for such a purpose and requires a refresh operation.

  There are two methods for starting a refresh operation in a semiconductor memory that requires a refresh operation. One is a method of inputting a refresh command from the outside (memory controller) and starting a refresh operation in response thereto. Another method is a self-refresh method in which a refresh request is periodically generated inside a semiconductor memory chip to start a refresh operation. In order to perform self-refresh, an oscillator is provided in the chip and a refresh request signal is periodically generated.

  The interval at which the refresh request signal is generated is related to the time during which the charge accumulated in the memory cell leaks and the voltage drops to a predetermined value, and is determined based on various factors. The higher the temperature, the shorter the refresh interval. There is a need to. Therefore, in order to guarantee the operation within the operating temperature range of the semiconductor memory, the interval at which the oscillator generates the refresh request signal, that is, the cycle of the oscillator, is determined corresponding to the upper limit temperature of the operating temperature range. However, the period of the oscillator thus determined is shorter than necessary at room temperature and low temperature. As described above, since the refresh operation consumes power, a refresh operation with a cycle shorter than necessary is not preferable in order to reduce power consumption. Therefore, recently, a temperature sensor is installed in the chip, and the oscillator generates refresh request signals with different periods, and the period of the refresh request signal is switched according to the temperature detected by the temperature sensor, thereby reducing power consumption. Technology to plan has come to be used.

  FIG. 1 is a block diagram showing a configuration example of a conventional semiconductor memory device in which the cycle of a refresh request signal is switched according to temperature. As shown in FIG. 1, in a chip 10 that accommodates the semiconductor memory device, two memory cell arrays 11A and 11B, an oscillator 21 that generates refresh request signals having two different periods, and a predetermined threshold temperature Required for the refresh operation according to the temperature sensor 22 whose output is switched, the selection circuit 23 for selecting one of the two refresh request signals output from the oscillator 21 according to the temperature sensor 22, and the refresh request signal output from the selection circuit. And a refresh circuit 24 for generating a simple signal and outputting it to the memory cell arrays 11A and 11B. Since each circuit element shown here is widely known, description of its internal configuration and operation is omitted.

  The oscillator 21 outputs, for example, two refresh request signals having a cycle of 1.25 μs and 10 μs, and the selection circuit 23 outputs one logical value (for example, “low ( L) ") selects and outputs a refresh request signal with a period of 10 μs. When the chip temperature is high, that is, when the output of the temperature sensor 22 is the other logical value (for example,“ high (H) ”), the refresh request signal is 1 μs. A periodic refresh request signal is selected and output.

  Although not directly related to the refresh operation, providing a temperature sensor in the chip and optimizing the operation of the circuit according to the detected temperature is described in Patent Documents 1 and 2.

JP-A-5-335490 JP 2005-71364 A

  As described above, in the conventional semiconductor memory, only one temperature sensor is mounted. When the temperature in the chip is not uniform, the temperature detected by the temperature sensor and the temperature near the actual memory cell array are different. It can happen to be different. For example, even when the temperature of the memory cell array is high and the cycle of the refresh request signal must be shortened, the cycle of the refresh request signal is long when the temperature sensor detects the temperature of the low temperature portion, and the stored data May be lost. On the contrary, when the temperature of the memory cell array is lower than the temperature detected by the temperature sensor, the cycle of the refresh request signal is actually shorter than the cycle necessary for the memory cell array, and power is consumed wastefully.

  In particular, in recent years, high integration of semiconductor memories has progressed, and in order to improve the usage of large-capacity semiconductor memories, for example, the memory cell array can be divided into a large number of blocks and the operation state can be set for each block. By doing so, power consumption can be reduced. In this case, the operating block and the non-operating block have very different temperatures, and it is difficult to accurately detect the temperature of the memory cell array of the operating block with one temperature sensor.

  In addition, as described above, the logic value of the output changes depending on whether the temperature sensor is lower or higher than the predetermined threshold temperature, and one of the two cycle refresh request signals according to the output of the temperature sensor, One of the refresh request signals having a period of 25 μs and 10 μs is selected. As described above, the cycle of the refresh request signal to be selected is different by 8 times. For example, even when the optimum refresh cycle of the memory cell array is 8 μs, the refresh request signal having a cycle of 1.25 μs is selected. There is a problem that the difference from the refresh cycle is large. In other words, there is a problem in that fine refresh cycle control cannot be performed and sufficient power consumption cannot be reduced.

  An object of the present invention is to solve such a problem and to make it possible to more appropriately switch the refresh cycle in a semiconductor memory device (memory) that requires a refresh operation.

  In order to achieve the above object, a semiconductor memory device of the present invention includes a plurality of temperature sensors arranged in a chip, and appropriately switches a refresh cycle according to a plurality of outputs of the plurality of temperature sensors.

  That is, the semiconductor memory device of the present invention includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells that need to be refreshed arranged corresponding to the intersections of the word lines and the bit lines, A memory cell array activated by selecting the word line and the bit line, a plurality of temperature sensors that detect a chip temperature and output a detection result, and an output process of the plurality of temperature sensors An operation circuit for generating a selection signal, an oscillator for generating a refresh request signal having a plurality of different cycles for instructing timing for refreshing each memory cell of the memory cell array, and the plurality of different cycles according to the selection signal A selection circuit for selecting one of the refresh request signals, and the memory cell array according to the selected refresh request signal A refresh circuit for refreshing the memory cells, characterized by comprising a.

  According to the present invention, it is possible to detect more information about the temperature of the chip by the plurality of temperature sensors, process a lot of temperature information detected by the arithmetic circuit, and perform an appropriate refresh operation.

  When using a temperature sensor that outputs a binary signal that switches depending on whether it is higher or lower than the threshold temperature, the threshold temperature of a plurality of temperature sensors is different from that of at least some of the temperature sensors. Sometimes

  When using a plurality of temperature sensors having the same threshold temperature, it is possible to detect two-stage temperatures, and the plurality of temperature sensors are divided into different positions in the chip, for example, the memory cell array is divided into a plurality of blocks. If so, a temperature sensor is arranged corresponding to the memory cell array of each block to detect the temperature of the memory cell array of each block.

  Further, when a plurality of temperature sensors having the same threshold temperature are used and the oscillator outputs refresh request signals having two different periods, the arithmetic circuit is configured such that all of the plurality of temperature sensors are higher than the threshold temperature. Depending on the specifications of the semiconductor memory device, the selection signal may be switched when the output is determined to be higher than the threshold temperature, and the selection signal may be switched when the output is determined to be higher than the threshold temperature. Set.

  When temperature sensors having different threshold temperatures are used, it is possible to detect a plurality of stages of temperatures according to the number of temperature sensors to be used. Therefore, if the oscillator outputs three or more refresh request signals having a plurality of different cycles and uses three or more temperature sensors having different threshold temperatures, the refresh cycle and the temperature sensor are associated with each other. Different refresh cycles can be set according to the detected temperature, and the refresh cycle can be controlled more finely.

  As the arithmetic circuit, a circuit that can perform desired control by setting a setting signal in accordance with specifications can be configured with a simple gate circuit.

  A memory cell array is composed of a plurality of sub memory cell arrays, a refresh operation is possible for each sub memory cell array, and a mode setting circuit for outputting a mode setting signal for designating a sub memory cell array to be used among the plurality of sub memory cell arrays is provided. When further provided, the arithmetic circuit arithmetically processes the output of the temperature sensor corresponding to the sub memory cell array selected by the mode setting signal among the plurality of temperature sensors to generate a selection signal, and the refresh circuit sets the mode setting The sub memory cell array selected by the signal is refreshed. As a result, the refresh operation for the sub memory cell array that does not require the refresh operation is stopped, so that the power consumption can be reduced. In this case, a plurality of temperature sensors having the same threshold temperature are arranged corresponding to each sub memory cell array, and the arithmetic circuit determines that all of the temperature sensors corresponding to the sub memory cell array selected by the mode setting signal are higher than the threshold temperature. When the output is determined, the selection signal is switched, or when the output is determined that at least one of the temperature sensors corresponding to the sub memory cell array selected by the mode setting signal is higher than the threshold temperature, the selection signal is switched.

  It is possible to configure a semiconductor device by providing the semiconductor memory device requiring the refresh operation of the present invention in the same package together with one or more nonvolatile semiconductor memory devices.

  Furthermore, it is possible to realize an electronic device in which a semiconductor memory device requiring a refresh operation according to the present invention is combined with a processor to constitute a system.

  According to the present invention, in a semiconductor memory device (memory) that requires a refresh operation, it is possible to detect more information about the temperature of the chip and perform a more appropriate refresh operation. Thereby, the power consumption of the semiconductor memory device can be further reduced.

  FIG. 2 is a diagram showing the configuration of the semiconductor memory device (semiconductor memory) of the first embodiment of the present invention. As apparent from the comparison with the conventional example of FIG. 1, the semiconductor memory of the first embodiment includes four temperature sensors 22A, 22B, 22C and 22D arranged in the memory chip 10 and four temperature sensors. Is different from the conventional example in that an arithmetic circuit 31 is provided that processes the output of the above and outputs a selection signal to the selection circuit 32. The other parts are the same as in the conventional example. As shown in FIG. 2, the temperature sensors 22A and 22B are disposed near the memory cell array 11A, and the temperature sensors 22C and 22D are disposed near the memory cell array 11B.

  FIG. 3 is a diagram illustrating a circuit configuration of the temperature sensors 22A, 22B, 22C, and 22D. As shown in the figure, this temperature sensor has a resistor R1 and a pnp bipolar transistor Tr connected in series between a high potential power source Vrfv and a low potential power source Vss, and a resistor R2 between the high potential power source Vrfv and the low potential power source Vss. And a resistor R3 are connected in series, connected to a connection node of the resistor R1 and the bipolar transistor Tr and one input of the operational amplifier OP, and connected to a connection node of the resistors R2 and R3 and the other input of the operational amplifier OP. The bipolar transistor Tr operates as a resistor because the collector and the base are connected, and the resistance value changes according to the temperature of the junction, and the amount of change is larger than the change in the resistance values of the resistors R1, R2, and R3. . Therefore, the voltage at the connection node between the resistor R1 and the bipolar transistor Tr is lower than the voltage at the connection node between the resistor R2 and the resistor R3 when the temperature is lower than the threshold temperature, but is higher than the voltage at the connection node between the resistor R2 and the resistor R3. The output of the operational amplifier OP changes from “low (L)” to “high (H)”.

  FIG. 4 is a diagram showing the configuration of the oscillator 21 and the selection circuit 32. As shown in FIG. The portion denoted by reference numeral 41 is an oscillation circuit that oscillates by connecting inverters to seven stages and returning the output to the input stage. The oscillation signal is stopped by setting the enable signal to “low (L)”. The oscillation operation is performed by setting it to “high (H)”. The frequency dividing circuit 42 divides the oscillation signal output from the oscillation circuit 41 and outputs refresh request signals RF1 and RF2 having different periods, for example, 1.25 μs and 10 μs. Various division ratios can be used, and the cycle of the refresh request signal can be set as appropriate. The oscillator 21 includes an oscillation circuit 41 and a frequency dividing circuit 42.

  The selection circuit 32 selects the refresh request signal RF1 having a cycle of 1.25 μs and the refresh request signal RF2 having a cycle of 10 μs output from the frequency dividing circuit 42 in accordance with the selection signal Sel from the arithmetic circuit 31, and outputs the refresh request signal. To do. Specifically, when the selection signal Sel is “low (L)”, the refresh request signal RF2 having a period of 10 μs is output, and when the selection signal Sel is “high (H)”, the refresh request signal having a period of 1.25 μs. RF2 is output.

  FIG. 5 is a diagram showing a circuit configuration of the arithmetic circuit 31 of the first embodiment. In this arithmetic circuit, by setting the pattern signal Pat to “low (L)”, the selection signal Sel is switched when all the outputs TS1 to TS4 of the temperature sensor indicate high temperature, and the pattern signal Pat is set to “high (H)”. By setting to, the selection signal Sel can be switched when at least one of the temperature sensor outputs TS1 to TS4 indicates a low temperature.

  As shown in the figure, the arithmetic circuit 31 has a 4-input NOR gate and a NAND gate to which outputs TS1, TS2, TS3, and TS4 of four temperature sensors are input. The output of the NOR gate and the pattern signal Pat are input to the NAND gate, the output of the NAND gate and the inverted signal of the pattern signal Pat are input to another NAND gate, and the two outputs of those NAND gates are further input to the NAND gate. The output is input as a selection signal Sel via an inverter.

  Although detailed description of the operation of the arithmetic circuit 31 is omitted, when the pattern signal Pat is set to “low (L)”, when at least one of the outputs TS1 to TS4 of the four temperature sensors indicates a low temperature, that is, TS1 to TS4. Sel becomes “low (L)” when at least one of them is “low (L)”, and when all of TS1 to TS4 become “high (H)”, Sel changes to “high (H)”. Therefore, in the selection circuit 32 of FIG. 4, when at least one of TS1 to TS4 indicates a low temperature, a refresh request signal RF2 having a period of 10 μs is output, and when all of TS1 to TS4 indicate a high temperature, a refresh request having a period of 1.25 μs is output. A signal RF1 is output.

  Further, by setting the pattern signal Pat to “high (H)”, when all of TS1 to TS4 indicate low temperature, the refresh request signal RF2 having a period of 10 μs is output, and at least one of TS1 to TS4 indicates high temperature. Sometimes the refresh request signal RF1 having a cycle of 1.25 μs is output.

  As described above, the arithmetic circuit 31 outputs the selection signal for switching so that the refresh request signal RF2 having a period of 10 μs is output at a low temperature and the refresh request signal RF1 having a period of 1.25 μs is output at a high temperature. By setting the signal Pat, it is possible to set whether this switching is performed when all of TS1 to TS4 show a high temperature or when at least one of TS1 to TS4 shows a high temperature. The setting of the pattern signal Pat is appropriately performed according to the specifications of the semiconductor memory.

  FIG. 6 is a diagram showing a configuration of a semiconductor memory device (semiconductor memory) according to the second embodiment of the present invention. As is clear from the configuration of the semiconductor memory of the first embodiment of FIG. 2, the semiconductor memory of the second embodiment has four memory cell arrays (memory blocks) 11A, 11B, 11C, and 11D. The refresh circuit 54 is divided so that the refresh operation is possible for each sub memory cell array, and the mode setting for setting whether the refresh operation is performed in each of the four sub memory cell arrays 11A, 11B, 11C, and 11D. The circuit 53 is different from the semiconductor memory of the first embodiment. The four temperature sensors 22A, 22B, 22C, and 22D are arranged near the corresponding sub memory cell array. The configurations of the oscillator 21 and the selection circuit 32 are the same as those in the first embodiment.

  FIG. 7 is a diagram showing the configuration of the arithmetic circuit 51 of the second embodiment. In this arithmetic circuit 51, by setting the reverse pattern signal IPat to “high (H)”, the selection signal Sel is switched when all the outputs TS1 to TS4 of the temperature sensor indicate high temperature, and the reverse pattern signal IPat is set to “low ( L) ”, the selection signal Sel can be switched when at least one of the temperature sensor outputs TS1 to TS4 indicates a low temperature. In other words, the setting values of the pattern signal Pat of the arithmetic circuit 31 of the first embodiment and the reverse pattern signal IPat of the arithmetic circuit 51 of the second embodiment are opposite.

  In FIG. 7, TS1 to TS4 are outputs of the temperature sensors 22A, 22B, 22C, and 22D, and are “low (L)” when the temperature is lower than the threshold temperature. When the temperature is higher, “high (H)” is indicated. Mode1, Mode2, Mode3, and Mode4 are outputs of the mode setting circuit 53, and are “high (H)” when the refresh operation is performed in each of the sub memory cell arrays 11A, 11B, 11C, and 11D. “Low (L)” when not performed.

  Signals corresponding to TS1 to TS4 and Mode1 to Mode4 are respectively input to four NAND circuits, and outputs of the four NAND circuits are input to a four-input NAND gate. Further, the inverted signals of Mode1 to Mode4 and the corresponding signals of TS1 to TS4 are input to four NOR circuits, respectively, and the outputs of the four NOR circuits are input to a four-input NOR gate. The output of the 4-input NOR gate and the reverse pattern signal IPat are input to the NAND gate, and the output of the 4-input NAND gate and the inverted signal of the reverse pattern signal IPat are input to another NAND gate. The two outputs are further input to a NAND gate, and the output is output as a selection signal Sel via a two-stage inverter.

  Although detailed description of the operation of the arithmetic circuit 51 is omitted, the mode setting signal among the outputs TS1 to TS4 of the four temperature sensors is set to “high (H)” by setting the reverse pattern signal IPat to “high (H)”. When at least one of the outputs of the temperature sensor corresponding to the sub memory cell array indicated as “low” indicates a low temperature, that is, when it is “low (L)”, Sel becomes “low (L)”, and the selection circuit 32 of FIG. The refresh request signal RF2 with a period of is output. When the output of the temperature sensor corresponding to the sub memory cell array in which the mode setting signal is set to “high (H)” among TS1 to TS4 becomes “high (H)”, Sel changes to “high (H)”. In the selection circuit 32 of FIG. 6, a refresh request signal RF1 having a cycle of 1.25 μs is output.

  Further, by setting the reverse pattern signal IPat to “low (L)”, all of the outputs of the temperature sensors corresponding to the sub-memory cell arrays in which the mode setting signal is set to “high (H)” among TS1 to TS4 are low temperature. , A refresh request signal RF2 having a period of 10 μs is output, and at least one of the outputs of the temperature sensors corresponding to the sub-memory cell array whose mode setting signal is “high (H)” among TS1 to TS4 indicates a high temperature. Sometimes the refresh request signal RF1 having a cycle of 1.25 μs is output.

  In response to the refresh request signal RF1, the refresh circuit 54 performs a refresh operation on the sub memory cell array whose mode setting signal is set to “high (H)”.

  As described above, in the semiconductor memory of the second embodiment, by setting the mode setting signals Mode1 to Mode4, the sub memory cell array and the temperature sensor to be refreshed are determined, and the first implementation is performed on them. The same control as in the example can be performed.

  FIG. 8 is a diagram showing the configuration of the temperature sensor, the arithmetic circuit, and the selection circuit of the semiconductor memory according to the third embodiment of the present invention. The other parts are the same as in the first embodiment.

  In the third embodiment, N temperature sensors 22A, 22B,..., 22N are provided, and a plurality of threshold temperatures of the temperature sensors are set. The arithmetic circuit 61 calculates the outputs of the N temperature sensors and sets one of the four selection signals to “high (H)”. The number of temperature sensors and the types of threshold temperatures may be any number, but here, for simplicity of explanation, for example, three temperature sensors 22A, 22B, and 22C are provided, each having a different threshold temperature. And In other words, there are three types of threshold temperatures, and four stages of temperatures can be detected by calculating the outputs of the three temperature sensors.

  The frequency dividing circuit 62 divides the oscillation signal from the oscillation circuit and outputs refresh request signals having four different periods. In response to the selection signal from the arithmetic circuit 61, the selection circuit 63 selects one of the four refresh request signals having different periods from the frequency dividing circuit 62 and outputs the selected refresh request signal to the refresh circuit.

  In the third embodiment, since refresh request signals having four different cycles can be selected according to the temperature, the refresh cycle can be set more precisely according to the temperature.

  FIG. 9 is a diagram showing the configuration of the semiconductor memory device (memory) of the fourth embodiment of the present invention. The semiconductor memory of the fourth embodiment has a RAM 71 that requires a refresh operation and a flash memory 72 that does not require a refresh operation in a chip 70, and has a common address input ADD and data input / output DI / O. The control input RAMC of the RAM 71 and the control input FMC of the flash memory 72 are provided. Here, the RAM 71 is a semiconductor memory having a plurality of temperature sensors described in any of the first to third embodiments.

  FIG. 10 is a diagram showing the configuration of an electronic device according to a fifth embodiment of the present invention. The electronic device of the fifth embodiment includes a processor 81 and a memory 82 that needs a refresh operation in a chip 80. Here, the memory 82 is a semiconductor memory having a plurality of temperature sensors described in any of the first to third embodiments.

  As mentioned above, although the Example of this invention was described, it cannot be overemphasized that various modifications are possible.

  The present invention is applicable to any semiconductor memory that requires a refresh operation and any device having the same. In particular, it is desirable to apply the present invention to a semiconductor memory used in a mobile phone or the like that has a strong demand for low power consumption.

FIG. 1 is a diagram showing a configuration example of a conventional semiconductor memory device. FIG. 2 is a diagram showing a configuration example of the semiconductor memory device according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating an example of a temperature sensor circuit. FIG. 4 is a diagram illustrating an example of an oscillator circuit and a selection circuit. FIG. 5 is a diagram showing the arithmetic circuit of the first embodiment. FIG. 6 is a diagram showing a configuration example of a semiconductor memory device according to the second embodiment of the present invention. FIG. 7 is a diagram showing an arithmetic circuit according to the second embodiment. FIG. 8 is a diagram showing an arithmetic circuit / selection circuit of the third embodiment. FIG. 9 is a diagram showing the configuration of the semiconductor memory device according to the fourth embodiment of the present invention. FIG. 10 is a diagram showing the configuration of an electronic apparatus according to a fifth embodiment of the present invention.

Explanation of symbols

11A, 11B Memory cell array 21 Oscillator 22A, 22B, 22C, 22D Temperature sensor 24 Refresh circuit 31 Arithmetic circuit 32 Selection circuit

Claims (10)

A plurality of word lines, a plurality of bit lines, and a plurality of memory cells which are arranged corresponding to the intersections of the word lines and the bit lines and need to be refreshed, and select the word lines and the bit lines A memory cell array activated by
A plurality of temperature sensors that detect the temperature of the chip and output the detection results;
An arithmetic circuit for calculating the output of the plurality of temperature sensors and generating a selection signal;
An oscillator for generating a refresh request signal having a plurality of different periods for instructing a timing for refreshing each memory cell of the memory cell array;
A selection circuit that selects one of the refresh request signals of the plurality of different periods according to the selection signal;
And a refresh circuit for refreshing each memory cell of the memory cell array in response to the selected refresh request signal.   2. The semiconductor memory device according to claim 1, wherein each temperature sensor outputs a binary signal that switches depending on whether the temperature sensor is higher or lower than a predetermined threshold temperature, and the predetermined threshold temperatures of the plurality of temperature sensors are the same temperature. The oscillator outputs refresh request signals having two different periods,
The semiconductor memory device according to claim 2, wherein the arithmetic circuit switches the selection signal when all outputs of the plurality of temperature sensors are outputs determined to be higher than the predetermined threshold temperature. The oscillator outputs refresh request signals having two different periods,
The semiconductor memory device according to claim 2, wherein the arithmetic circuit switches the selection signal when at least one output of the plurality of temperature sensors is an output determined to be higher than the predetermined threshold temperature.   2. The semiconductor memory device according to claim 1, wherein each temperature sensor outputs a binary signal that switches according to whether the temperature is higher or lower than a predetermined threshold temperature, and at least a part of the plurality of temperature sensors has the predetermined threshold temperature different. The memory cell array is composed of a plurality of sub memory cell arrays, and a refresh operation is possible for each sub memory cell array.
A mode setting circuit for outputting a mode setting signal for designating a sub memory cell array to be used among the plurality of sub memory cell arrays;
The arithmetic circuit generates a selection signal by arithmetically processing the output of the temperature sensor corresponding to the sub memory cell array selected by the mode setting signal and the mode setting signal among the plurality of temperature sensors,
The semiconductor memory device according to claim 1, wherein the refresh circuit refreshes a sub memory cell array selected by the mode setting signal. Each temperature sensor outputs a binary signal that switches depending on whether it is higher or lower than a predetermined threshold temperature, and the predetermined threshold temperatures of the plurality of temperature sensors are the same temperature,
The oscillator outputs refresh request signals having two different periods,
7. The arithmetic circuit switches the selection signal when all outputs of the temperature sensor corresponding to the sub memory cell array selected by the mode setting signal are outputs determined to be higher than the predetermined threshold temperature. The semiconductor memory device described in 1. Each temperature sensor outputs a binary signal that switches depending on whether it is higher or lower than a predetermined threshold temperature, and the predetermined threshold temperatures of the plurality of temperature sensors are the same temperature,
The oscillator outputs refresh request signals having two different periods,
The arithmetic circuit switches the selection signal when at least one output of a temperature sensor corresponding to a sub memory cell array selected by the mode setting signal is an output determined to be higher than the predetermined threshold temperature. 6. The semiconductor memory device according to 6. One or more semiconductor memory devices that require refreshing according to claim 1 or 6;
A semiconductor device comprising one or more nonvolatile semiconductor memory devices in the same package. One or more semiconductor memory devices that require refreshing according to claim 1 or 6;
An electronic device comprising a system comprising a processor.

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