CN101399538B

CN101399538B - FPGA chip

Info

Publication number: CN101399538B
Application number: CN2008101167001A
Authority: CN
Inventors: 姜岩峰
Original assignee: North China University of Technology
Current assignee: Beijing University of Technology; North China University of Technology
Priority date: 2008-07-15
Filing date: 2008-07-15
Publication date: 2010-09-22
Anticipated expiration: 2028-07-15
Also published as: CN101399538A

Abstract

The invention relates to a FPGA chip which comprises a plurality of logic units. The logic units comprise a plurality of MRAMs which are based on a MTJ and form a logic array. The data in the MTJ is stored in a magnetic state and does not leak like charge as time goes on; therefore, in the power-down condition, the magnetization direction does not change, the data can be kept. Moreover, when electricity is supplied, the state of the stored data is induced by measuring the MTJ resistance, the state before the power-down can be quickly restored, and the FPGA restarts normal operation, which shortens starting time.

Description

A kind of fpga chip

Technical field

The present invention relates to technical field of integrated circuits, relate in particular to a kind of field programmable gate array chip based on magnetic tunnel-junction.

Background technology

The FPGA field programmable gate array is a kind of programming device, and the designer can utilize Software tool exploitation fast, emulation and test.FPGA provides high logic density, abundant characteristic, is widely used, handle and storage as data, and instrument and meter, telecommunications and Digital Signal Processing etc., have short, reliability advantages of higher of construction cycle.

At present, traditional FPGA based on SRAM is the most frequently used in the market kind.Based on the basic structure of the FPGA of SRAM memory, wherein comprise 3 * 3 logical block CLB, data channel, input module as shown in Figure 1,, thereby finish the distribution of FPGA integral working by connected mode and the operating state of control logic unit CLB.During each work,, the data in the SRAM memory are read among the CLB by the input module among the FPGA.Owing to adopt SRAM as memory element, when powering up startup, all need to fetch data at every turn by external read.When power supply was arranged, SRAM can preserve memory contents, but in case after the outage shutdown, the content of storing among the SRAM also can disappear automatically.

So, when restarting after the FPGA outage, need read in the memory contents of SRAM from external interface again, have only after the write state among the SRAM is finished, the state of the internal state register among the FPGA just can be decided, again return to the preceding state of outage last time, FPGA just can restart operate as normal then, so start-up time is all long.

Below, technical term of using among the present invention and breviary:

MTJ:Magnetic Tunnel Junction magnetic tunnel device;

MRAM:Magnetoresistive Random Access Memory magnetic random access memory;

FPGA:Field Programmable Gate Array field programmable gate array, a kind of programmable chip;

SRAM:Static RAM static random access memory;

CLB:Configurable Logic Block programmable logic cells.

Summary of the invention

In view of above-mentioned existing in prior technology problem, the purpose of this invention is to provide a kind of fpga chip based on MRAM, the MTJ among the MRAM can remember the data mode before the outage, makes the toggle speed once more of FPGA fast.

The objective of the invention is to be achieved through the following technical solutions:

A kind of fpga chip, it comprises a plurality of logical blocks, this logical block comprises mram memory, a plurality of mram memories have constituted logic array, this mram memory comprises MTJ and connected metal-oxide-semiconductor field effect transistor, this MTJ has fixed magnetic layer, thin insulating tunnel separator and free magnetosphere, this MTJ is connected with the positive input of an operational amplifier, the negative input of this operational amplifier connects a reference resistance, and the resistance of this reference resistance is between the high resistance and low resistance value of this MTJ.

Wherein, the low resistance of this MTJ is the magnetic moment direction of the free magnetosphere of MTJ when parallel with the magnetic moment direction of fixed magnetic layer, the resistance that MTJ has.

Wherein, the high resistance of this MTJ is the magnetic moment direction of the magnetic moment direction of free magnetosphere and fixed magnetic layer when antiparallel, the resistance that MTJ has.

As seen from the above technical solution provided by the invention, the present invention is based on the fpga chip of MRAM, and the data among the MTJ are stored with a kind of magnetic state, can can not leak along with the time like that by image charge, therefore under the situation of outage, the direction of magnetization no longer changes, and data just can be maintained; And when powering on, respond to stored data states by measuring MTJ resistance, automatically state " memory " is got up, the state before outage last time of the fast quick-recovery of FPGA enters operate as normal, has shortened start-up time.

Description of drawings

Fig. 1 is the FPGA device architecture schematic diagram based on SRAM of prior art;

Fig. 2 is a basic model mram memory cross-sectional view of the present invention;

Fig. 3 is a fpga chip structural representation of the present invention;

Fig. 4 is the syndeton schematic diagram of MRAM and operational amplifier in the fpga chip of the present invention;

Fig. 5 is the structural representation of operational amplifier among Fig. 4;

Fig. 6 is the fpga chip pin assignments schematic diagram of invention.

Embodiment

As shown in Figure 3, a kind of fpga chip comprises logic array and data channel that controller, I/O unit, a plurality of logical block are formed, by the connected mode and the operating state of control logic unit, thereby finishes the distribution of FPGA integral working.This logical block comprises the MRAM based on MTJ, a plurality of MRAM have constituted the logic array of cross arrangement, and (quantity of logical block just schematically among the figure, should not do limited explanation), bit line and digital line are across a plurality of logical blocks, and the chi structure of bit line and digital line can make each logical block can both obtain visit easily.The logical block of fpga chip is realized by the MTJ device, realizes its logic function by the resistance of control MTJ is big or small, thereby finishes the distribution of FPGA integral working.

As shown in Figure 2, based on the MRAM of MTJ, it adopts integrated circuit technology that a MTJ and a N-channel MOS field effect transistor are formed in chip manufacture.Promptly this MRAM is a basic model.MTJ has fixed magnetic layer 1, thin insulating tunnel separator 2 and free magnetosphere 3; The free magnetosphere 1 of this MTJ is connected with metal bit line BL1; The fixed magnetic layer 3 of this MTJ is connected with metal-oxide-semiconductor field effect transistor 4 (MOSFET), metal-oxide-semiconductor field effect transistor 4 is included in diffusion region, the source N+ that makes two high-dopant concentrations on the P type silicon substrate and leaks diffusion region N+, draw source S (Source) and drain D (Drain) more respectively, and metal 6, metal 7, oxide S iO2; The grid of this metal-oxide-semiconductor field effect transistor 4 is connected with word line WL1; The below of this MTJ is provided with digital line DL1; This word line WL1 and this digital line DL1 are arranged to row; This bit line BL1 is provided with and embarks on journey; This MTJ and this digital line DL1 have formed electric isolation by the SiO layer of this metal-oxide-semiconductor field effect transistor 4.

By among Fig. 2 as can be known, read data and write in the process of data at the MTJ memory and all will use bit line DL1, the magnetization of free magnetosphere 3 is decided jointly by the current impulse among orthogonal bit line BL1 and the digital line DL1 among the MTJ.In the magnetization process, shown in rotation direction arrow among the figure, single line provides the magnetic field of MTJ direction of easy axis, single line provides the magnetic field of MTJ hard direction in addition, just produced the peak value in a magnetic field at two line infalls, this peak value can surpass the switching threshold of the free magnetosphere 3 of MTJ, thereby makes the reversal of magnetism of the free magnetosphere 3 of MTJ, reverses.The magnetic moment direction of fixed magnetic layer 1 is changeless, when the magnetic moment direction of the magnetic moment direction of the free magnetosphere 3 of MTJ and fixed magnetic layer 1 antiparallel, MTJ has high resistance (logical value 1), when the magnetic moment direction of the free magnetosphere 3 of MTJ was parallel with the magnetic moment direction of fixed magnetic layer 1, MTJ had low resistance (logical value 0).

When data write MTJ, the drain electrode S and the source electrode D of word line WL1 control metal-oxide-semiconductor field effect transistor 4 end, bit line BL1 and digital line DL1 have electric current to flow through simultaneously, and electric current carries out writing of data by the magnetic field of two orthogonals that orthogonal bit line BL1 and digital line DLI produce in each intersection place.

When sense data, the drain D and the source S conducting of word line WL1 control metal-oxide-semiconductor field effect transistor 4, electric current is from bit line BL1 inflow and by MTJ and metal-oxide-semiconductor field effect transistor 4, and the size of current impulse depends on the height of MTJ resistance, and therefore the data of storage are just determined by the size of MTJ resistance in the position.

Referring to Fig. 4, Fig. 5, fpga chip of the present invention, its logical block also comprises operational amplifier, the positive input V+ of the free magnetosphere concatenation operation amplifier of MTJ, the negative input V-of operational amplifier connects a reference resistance R _Ref, the source S of metal-oxide-semiconductor field effect transistor connects power supply, this reference resistance R _RefResistance between the high resistance and low resistance value of this MTJ.Three input A, B of this MTJ device, C ₀(bit line, digital line, word line) controls the magnetic vector direction in its free magnetosphere, thereby can access the equivalent resistance R of MTJ correspondence, by the comparison of operational amplifier, determine that resistance states is low or the height and the data of therefore being stored, and finishes the realization of its logic function.

The present invention is based on the fpga chip of MTJ, not only its logical block is realized by the MTJ device, and MTJ the outage situation under, the MTJ direction of magnetization no longer changes, data just can be maintained, when powering on, respond to stored data states by measuring MTJ resistance, automatically state " memory " is got up, make the preceding state of the fast quick-recovery of FPGA outage last time, enter operate as normal, shortened start-up time.The present invention adopts operational amplifier, but known other of not getting rid of those skilled in the art can be measured the device of MTJ voltage, resistance.Operational amplifier is the technology of comparative maturity, does not do and gives unnecessary details, and its parameter sees the following form:

Parameter	Numerical value
Parameter	Numerical value	Supply power voltage	3.3V
Load capacitance	2pF	Supply power voltage	3.3V
Load capacitance	2pF	A _DC	≥60dB
UGBW	≥20MHz	A _DC	≥60dB
UGBW	≥20MHz	PM	≥70
SR	≥20V/μs	PM	≥70
SR	≥20V/μs	The maximum output voltage amplitude of oscillation	V _DD-0.45V≥Vout≥0.45V

Referring to Fig. 6, has abundant I/O pin based on the fpga chip of MTJ.The present invention is based on the fpga chip of MTJ, MRAM can be a MTJ and the basic model that metal-oxide-semiconductor field effect transistor forms in chip manufacture among Fig. 3, also can be existing follow-on MRAM, and is unrestricted.

Fpga chip is a kind of semi-custom circuit in the application-specific integrated circuit (ASIC) field, has both solved the deficiency of custom circuit, has overcome the limited shortcoming of original programming device gate circuit number again.Based on the fpga chip of MTJ, solved the FPGA power down after FPGA become white sheet, the defective that internal logic relation disappears realizes that FPGA can start fast once more.

The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.

Claims

1. fpga chip, it comprises a plurality of logical blocks, it is characterized in that, this logical block comprises mram memory, a plurality of mram memories have constituted logic array, this mram memory comprises MTJ and connected metal-oxide-semiconductor field effect transistor, this MTJ has fixed magnetic layer, thin insulating tunnel separator and free magnetosphere, this MTJ is connected with the positive input of an operational amplifier, the negative input of this operational amplifier connects a reference resistance, the resistance of this reference resistance is between the height of this MTJ, between the low-resistance value, by bit line, the signal controlling of digital line and word line input obtains the equivalent resistance of this MTJ correspondence, this operational amplifier is equivalent resistance and this reference resistance of this MTJ correspondence relatively, realizes the logic function of this logical block.

2. fpga chip according to claim 1 is characterized in that, the low resistance of this MTJ is the magnetic moment direction of the free magnetosphere of MTJ when parallel with the magnetic moment direction of fixed magnetic layer, the resistance that MTJ has.

3. fpga chip according to claim 1 is characterized in that, the high resistance of this MTJ is the magnetic moment direction of the magnetic moment direction of free magnetosphere and fixed magnetic layer when antiparallel, the resistance that MTJ has.