CN1052964A - Semicondctor storage array with interdigitated bit-line structure - Google Patents
Semicondctor storage array with interdigitated bit-line structure Download PDFInfo
- Publication number
- CN1052964A CN1052964A CN90106618A CN90106618A CN1052964A CN 1052964 A CN1052964 A CN 1052964A CN 90106618 A CN90106618 A CN 90106618A CN 90106618 A CN90106618 A CN 90106618A CN 1052964 A CN1052964 A CN 1052964A
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- China
- Prior art keywords
- bit line
- sensor
- sensor amplifier
- amplifier
- groups
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 230000005039 memory span Effects 0.000 description 2
- SVTBMSDMJJWYQN-UHFFFAOYSA-N 2-methylpentane-2,4-diol Chemical compound CC(O)CC(C)(C)O SVTBMSDMJJWYQN-UHFFFAOYSA-N 0.000 description 1
- 101000991410 Homo sapiens Nucleolar and spindle-associated protein 1 Proteins 0.000 description 1
- 101001095380 Homo sapiens Serine/threonine-protein phosphatase 6 regulatory subunit 3 Proteins 0.000 description 1
- ANNNBEZJTNCXHY-NSCUHMNNSA-N Isorhapontigenin Chemical compound C1=C(O)C(OC)=CC(\C=C\C=2C=C(O)C=C(O)C=2)=C1 ANNNBEZJTNCXHY-NSCUHMNNSA-N 0.000 description 1
- 102100030991 Nucleolar and spindle-associated protein 1 Human genes 0.000 description 1
- JXASPPWQHFOWPL-UHFFFAOYSA-N Tamarixin Natural products C1=C(O)C(OC)=CC=C1C1=C(OC2C(C(O)C(O)C(CO)O2)O)C(=O)C2=C(O)C=C(O)C=C2O1 JXASPPWQHFOWPL-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
Abstract
The spacing that is used to increase between bit line and between sensor amplifier is disclosed so that realize a kind of layout design method and the semiconductor memory array that can reduce sensor amplifier quantity of the manufacturing of semiconductor storage unit.This semicondctor storage array comprises multiple bit lines, a plurality of sensor amplifiers, each sensor amplifier is connected with each pairs of bit line, wherein, sensor amplifier by every row setting constitutes each group, the odd number pairs of bit line links to each other with idol or strange sensor amplifier, and the even-even bit line links to each other with sensor amplifier strange or idol.
Description
The present invention relates to semicondctor storage array, more precisely, relate to and have the semicondctor storage array that can increase the bit line structure of spacing between bit line.
In general, semiconductor storage unit comprises multiple bit lines, a plurality of sensor amplifiers, many word lines and a plurality of memory cell.Yet, because semiconductor storage unit trends towards comprising more storage unit, so that the spacing between corresponding each line reduce thereupon.
In other words, as reduce spacing between the bit line, the spacing between the sensor amplifier also reduces, and so, the layout of sensor amplifier is just very difficult.
At this moment, the miniaturization of semiconductor storage unit is because this memory device forming fine wiring makes that the manufacturing of this semiconductor storage unit is more complicated and difficult.
Among Fig. 1, conventional memory cell array, one-tenth pairs of bit line are connected on each bit lines.With reference to figure 1, because the number of sensor amplifier and being in proportion of memory span, so the stray capacitance of the line between the bit line and the circuit of drawing from sensor amplifier increases along with the increase of memory span.The increase of this stray capacitance is slowed down the operating rate of sensor amplifier, thereby has put off the access time.
Therefore, an object of the present invention is to provide a kind of spacing between the bit line and layout method of the spacing between the sensor amplifier of increasing, make the manufacturing that is easy to finish semiconductor storage unit.
Another object of the present invention provides a kind of semicondctor storage array that can reduce the sensor amplifier number.
According to one aspect of the present invention, semicondctor storage array of the present invention comprises multiple bit lines, with a plurality of sensor amplifiers, each sensor amplifier links to each other with each pairs of bit line, wherein, place the sensor amplifier of every row to constitute each group, the odd number pairs of bit line is connected on sense amplifier groups even number or odd number, and the even-even bit line is connected to sense amplifier groups odd number or even number.
According to another aspect of the present invention, semiconductor memory array of the present invention comprises a plurality of sensor amplifiers, multiple bit lines, and the bit line that starts from an amplifier group is not connected with bit line from adjacent sense amplifier groups.
How to realize the present invention being described below for understanding the present invention better and illustrating by the example reference accompanying drawing, in the accompanying drawing:
Fig. 1 is the conventional memory array;
Fig. 2 is according to memory array of the present invention; And
Fig. 3 is the detail view of Fig. 2 partial circuit.
Fig. 2 has illustrated the array according to bit line of the present invention and sensor amplifier, and Fig. 3 is the internal circuit diagram of the part 100 among Fig. 2.
With reference to figure 2, sensor amplifier constitutes each group.Each group comprises the sensor amplifier that is positioned at same column, and the spacing between the sensor amplifier is 4 live widths.That is, first pairs of bit line in the row is connected to (n-1) individual sense amplifier groups SAG
N-1First sensor amplifier SA1
N-1And (n+1) individual sense amplifier groups SAG
N+1The 1st sensor amplifier SA1
N+1Second pairs of bit line is connected to (n-2) group SAG
N-2The 1st sensor amplifier SA1
N-2And first sensor amplifier SA1n and (n+2) individual sense amplifier groups SAG of n sense amplifier groups SAGn
N+2The 1st sensor amplifier SA1
N+2The 3rd pairs of bit line is connected to (n-1) sense amplifier groups SAG
N-1The second sensor amplifier SA2
N-1With (n+1) sense amplifier groups SAG
N+1The 2nd sensor amplifier SA2
N+1, the 4th pairs of bit line is connected to (n-2) sense amplifier groups SAG
N-2The 2nd amplifier SA2
N-2And second sensor amplifier SA2n and (n+2) sense amplifier groups SAG of (n) sense amplifier groups SAGn
N+2The second sensor amplifier SA2
N+2
Therefore, can understand respectively just in time that (2k) (k is a positive integer) pairs of bit line is connected to (n-2) sense amplifier groups SAG
N-2K sensor amplifier SAK
N-2, (n) sense amplifier groups SAGn k sensor amplifier SAKn and (n+2) sense amplifier groups SAG
N+2K sensor amplifier SAK
N+2, and (2k+1) pairs of bit line is connected to (n-1) sense amplifier groups SAG
N-1K sensor amplifier SAK and (n+1) sensor amplifier SAG
N+1K sensor amplifier SAK
N+1
On the other hand, other method with the interconnection of bit line and sensor amplifier can be proposed.That is, respectively (2K) pairs of bit line is connected to (n-1) sense amplifier groups SAG
N-1(k) individual sensor amplifier SAK
N-1And (n+1) sense amplifier groups SAG
N+1(k) individual sensor amplifier SAK
N+1, and (2K-1) pairs of bit line is connected to (n-2) sense amplifier groups SAG
N-2(k) individual sensor amplifier SAK
N-2And (K) individual sensor amplifier SAKn and (n+2) sense amplifier groups SAG of (n) sense amplifier groups SAGn
N+2(k) individual sensor amplifier SAK
N+2
Owing to want wide two bit lines, the wiring of having relaxed sensor amplifier according to the conventional spacing between the gap ratio sensor amplifier between the sensor amplifier of the present invention.Can learn that also can reduce half owing to be connected to public number of reading the sensor amplifier of node SN, the so public node SN stray capacitance of reading reduces half from the internal circuit of Fig. 3.Therefore, publicly read reducing of node SN stray capacitance, quickened read operation.Among Fig. 3, circuit SAPL and SAPR are recovered clock, and ISOL and ISOR are the circuit that is used for bit line and sensor amplifier isolation.
Illustrated as preamble, the increase that the invention has the advantages that spacing between the sensor amplifier makes packs more that the topological design of the semicondctor storage array of multi-memory unit will be easy to finish.
Another advantage of the present invention is, owing to reduced public node and the stray capacitance of reading, makes read operation more fast.
More than describe most preferred embodiment of the present invention only has been described.For a person skilled in the art, the various modification that only do not depart from by the scope of the present invention that claims limited all are conspicuous.So, shown in and described embodiment be illustrative and nonrestrictive.
Claims (7)
1, a kind of semicondctor storage array of a plurality of sensor amplifiers that have multiple bit lines and link to each other with described one-tenth pairs of bit line is characterized in that:
Described sensor amplifier is divided into many groups, and each described sensor amplifier is connected to a pair of described bit line, and the right described bit line of odd number is connected to the sense amplifier groups of odd number, and the described bit line of even-even is connected to the sense amplifier groups of even number.
2, a kind of semicondctor storage array of a plurality of sensor amplifiers that have multiple bit lines and link to each other with described one-tenth pairs of bit line is characterized in that:
Described sensor amplifier is divided into many groups, and each described sensor amplifier is connected to a pair of described bit line, and the right described bit line of odd number is connected to the sense amplifier groups of described even number, and the described bit line of even-even is connected to the sense amplifier groups of described odd number.
3, a kind of semicondctor storage array with many pairs of bit line and a plurality of sensor amplifiers is characterized in that:
In each sides of two pairs of described bit lines in two a pair of described sensor amplifiers one is set, one in two sensor amplifiers is connected on a pair of that institute's rheme gives birth to, and another sensor amplifier is connected to described bit line another to last.
4, semiconductor memory array as claimed in claim 1 is characterized in that, the described bit line of sensor amplifier described in described each sense amplifier groups is not connected with described sensor amplifier in the described adjacent sense amplifier groups.
5, semiconductor memory array as claimed in claim 2 is characterized in that, the described bit line of sensor amplifier described in described each sense amplifier groups is not connected with described sensor amplifier in the described adjacent sense amplifier groups.
6, a kind of have a semiconductor memory array that multiple bit lines and described bit line are attached thereto a plurality of sensor amplifiers that connect, and it is characterized in that: the paired described bit line that is connected to each sensor amplifier is not connected with described adjacent sensor amplifier.
7, a kind of have a plurality of sensor amplifiers and with it the interconnection each described bit line and each are read the semiconductor memory array of node, with circuit described sensor amplifier is divided into a plurality of groups, it is characterized in that: described sense amplifier groups is not connected with described adjacent sense amplifier groups.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890020604A KR930001743B1 (en) | 1989-12-30 | 1989-12-30 | Bit-line array method of semiconductor memory device |
| KR20604/89 | 1989-12-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1052964A true CN1052964A (en) | 1991-07-10 |
| CN1022146C CN1022146C (en) | 1993-09-15 |
Family
ID=19294652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN90106618A Expired - Fee Related CN1022146C (en) | 1989-12-30 | 1990-07-31 | Semiconductor memory array having interdigitated bit-line structure |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH03212890A (en) |
| KR (1) | KR930001743B1 (en) |
| CN (1) | CN1022146C (en) |
| IT (1) | IT1241523B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002017326A1 (en) * | 1998-07-13 | 2002-02-28 | Shau Jeng Jye | High performance embedded semiconductor memory device with multiple dimension first-level bit-lines |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63205897A (en) * | 1987-02-20 | 1988-08-25 | Matsushita Electric Ind Co Ltd | Semiconductor storage device |
| JPS63225993A (en) * | 1987-03-13 | 1988-09-20 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPS6488993A (en) * | 1987-09-29 | 1989-04-03 | Nec Corp | Semiconductor memory |
-
1989
- 1989-12-30 KR KR1019890020604A patent/KR930001743B1/en not_active IP Right Cessation
-
1990
- 1990-03-22 JP JP2069925A patent/JPH03212890A/en active Pending
- 1990-07-31 CN CN90106618A patent/CN1022146C/en not_active Expired - Fee Related
- 1990-07-31 IT IT48188A patent/IT1241523B/en active IP Right Grant
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002017326A1 (en) * | 1998-07-13 | 2002-02-28 | Shau Jeng Jye | High performance embedded semiconductor memory device with multiple dimension first-level bit-lines |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03212890A (en) | 1991-09-18 |
| IT9048188A1 (en) | 1992-01-31 |
| KR910013269A (en) | 1991-08-08 |
| IT1241523B (en) | 1994-01-17 |
| IT9048188A0 (en) | 1990-07-31 |
| CN1022146C (en) | 1993-09-15 |
| KR930001743B1 (en) | 1993-03-12 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C15 | Extension of patent right duration from 15 to 20 years for appl. with date before 31.12.1992 and still valid on 11.12.2001 (patent law change 1993) | ||
| OR01 | Other related matters | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |