CN105271103A - Nano-structure array and manufacturing method and application thereof - Google Patents
Nano-structure array and manufacturing method and application thereof Download PDFInfo
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- CN105271103A CN105271103A CN201510684152.2A CN201510684152A CN105271103A CN 105271103 A CN105271103 A CN 105271103A CN 201510684152 A CN201510684152 A CN 201510684152A CN 105271103 A CN105271103 A CN 105271103A
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Abstract
The invention provides a nano-structure array and a manufacturing method and an application thereof. The area of the nano-structure array is 100-250,000mum<2>, and the line width of the nano-array is 3-15 nanometers. The manufacturing method of the nano-structure array comprises the following steps: performing a surface treatment on a substrate; forming a nano-structure array pattern on the substrate by adopting an electron beam exposure technology; and depositing a substance to be deposited on the nano-structure array pattern, peeling a deposit, and performing a post treatment on the deposit to obtain the nano-structure array. The manufacturing method has high controllability and repeatability. A manufactured nano-structure is uniform in size, up to a sub-millimeter grade in area, and suitable for various materials. The substrate for manufacturing the nano-structure array is reusable, so that standard and quantitative researches can be carried out easily. The developments of devices using the nano-structure array towards smaller sizes, larger areas and more stable processes can be facilitated. The nano-structure array can be widely applied to the fields of chips, biological and chemical sensing, nano-optics, plasma resonance and the like.
Description
Technical field
The invention belongs to technical field of nano material, relate to a kind of nano-structure array and its production and use, particularly relate to a kind of submillimeter area near limit sized nanostructures array and its production and use.
Background technology
Nano material likely produces new phenomenon along with the further reduction of size, shows the character and performance that make new advances.Such as, research finds that plasma resonance enhancement effect in the gold nano structure in sub-10nm gap has the lifting of several order of magnitude.Therefore, near limit sized nanostructures has broad application prospects in fields such as various chip information technology, biological and chemical sensor, nanocomposite optical, plasma resonances.
At present, the method making near limit sized nanostructures mainly contains two kinds: chemical synthesis process from bottom to top, such as self-assembling technique; And top-down fabrication method.Chemical synthesis process makes nanostructured and typically refers to synthesis of nano particle in the solution, there is the nano gap that interaction can form near limit size between nano particle.Nanofabrication technique is the processing utilizing the technology such as electron beam exposure, etching and plated film to realize nano-precision, namely realizes the removal of material surface atom and molecule, resettlement and restructuring.Compared with chemical synthesis process, utilize nanofabrication technique to make near limit sized nanostructures and there is following advantage: nanostructure size is homogeneous controlled; Nano-structure design is adjustable flexibly; Nanofabrication technique is applicable to processing and the preparation of various metal and nonmetallic materials etc.; The nanostructure substrate made is reusable, conveniently preserves for a long time; Be easy to carry out standardization and Quantitative study etc.
Research about nano array structure is existing a lot, as CN101486439A discloses a kind of germanium nanopoint/silicon nanowire array structure thin film and preparation method thereof, described germanium nanopoint/silicon nanowire array structure thin film is primarily of silicon nanowire array and germanium nanopoint composition, and described germanium nanopoint is distributed on the silicon nanowires of silicon nanowire array; Its preparation method mainly comprises: utilize P type or n type single crystal silicon, polysilicon does original material; Etching method is utilized to prepare bulk silicon nano-wire array; Then use low-pressure chemical vapor deposition technology, use germane is source of the gas, and bulk silicon nano-wire array substrate is prepared germanium point.CN102110597A discloses a kind of method realizing the long lines of sub-10nm grid: the long-pending or thermal oxide growth dielectric layer of pad, the long-pending gate material of pad, the exposure of positive electronic bundle the long-pending medium of oxides layer of etched recesses, pad, medium of oxides layer surface planarisation, the exposure of positive electronic bundle etched recesses and etching gate material etc. on substrate.
The near limit sized nanostructures controlled due to preparation appearance and size remains at a lot of technical difficulty, and the method therefore making large area near limit sized nanostructures have not been reported.The making of dimension limit nanostructured not only needs to solve many key technologies in nanoprocessing process, and needs deeply to understand, understand fully the general principle such as physics chemical action of various complexity in the process such as electron beam exposure, etching and plated film.The less parameter to various machining process of processing dimension is more responsive, more wayward.Therefore, be difficult to completely conveniently technique thinking and countermeasure and go Development limitation dimensioned technology, and first must verify the most critical parameters of impact and controlling dimension and crudy in each process under dimension limit, so just likely developed into stable process technology.Therefore, the present invention precisely controls the technologies such as electron beam exposure, plated film, stripping and etching according to this basic ideas, thus realizes processing and the preparation of larger area near limit sized nanostructures array.
Summary of the invention
The object of the present invention is to provide a kind of nano-structure array and its production and use, the nanostructure size of described nano-structure array is homogeneous, array area reaches submillimeter level, material category is various, can be widely used in chip, biology and chemical sensitisation, nanocomposite optical and Plasmon Resonance field.
For reaching this object, the present invention by the following technical solutions:
A kind of nano-structure array, the area of described nano-structure array is 100-250000 μm
2, the live width of described nano-structure array is 3-15nm.
Described nano-structure array is the nano-structure array of submillimeter area near limit size.The area of described nano-structure array is 100-250000 μm
2, as 200 μm
2, 500 μm
2, 1000 μm
2, 5000 μm
2, 10000 μm
2, 50000 μm
2, 100000 μm
2, 150000 μm
2, 200000 μm
2or 240000 μm
2deng, the live width of described nano-structure array is 3-15nm, and as 3nm, 4nm, 5nm, 8nm, 10nm, 12nm or 14nm etc., the live width of described nano-structure array refers to the width of linear nano structured channel.
Described nano-structure array can be two-dimensional structure array, also can be three-dimensional structure array.
The thickness of described nano-structure array is 1-100nm, as 2nm, 5nm, 10nm, 20nm, 30nm, 50nm, 70nm, 80nm or 90nm etc.
Preferably, the component of described nano-structure array is metal, metal oxide or the combination except any one in the semi-conducting material of burning beyond the region of objective existence or at least two kinds, typical but non-limitingly to be combined as: metal and metal oxide, metal oxide and semi-conducting material, metal and semi-conducting material, metal, metal oxide and semi-conducting material.The component of described nano-structure array is not limited to metal, metal oxide or semi-conducting material, and those skilled in the art can select suitable component according to the actual needs.
Preferably, described metal is the combination of any one or at least two kinds in gold, platinum, silver, copper, chromium, aluminium, nickel, titanium, germanium, niobium or tantalum, typical but non-limitingly to be combined as: gold and platinum, silver, copper and chromium, platinum, silver and copper, chromium, aluminium, nickel, titanium and germanium, aluminium, nickel, titanium, germanium, niobium and tantalum.
Preferably, described metal oxide is the combination of any one or at least two kinds in titanium oxide, zinc oxide, aluminium oxide, cadmium oxide, indium oxide, typical but non-limiting oxide-metal combinations is: titanium oxide and zinc oxide, aluminium oxide, cadmium oxide and indium oxide, aluminium oxide and cadmium oxide, zinc oxide, aluminium oxide and cadmium oxide.
Preferably, the described semi-conducting material except burning beyond the region of objective existence is the combination of any one or at least two kinds in niobium nitride, titanium nitride, zirconium nitride, GaAs, indium phosphide, gallium nitride, typical but non-limiting semiconductor material combinations can be: titanium nitride and zirconium nitride, niobium nitride, GaAs and indium phosphide, indium phosphide and gallium nitride, GaAs, indium phosphide and gallium nitride.
Present invention also offers a kind of preparation method of nano-structure array, described method comprises the steps:
(1) surface treatment is carried out to substrate;
(2) adopt electron beam lithography on substrate, prepare nano-structure array pattern;
(3) on nano-structure array pattern, deposit thing to be deposited, peel off deposit and post processing is carried out to it, obtaining nano-structure array.
Nano-structure array provided by the invention first adopts electron beam exposure method on substrate, prepare nano-structure array pattern, deposits thing to be deposited afterwards on nano-structure array pattern, then is peeled off by deposit and carry out post processing and obtain.
Step (1) described substrate is silicon, quartz or SOI (silicon in dielectric substrate).Described substrate is not limited to this three kinds of materials, and those skilled in the art can select different substrates according to actual conditions.
Preferably, step (1) described surface treatment is: with RCA standard cleaning method cleaning substrate, and use oxygen plasma treatment substrate surface.
Preferably, described oxygen plasma treatment is carried out on plasma surface treatment instrument.Because described substrate is for the preparation of nano-structure array, the situation of substrate surface will affect the form of obtained product, therefore extremely important to the process of substrate surface.
Preferably, the power of described plasma surface treatment instrument is 50-150W, as 55W, 60W, 70W, 80W, 100W, 120W, 130W or 140W etc.
Preferably, the time of described oxygen plasma treatment is 0.5-5min, as 1min, 1.5min, 2min, 2.5min, 3min, 3.5min, 4min or 4.5min etc.
Step (2) described electron beam lithography is specially: first spin coating electronic corrosion-resistant on substrate after surface treatment, then develops with electron beam exposure electronic corrosion-resistant.
Preferably, described electronic corrosion-resistant can be positive electronic corrosion-resistant and/or negative electronic erosion-resisting agent, is preferably negative electronic erosion-resisting agent.The exposure sensitivity of negative electronic erosion-resisting agent is more much higher than positive electronic corrosion-resistant.
Preferably, the thickness of the electronic corrosion-resistant after spin coating is 30-300nm, as 30nm, 50nm, 80nm, 100nm, 150nm, 200nm, 250nm, 300nm etc.
Preferably, the beam spot size of described electron beam is 0.5-10nm, as 1nm, 1.5nm, 2nm, 3nm, 4nm, 5nm, 6nm, 8nm or 9nm etc.
The less parameter to various machining process of processing dimension is more responsive, more wayward.And the preparation impact of the beam spot size of the kind of electronic corrosion-resistant, spin coating thickness and electron beam on nano-structure array is very large, these parameters cooperatively interact, and just can obtain the nano-structure array preset.
Preferably, the developer solution that described development uses is acetone, any one in acetone soln, sodium hydroxide solution, methyl iso-butyl ketone (MIBK) or methyl isobutyl ketone solution.
Preferably, the time of described development is 0.5-5min, as 1min, 2min, 3min or 4min etc.
Step (3) adopts hot evaporation, electron beam evaporation plating or magnetron sputtering deposition thing to be deposited.
Preferably, the speed of step (3) described deposition is
as
or
deng.
Preferably, the described sedimental thickness of step (3) is 1-100nm, as 2nm, 5nm, 10nm, 20nm, 30nm, 50nm, 70nm, 80nm or 90nm etc.
Preferably, the described thing to be deposited of step (3) is metal, metal oxide or the combination except any one or at least two kinds in the semi-conducting material of burning beyond the region of objective existence, typical but non-limitingly to be combined as: metal and metal oxide, metal oxide and semi-conducting material, metal and semi-conducting material, metal, metal oxide and semi-conducting material.
Preferably, described metal is the combination of any one or at least two kinds in gold, platinum, silver, copper, chromium, aluminium, nickel, titanium, germanium, niobium or tantalum, typical but non-limitingly to be combined as: gold and platinum, silver, copper and chromium, platinum, silver and copper, chromium, aluminium, nickel, titanium and germanium, aluminium, nickel, titanium, germanium, niobium and tantalum.
Preferably, described metal oxide is the combination of any one or at least two kinds in titanium oxide, zinc oxide, aluminium oxide, cadmium oxide, indium oxide, typical but non-limiting oxide-metal combinations is: titanium oxide and zinc oxide, aluminium oxide, cadmium oxide and indium oxide, aluminium oxide and cadmium oxide, zinc oxide, aluminium oxide and cadmium oxide.
Preferably, the described semi-conducting material except burning beyond the region of objective existence is the combination of any one or at least two kinds in titanium nitride, zirconium nitride, GaAs, indium phosphide, gallium nitride, typical but non-limiting semiconductor material combinations can be: titanium nitride and zirconium nitride, GaAs and indium phosphide, indium phosphide and gallium nitride, GaAs, indium phosphide and gallium nitride.
Step (3) adopts acetone, sodium hydroxide solution or hydrofluoric acid solution to peel off deposit.
Preferably, the time of step (3) described stripping is 1-10min, as 2min, 3min, 4min, 5min, 6min, 7min, 8min or 9min.
Preferably, step (3) described post processing is: remove the electronic corrosion-resistant remained on deposit.
The electronic corrosion-resistant remained on deposit can adopt multiple method to remove, and is preferably and uses etching method to remove electronic corrosion-resistant.
Preferably, the etching gas that described etching method uses is fluoroform (CHF
3) with the gaseous mixture of argon gas or oxygen.
Preferably, the time of described etching is 5s-5min, as 10s, 20s, 30s, 50s, 1min, 2min, 3min, 4min or 4.5min.
Preferably, the speed of described etching is 50-500nm/min, as 60nm/min, 80nm/min, 100nm/min, 200nm/min, 300nm/min, 400nm/min or 450nm/min etc.
As preferred technical scheme, described preparation method comprises the steps:
(1) RCA standard cleaning method and oxygen plasma treatment is adopted to carry out surface treatment to substrate;
(2) negative electronic erosion-resisting agent that substrate surface spin coating 30-300nm is after surface treatment thick, be the electron beam exposure negative electronic erosion-resisting agent of 0.5-10nm with beam spot size afterwards and develop, the time of development is 0.5-5min, obtains nano-structure array pattern;
(3) on nano-structure array pattern with
deposition rate thickness be the thing to be deposited of 1-100nm, and deposit to be peeled off, obtains overburden;
(4) remove negative electronic erosion-resisting agent residual on overburden with the speed of 50-500nm/min etching, the time of etching is 5s-5min, obtains the nano-structure array that live width is 3-15nm.
Nano-structure array provided by the invention is submillimeter area near limit sized nanostructures array, it adopts electron beam exposure electronic corrosion-resistant, form the electronic corrosion-resistant nano-structure array pattern of near limit size, deposition thing to be deposited after development, then peel off, the electronic corrosion-resistant of etching residue again, has finally prepared the nano-structure array of near limit characteristic size (sub-10nm).
Present invention also offers the purposes of described nano-structure array, it is for chip, biology and chemical sensitisation, nanocomposite optical or plasma resonance field.
Compared with prior art, beneficial effect of the present invention is:
Preparation method's controllability of submillimeter area near limit sized nanostructures array provided by the invention and reproducible, the nanostructure size of preparation is homogeneous, and area reaches submillimeter level, is applicable to multiple material; The substrate preparing nano-structure array is reusable, is easy to carry out standardization and Quantitative study.
Submillimeter area near limit sized nanostructures array provided by the invention uses impelling the future development that the device of nano-structure array is less towards size, area is larger and technique is more stable, and it will have in fields such as chip information technology, biology and chemical sensitisation, nanocomposite optical and Plasmon Resonance applies very widely.
Accompanying drawing explanation
The scanning electron microscope (SEM) photograph of the nano-structure array pattern that Fig. 1 provides for embodiment 1.Wherein, (a) is triangle nano-array pattern; B () is quadrangle nano-array pattern; C () is hexagon nano-array pattern.
The scanning electron microscope (SEM) photograph of the gold nano array of structures that Fig. 2 provides for embodiment 1.Wherein, (a) is triangle nano-structure array; B () is quadrangle nano-structure array; C () is hexagon nano-structure array.
The scanning electron microscope (SEM) photograph of the gold nano array of structures that Fig. 3 provides for embodiment 2.Wherein, (a) is triangle nano-structure array; B () is quadrangle nano-structure array; C () is hexagon nano-structure array.
The scanning electron microscope (SEM) photograph of the copper nano-structure array that Fig. 4 provides for embodiment 3.Wherein, (a) is triangle nano-structure array; B () is quadrangle nano-structure array; C () is hexagon nano-structure array.
Detailed description of the invention
Technical scheme of the present invention is further illustrated by detailed description of the invention below in conjunction with accompanying drawing.
Embodiment 1:
The preparation method of gold nano array of structures, comprises the steps:
(1) adopt RCA standard cleaning method cleaning silicon (100) substrate, employing power is oxygen plasma surface treatment instrument process silicon (100) the substrate 2min of 60W;
(2) on three substrates, spin coating thickness is the negative electronic erosion-resisting agent of 100nm respectively, employing beam spot diameter, is the electron beam exposure electronic corrosion-resistant of 1nm, electron-beam exposure system is connected with pattern generator, regulates electron beam exposure dosage to be respectively 60000 μ C/cm
2, 80000 μ C/cm
2with 100000 μ C/cm
2obtain triangle, quadrangle and hexagon nano-array pattern (as shown in Figure 1), nano-array pattern is of a size of 100 μm × 100 μm, and the live width of triangle, quadrangle and hexagon nano-array pattern is respectively 5.8nm, 8.7nm and 8.7nm; Be that the NaOH solution of 1% is to the triangle obtained, quadrangle and hexagon nano-array pattern development 4min with mass percentage, use pure water rinsing 2min afterwards, again respectively with the alcohol immersion substrate 10min that mass percentage is 30%, 50%, 70%, 85% and 95%, with soaked in absolute ethyl alcohol substrate twice, each 10min, finally uses critical point drying instrument drying substrates;
(3) adopt the electron beam evaporation chromium that evaporation 2nm is thick on nano-array pattern, the gold that evaporation 20nm is thick on chromium more afterwards, the sedimentation rate of chromium and gold is respectively
with
by the ultrasonic stripping 8min in BOE solution of the substrate after plated metal;
(4) with CHF
3for the upper residual negativity electronics etching agent of etching gas etching gold, etch period is 1min, obtains triangle, quadrangle and hexagonal gold nano array of structures (as shown in Figure 2).
Embodiment 2:
The preparation method of gold nano array of structures:
Thickness except negative electronic erosion-resisting agent is 80nm, and the beam spot diameter, of electron beam is 0.5nm, and electron beam exposure dosage is 60000 μ C/cm
2, the nano-array pattern obtained is of a size of 150 μm × 150 μm; Substrate pure water rinsing 2min after development, then rinses 1min with isopropyl alcohol, finally dries up with high pure nitrogen; Nano-structure array pattern deposits the gold that 20nm is thick, and the sedimentation rate of gold is
outward, all the other are identical with embodiment 1.The gold nano array of structures obtained as shown in Figure 3, learn by measurement, and the live width of triangle, quadrangle and hexagon nano-array is respectively 8.7nm, 5.8nm and 9.8nm.
Embodiment 3:
The preparation method of copper nano-structure array:
Except nano-structure array pattern is of a size of 150 μm × 150 μm, first deposit the chromium of 8nm in electron beam evaporation plating process, then deposit the copper of 15nm, the sedimentation rate of chromium and copper is respectively
with
outward, all the other are identical with embodiment 1.The copper nano-structure array obtained as shown in Figure 4, learn by measurement, and the live width of triangle, quadrangle and hexagon nano-array is respectively 5.8nm, 8.7nm and 11.7nm.
Embodiment 4:
The preparation method of niobium nitride nano-structure array:
Except electron beam exposure dosage is 100000 μ C/cm
2; Adopt magnetron sputtering method on nano-structure array pattern, deposit the thick niobium nitride of 20nm, sedimentation rate is
adopt the ultrasonic stripping niobium nitride of acetone, splitting time is 4min; Be that etching gas etching residue is peeling off the negativity electronics etching agent on niobium nitride with oxygen, etch period is outside 15s, and all the other are identical with embodiment 1.
Embodiment 5:
The preparation method of alumina nanostructures array:
(1) adopt RCA standard cleaning method cleaning substrate, and carry out oxygen plasma surface treatment with the plasma surface treatment instrument that power is 50W to substrate, the processing time is 5min;
(2) at the negative electronic erosion-resisting agent that substrate surface spin coating 30nm is thick, be the electron beam exposure negative electronic erosion-resisting agent of 0.5nm with beam spot size afterwards and develop, the solvent that development uses is acetone, the time of development is 0.5min, by the substrate pure water rinsing 2min after development, then rinse 1min with isopropyl alcohol, finally dry up with high pure nitrogen, obtain triangle nano-array pattern;
(3) adopt hot evaporation process on triangle nano-array pattern with
deposition rate thickness be the aluminium oxide of 10nm, and will deposition aluminium oxide peel off, peel off use solvent be acetone, the time of stripping is 1min;
(4) negative electronic erosion-resisting agent residual on aluminium oxide is removed with the speed of 50nm/min etching, the time of etching is 5s, etching gas is oxygen, and obtain the aluminium oxide triangle nano-structure array that live width is 3nm, the area of alumina nanostructures array is 100 μm
2.
Embodiment 6
The preparation method of zirconium nitride nano-structure array:
(1) adopt RCA standard cleaning method cleaning substrate, and carry out oxygen plasma surface treatment with the plasma surface treatment instrument that power is 150W to substrate, the processing time is 0.5min;
(2) at the negative electronic erosion-resisting agent that substrate surface spin coating 300nm is thick, be the electron beam exposure negative electronic erosion-resisting agent of 10nm afterwards with beam spot size, sodium hydroxide solution develops, the time of development is 2min, by the substrate pure water rinsing 2min after development, then rinse 1min with isopropyl alcohol, finally dry up with high pure nitrogen, obtain quadrangle nano-array pattern;
(3) adopt magnetron sputtering technique on quadrangle nano-array pattern with
deposition rate thickness be the zirconium nitride of 100nm; And the zirconium nitride of deposition is peeled off, peeling off the solvent used is hydrofluoric acid solution, and the time of stripping is 10min;
(4) remove negative electronic erosion-resisting agent residual on zirconium nitride with the speed of 500nm/min etching, the time of etching is 5min, and etching gas is fluoroform (CHF
3) and argon gas, obtain the zirconium nitride quadrangle nano-structure array that live width is 15nm, the area of zirconium nitride nano-structure array is 250000 μm
2.
Embodiment 7
The preparation method of titanium dioxide nanostructure array:
(1) adopt RCA standard cleaning method cleaning substrate, and carry out oxygen plasma surface treatment with the plasma surface treatment instrument that power is 100W to substrate, the processing time is 2min;
(2) at the positive electronic corrosion-resistant that substrate surface spin coating 100nm is thick, be the electron beam exposure positive electronic corrosion-resistant of 5nm with beam spot size afterwards and develop, the mixed solution that the solvent that development uses is methyl iso-butyl ketone (MIBK) and acetone, the time of development is 2min, by the substrate pure water rinsing 2min after development, then rinse 1min with isopropyl alcohol, finally dry up with high pure nitrogen, obtain hexagon nano-array pattern;
(3) adopt electron beam evaporation on pentagon nano-array pattern with
deposition rate thickness be the titanium dioxide of 30nm; And the titanium dioxide of deposition is peeled off, peel off and use acetone, the time of stripping is 5min;
(4) negative electronic erosion-resisting agent residual on titanium dioxide is removed with the speed of 100nm/min etching, the time of etching is 1min, etching gas is oxygen, and obtain the titanium dioxide hexagon nano-structure array that live width is 10nm, the area of titanium dioxide nanostructure array is 100000 μm
2.
Applicant states; the foregoing is only the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; person of ordinary skill in the field should understand; anyly belong to those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all drop within protection scope of the present invention and open scope.
Claims (10)
1. a nano-structure array, is characterized in that, the area of described nano-structure array is 100-250000 μm
2, the live width of described nano-structure array is 3-15nm.
2. nano-structure array according to claim 1, is characterized in that, the thickness of described nano-structure array is 1-100nm;
Preferably, the component of described nano-structure array is metal, metal oxide or the combination except any one or at least two kinds in the semi-conducting material of burning beyond the region of objective existence;
Preferably, described metal is the combination of any one or at least two kinds in gold, platinum, silver, copper, chromium, aluminium, nickel, titanium, germanium, niobium or tantalum;
Preferably, described metal oxide is the combination of any one or at least two kinds in titanium oxide, zinc oxide, aluminium oxide, cadmium oxide, indium oxide;
Preferably, the described semi-conducting material except burning beyond the region of objective existence is the combination of any one or at least two kinds in niobium nitride, titanium nitride, zirconium nitride, GaAs, indium phosphide, gallium nitride.
3. the preparation method of nano-structure array according to claim 1 or 2, it is characterized in that, described method comprises the steps:
(1) surface treatment is carried out to substrate;
(2) adopt electron beam lithography on substrate, prepare nano-structure array pattern;
(3) on nano-structure array pattern, deposit thing to be deposited, peel off deposit and post processing is carried out to it, obtaining nano-structure array.
4. preparation method according to claim 3, is characterized in that, step (1) described substrate is silicon, quartz or SOI;
Preferably, step (1) described surface treatment is: with RCA standard cleaning method cleaning substrate, and use oxygen plasma treatment substrate surface;
Preferably, described oxygen plasma treatment is carried out on plasma surface treatment instrument;
Preferably, the power of described plasma surface treatment instrument is 50-150W;
Preferably, the time of described oxygen plasma treatment is 0.5-5min.
5. the method according to claim 3 or 4, is characterized in that, step (2) described electron beam lithography is specially: first spin coating electronic corrosion-resistant on substrate after surface treatment, then develops with electron beam exposure electronic corrosion-resistant;
Preferably, described electronic corrosion-resistant is negative electronic erosion-resisting agent;
Preferably, the thickness of the electronic corrosion-resistant after spin coating is 30-300nm;
Preferably, the beam spot size of described electron beam is 0.5-10nm;
Preferably, the developer solution that described development uses is acetone, any one in acetone soln, sodium hydroxide solution, methyl iso-butyl ketone (MIBK) or methyl isobutyl ketone solution;
Preferably, the time of described development is 0.5-5min.
6. according to the method one of claim 3-5 Suo Shu, it is characterized in that, step (3) adopts hot evaporation, electron beam evaporation plating or magnetron sputtering deposition thing to be deposited;
Preferably, the speed of step (3) described deposition is
Preferably, the described sedimental thickness of step (3) is 1-100nm;
Preferably, the described thing to be deposited of step (3) is metal, metal oxide or the combination except any one or at least two kinds in the semi-conducting material of burning beyond the region of objective existence;
Preferably, step (3) described metal is the combination of any one or at least two kinds in gold, platinum, silver, copper, chromium, aluminium, nickel, titanium, germanium, niobium or tantalum;
Preferably, step (3) described metal oxide is the combination of any one or at least two kinds in titanium oxide, zinc oxide, aluminium oxide, cadmium oxide, indium oxide;
Preferably, the described semi-conducting material except burning beyond the region of objective existence of step (3) is the combination of any one or at least two kinds in niobium nitride, titanium nitride, zirconium nitride, GaAs, indium phosphide, gallium nitride.
7. according to the method one of claim 3-6 Suo Shu, it is characterized in that, step (3) adopts acetone, sodium hydroxide solution or hydrofluoric acid solution to peel off deposit;
Preferably, the time of step (3) described stripping is 1-10min.
8. according to the method one of claim 3-7 Suo Shu, it is characterized in that, step (3) described post processing is: remove the electronic corrosion-resistant remained on deposit;
Preferably, etching method is used to remove electronic corrosion-resistant;
Preferably, the etching gas that uses of described etching method be fluoroform and argon gas mist or oxygen;
Preferably, the time of described etching is 5s-5min;
Preferably, the speed of described etching is 50-500nm/min.
9. according to the method one of claim 3-8 Suo Shu, it is characterized in that, described method comprises the steps:
(1) RCA standard cleaning method and oxygen plasma treatment is adopted to carry out surface treatment to substrate;
(2) negative electronic erosion-resisting agent that substrate surface spin coating 30-300nm is after surface treatment thick, be the electron beam exposure negative electronic erosion-resisting agent of 0.5-10nm with beam spot size afterwards and develop, the time of development is 0.5-5min, obtains nano-structure array pattern;
(3) on nano-structure array pattern with
deposition rate thickness be the thing to be deposited of 1-100nm, peel off deposit, obtain overburden;
(4) remove negative electronic erosion-resisting agent residual on overburden with the speed of 50-500nm/min etching, the time of etching is 5s-5min, obtains the nano-structure array that live width is 3-15nm.
10. the purposes of nano-structure array according to claim 1 or 2, it is for chip, biology and chemical sensitisation, nanocomposite optical or plasma resonance field.
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| CN107275168A (en) * | 2017-06-06 | 2017-10-20 | 东南大学 | A kind of novel nano structure photocathode based on titanium nitride |
| CN108375567A (en) * | 2018-02-24 | 2018-08-07 | 国家纳米科学中心 | A kind of surface-enhanced Raman substrate and preparation method thereof |
| CN108396290A (en) * | 2018-02-24 | 2018-08-14 | 国家纳米科学中心 | A kind of TiZn alloy films and its preparation method and application |
| CN109161849A (en) * | 2018-07-19 | 2019-01-08 | 西安交通大学 | A kind of ordered porous array and preparation method thereof of silver tantalum composite material building |
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| CN106770180A (en) * | 2017-02-23 | 2017-05-31 | 国家纳米科学中心 | A kind of surface-enhanced Raman substrate and preparation method thereof |
| CN106770180B (en) * | 2017-02-23 | 2019-10-11 | 国家纳米科学中心 | A kind of preparation method of surface-enhanced Raman substrate |
| CN107275168A (en) * | 2017-06-06 | 2017-10-20 | 东南大学 | A kind of novel nano structure photocathode based on titanium nitride |
| CN107275168B (en) * | 2017-06-06 | 2019-03-29 | 东南大学 | A kind of novel nano structure photocathode based on titanium nitride |
| CN108396290B (en) * | 2018-02-24 | 2020-04-24 | 国家纳米科学中心 | TiZn alloy film and preparation method and application thereof |
| CN108375567A (en) * | 2018-02-24 | 2018-08-07 | 国家纳米科学中心 | A kind of surface-enhanced Raman substrate and preparation method thereof |
| CN108396290A (en) * | 2018-02-24 | 2018-08-14 | 国家纳米科学中心 | A kind of TiZn alloy films and its preparation method and application |
| CN109161849A (en) * | 2018-07-19 | 2019-01-08 | 西安交通大学 | A kind of ordered porous array and preparation method thereof of silver tantalum composite material building |
| CN109698257A (en) * | 2019-01-10 | 2019-04-30 | 平顶山学院 | A kind of preparation method of nano-tube/CdS/Si hetero-junctions |
| CN109698257B (en) * | 2019-01-10 | 2021-05-28 | 平顶山学院 | Preparation method of nano CdS/Si heterojunction |
| CN111217319A (en) * | 2019-11-20 | 2020-06-02 | 西南交通大学 | Preparation method of one-dimensional ZnO nano heterojunction array |
| CN111217319B (en) * | 2019-11-20 | 2023-04-11 | 西南交通大学 | Preparation method of one-dimensional ZnO nano heterojunction array |
| CN111439720A (en) * | 2020-03-13 | 2020-07-24 | 中国科学院物理研究所 | Method for preparing reducing nano structure |
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