CN105271103B - Nano-structure array and preparation method and application thereof - Google Patents
Nano-structure array and preparation method and application thereof Download PDFInfo
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Abstract
The invention provides a nano-structure array and a preparation method and application thereof, wherein the area of the nano-structure array is 100-250000 mu m2The line width of the nano array is 3-15 nm; the preparation method of the nanostructure array comprises the following steps: carrying out surface treatment on the substrate; preparing a nanostructure array pattern on a substrate by adopting an electron beam exposure technology; and depositing a to-be-deposited substance on the nanostructure array pattern, stripping the to-be-deposited substance, and performing post-treatment on the to-be-deposited substance to obtain the nanostructure array. The preparation method has good controllability and repeatability, the prepared nano structure has uniform size, the area reaches submillimeter level, and the method is suitable for various materials; the substrate for preparing the nano-structure array can be repeatedly used, and standardization and quantification research is easy to develop; the device using the nanostructure array can be promoted to develop towards the direction of smaller size, larger area and more stable process, and can be widely applied to the fields of chips, biological and chemical sensing, nano-optics, plasma resonance and the like.
Description
Technical Field
The invention belongs to the technical field of nano materials, relates to a nano structure array and a preparation method and application thereof, and particularly relates to a sub-millimeter area near-limit size nano structure array and a preparation method and application thereof.
Background
Nanomaterials, with further reduction in size, are likely to produce new phenomena, exhibiting new properties and performance. For example, plasmon resonance has been found to enhance the effect of several orders of magnitude in gold nanostructures with sub-10 nm gaps. Therefore, the near-ultimate-size nano structure has wide application prospects in the fields of various chip information technologies, biological and chemical sensors, nano optics, plasma resonance and the like.
At present, there are two main methods for fabricating near-ultimate size nanostructures: bottom-up chemical synthesis methods, such as self-assembly techniques; and a top-down nano-fabrication method. Chemical synthesis methods for making nanostructures generally refer to the synthesis of nanoparticles in solution, where interactions between the nanoparticles form a near-critical size of the nanogap. The nano-processing technology is to realize the processing of nano-precision by using the technologies of electron beam exposure, etching, film coating and the like, namely to realize the removal, the relocation and the recombination of atoms and molecules on the surface of a material. Compared with a chemical synthesis method, the nano-structure with the near-limit size manufactured by utilizing the nano-processing technology has the following advantages: the size of the nano structure is uniform and controllable; the nano structure is designed flexibly and adjustably; the nano-processing technology is suitable for processing and preparing various metal and non-metal materials and the like; the manufactured nano-structure substrate can be repeatedly used, and is convenient for long-term storage; easy to carry out standardization and quantification research, etc.
For example, CN 101486439a discloses a germanium nanodot/silicon nanowire array structure thin film and a preparation method thereof, wherein the germanium nanodot/silicon nanowire array structure thin film mainly consists of a silicon nanowire array and germanium nanodots, and the germanium nanodots are distributed on the silicon nanowires of the silicon nanowire array; the preparation method mainly comprises the following steps: p-type or N-type monocrystalline silicon and polycrystalline silicon are used as raw materials; preparing a large-area silicon nanowire array by using an etching method; and then preparing germanium points on the large-area silicon nanowire array substrate by using a low-pressure chemical vapor deposition technology and using germane as a gas source. CN 102110597a discloses a method for realizing sub-10 nm gate length lines: depositing a medium layer on a substrate or thermally oxidizing a growth medium layer, depositing a gate electrode material, exposing and etching a groove by positive electron beams, depositing an oxide medium layer, flattening the surface of the oxide medium layer, exposing and etching the groove by positive electron beams, etching the gate electrode material and the like.
Because there are many technical difficulties in preparing near-ultimate size nanostructures with controllable morphology and size, a method for preparing large-area near-ultimate size nanostructures has not been reported. The fabrication of the ultimate size nanostructure not only needs to solve many key technologies in the nano-fabrication process, but also needs to understand and clarify the basic principles of various complex physicochemical actions and the like in the processing processes of electron beam exposure, etching, coating and the like. The smaller the process size, the more sensitive and less controllable the parameters of the various processes. Therefore, it is difficult to develop the critical dimension processing technology completely according to the conventional process thought and method, and the most critical parameters influencing and controlling the dimension and the processing quality in each processing process under the critical dimension must be firstly ascertained, so that the development of the critical dimension processing technology into the stable processing technology is possible. Therefore, the invention accurately controls the process technologies of electron beam exposure, film coating, stripping, etching and the like according to the basic idea, thereby realizing the processing and preparation of the nano structure array with larger area and near-limit size.
Disclosure of Invention
The invention aims to provide a nano-structure array, a preparation method and application thereof, wherein the nano-structure array has uniform nano-structure size, sub-millimeter array area and various material types, and can be widely applied to the technical fields of chips, biological and chemical sensing, nano-optics and plasma resonance.
In order to achieve the purpose, the invention adopts the following technical scheme:
a nano-structure array, the area of the nano-structure array is 100-250000 μm2The line width of the nano structure array is 3-15 nm.
The nanostructure array is a submillimeter area near-limit size nanostructure array. The area of the nano structure array is 100-250000 mu m2E.g. 200 μm2、500μm2、1000μm2、5000μm2、10000μm2、50000μm2、100000μm2、150000μm2、200000μm2Or 240000 μm2Etc. the line width of the nanostructure array is 3-15nm, such as 3nm, 4nm, 5nm, 8nm, 10nm, 12nm, or 14nm, etc., and the line width of the nanostructure array refers to the width of the linear nanostructure trench.
The nanostructure array can be a two-dimensional structure array or a three-dimensional structure array.
The thickness of the nanostructure array is 1-100nm, such as 2nm, 5nm, 10nm, 20nm, 30nm, 50nm, 70nm, 80nm or 90 nm.
Preferably, the constituent substances of the nanostructure array are any one or a combination of at least two of metals, metal oxides, or semiconductor materials other than metal oxides, typical but not limiting combinations are: metal and metal oxide, metal oxide and semiconductor material, metal oxide and semiconductor material. The constituent material of the nanostructure array is not limited to metal, metal oxide or semiconductor material, and those skilled in the art can select an appropriate constituent material according to actual needs.
Preferably, the metal is any one or a combination of at least two of gold, platinum, silver, copper, chromium, aluminum, nickel, titanium, germanium, niobium, or tantalum, with a typical but non-limiting combination being: gold and platinum, silver, copper and chromium, platinum, silver and copper, chromium, aluminum, nickel, titanium and germanium, aluminum, nickel, titanium, germanium, niobium and tantalum.
Preferably, the metal oxide is any one of titanium oxide, zinc oxide, aluminum oxide, cadmium oxide, indium oxide or a combination of at least two of them, and a typical but non-limiting metal oxide combination is: titanium oxide and zinc oxide, aluminum oxide, cadmium oxide and indium oxide, aluminum oxide and cadmium oxide, zinc oxide, aluminum oxide and cadmium oxide.
Preferably, the semiconductor material other than the metal oxide is any one of niobium nitride, titanium nitride, zirconium nitride, gallium arsenide, indium phosphide, gallium nitride, or a combination of at least two thereof, and a typical but non-limiting combination of semiconductor materials may be: titanium nitride and zirconium nitride, niobium nitride, gallium arsenide and indium phosphide, indium phosphide and gallium nitride, gallium arsenide, indium phosphide and gallium nitride.
The invention also provides a preparation method of the nano-structure array, which comprises the following steps:
(1) carrying out surface treatment on the substrate;
(2) preparing a nanostructure array pattern on a substrate by adopting an electron beam exposure technology;
(3) and depositing a to-be-deposited substance on the nanostructure array pattern, stripping the deposited substance, and performing post-treatment on the deposited substance to obtain the nanostructure array.
The nanostructure array provided by the invention is obtained by preparing a nanostructure array pattern on a substrate by adopting an electron beam exposure method, depositing a deposit to be deposited on the nanostructure array pattern, stripping the deposit and carrying out post-treatment.
The substrate in the step (1) is silicon, quartz or SOI (silicon on insulator substrate). The substrate is not limited to these three materials, and those skilled in the art can select different substrates according to actual situations.
Preferably, the surface treatment of step (1) is: the substrate was cleaned using an RCA standard clean and the surface of the substrate was treated with oxygen plasma.
Preferably, the oxygen plasma treatment is performed on a plasma surface treating apparatus. Since the substrate is used for preparing the nanostructure array, the condition of the surface of the substrate will affect the morphology of the prepared product, and thus the treatment of the surface of the substrate is very important.
Preferably, the power of the plasma surface treatment apparatus is 50-150W, such as 55W, 60W, 70W, 80W, 100W, 120W, 130W or 140W.
Preferably, the oxygen plasma treatment time is 0.5-5min, such as 1min, 1.5min, 2min, 2.5min, 3min, 3.5min, 4min or 4.5 min.
The electron beam exposure technology in the step (2) is specifically as follows: the surface-treated substrate is spin-coated with an electron resist, and then the electron resist is exposed by an electron beam and developed.
Preferably, the electronic resist may be a positive electronic resist and/or a negative electronic resist, preferably a negative electronic resist. The exposure sensitivity of the negative electron resist is much higher than that of the positive electron resist.
Preferably, the thickness of the spin-coated electronic resist is 30-300nm, such as 30nm, 50nm, 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, and the like.
Preferably, the electron beam has a spot size of 0.5-10nm, such as 1nm, 1.5nm, 2nm, 3nm, 4nm, 5nm, 6nm, 8nm, or 9nm, etc.
The smaller the process size, the more sensitive and less controllable the parameters of the various processes. The type of the electronic resist, the spin coating thickness and the beam spot size of the electron beam have great influence on the preparation of the nanostructure array, and the preset nanostructure array can be obtained only by matching the parameters.
Preferably, the developing solution used for the development is any one of acetone, an acetone solution, a sodium hydroxide solution, methyl isobutyl ketone or a methyl isobutyl ketone solution.
Preferably, the development time is 0.5-5min, such as 1min, 2min, 3min or 4 min.
And (3) depositing the to-be-deposited material by adopting thermal evaporation, electron beam evaporation or magnetron sputtering.
Preferably, the deposition rate of step (3) is
Such as
Or
And the like.
Preferably, the thickness of the deposit in step (3) is 1-100nm, such as 2nm, 5nm, 10nm, 20nm, 30nm, 50nm, 70nm, 80nm or 90 nm.
Preferably, the deposit to be deposited in step (3) is any one of metal, metal oxide or semiconductor material except metal oxide or a combination of at least two of the following, typical but not limiting combinations are: metal and metal oxide, metal oxide and semiconductor material, metal oxide and semiconductor material.
Preferably, the metal is any one or a combination of at least two of gold, platinum, silver, copper, chromium, aluminum, nickel, titanium, germanium, niobium, or tantalum, with a typical but non-limiting combination being: gold and platinum, silver, copper and chromium, platinum, silver and copper, chromium, aluminum, nickel, titanium and germanium, aluminum, nickel, titanium, germanium, niobium and tantalum.
Preferably, the metal oxide is any one of titanium oxide, zinc oxide, aluminum oxide, cadmium oxide, indium oxide or a combination of at least two of them, and a typical but non-limiting metal oxide combination is: titanium oxide and zinc oxide, aluminum oxide, cadmium oxide and indium oxide, aluminum oxide and cadmium oxide, zinc oxide, aluminum oxide and cadmium oxide.
Preferably, the semiconductor material other than the metal oxide is any one of titanium nitride, zirconium nitride, gallium arsenide, indium phosphide, gallium nitride or a combination of at least two of them, and a typical but non-limiting semiconductor material combination may be: titanium nitride and zirconium nitride, gallium arsenide and indium phosphide, indium phosphide and gallium nitride, gallium arsenide, indium phosphide and gallium nitride.
And (3) stripping the deposit by using acetone, sodium hydroxide solution or hydrofluoric acid solution.
Preferably, the peeling time in step (3) is 1-10min, such as 2min, 3min, 4min, 5min, 6min, 7min, 8min or 9 min.
Preferably, the post-treatment of step (3) is: the electronic resist remaining on the deposits is removed.
The electronic resist remaining on the deposits can be removed by various methods, preferably by etching.
Preferably, the etching method uses an etching gas of trifluoromethane (CHF)3) Mixed with argon or oxygen.
Preferably, the etching time is 5s-5min, such as 10s, 20s, 30s, 50s, 1min, 2min, 3min, 4min or 4.5 min.
Preferably, the etching rate is 50-500nm/min, such as 60nm/min, 80nm/min, 100nm/min, 200nm/min, 300nm/min, 400nm/min or 450 nm/min.
As a preferred technical scheme, the preparation method comprises the following steps:
(1) carrying out surface treatment on the substrate by adopting an RCA standard cleaning method and oxygen plasma treatment;
(2) spin-coating a negative electronic resist with the thickness of 30-300nm on the surface of the substrate after surface treatment, then exposing the negative electronic resist by using an electron beam with the beam spot size of 0.5-10nm and developing for 0.5-5min to obtain a nano-structure array pattern;
(3) on the nanostructure array pattern
Depositing the deposit to be deposited with the thickness of 1-100nm at the speed of (1), and stripping the deposit to obtain a stripped object;
(4) and etching and removing the residual negative electronic resist on the stripping material at the speed of 50-500nm/min for 5s-5min to obtain the nano-structure array with the line width of 3-15 nm.
The nanostructure array provided by the invention is a submillimeter-area near-limit-size nanostructure array, electron beams are adopted to expose an electronic resist to form a near-limit-size electronic resist nanostructure array pattern, the pattern is developed and then deposited to be deposited, then stripped and etched with the residual electronic resist, and finally the near-limit characteristic-size (sub-10 nm) nanostructure array is prepared.
The invention also provides the application of the nanostructure array, which is applied to the fields of chips, biological and chemical sensing, nano optics or plasma resonance.
Compared with the prior art, the invention has the beneficial effects that:
the preparation method of the submillimeter-area near-limit-size nano-structure array provided by the invention has good controllability and repeatability, the prepared nano-structure has uniform size, the area reaches submillimeter level, and the preparation method is suitable for various materials; the substrate for preparing the nano-structure array can be repeatedly used, and the standardization and quantification research is easy to develop.
The submillimeter-area near-limit-size nano-structure array provided by the invention can promote the development of devices using the nano-structure array towards the direction of smaller size, larger area and more stable process, and can be widely applied to the fields of chip information technology, biological and chemical sensing, nano-optics, plasma resonance technology and the like.
Drawings
Fig. 1 is a scanning electron micrograph of a nanostructure array pattern provided in example 1. Wherein (a) is a triangular nano-array pattern; (b) a quadrilateral nano array pattern; (c) in a hexagonal nano-array pattern.
Fig. 2 is a scanning electron microscope image of the gold nanostructure array provided in example 1. Wherein (a) is a triangular nanostructure array; (b) is a quadrilateral nanostructure array; (c) is a hexagonal nanostructure array.
Fig. 3 is a scanning electron microscope image of the gold nanostructure array provided in example 2. Wherein (a) is a triangular nanostructure array; (b) is a quadrilateral nanostructure array; (c) is a hexagonal nanostructure array.
Fig. 4 is a scanning electron micrograph of the copper nanostructure array provided in example 3. Wherein (a) is a triangular nanostructure array; (b) is a quadrilateral nanostructure array; (c) is a hexagonal nanostructure array.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Example 1:
the preparation method of the gold nanostructure array comprises the following steps:
(1) cleaning the silicon (100) substrate by adopting an RCA standard cleaning method, and treating the silicon (100) substrate for 2min by adopting an oxygen plasma surface treatment instrument with the power of 60W;
(2) spin coating negative electrode with thickness of 100nm on three substratesThe sub-resist is prepared by exposing electron resist with electron beam having beam spot diameter of 1nm, wherein the electron beam exposure system is connected with pattern generator, and the exposure dose of the electron beam is adjusted to 60000 μ C/cm2、80000μC/cm2And 100000. mu.C/cm2Obtaining triangular, quadrangular and hexagonal nano array patterns (as shown in figure 1), wherein the size of the nano array patterns is 100 mu m multiplied by 100 mu m, and the line widths of the triangular, quadrangular and hexagonal nano array patterns are respectively 5.8nm, 8.7nm and 8.7 nm; developing the obtained triangular, quadrilateral and hexagonal nano array patterns for 4min by using a NaOH solution with the mass percentage of 1%, then washing for 2min by using pure water, then respectively soaking the substrate for 10min by using ethanol with the mass percentage of 30%, 50%, 70%, 85% and 95%, soaking the substrate for two times by using absolute ethanol, wherein each time is 10min, and finally drying the substrate by using a critical point dryer;
(3) evaporating chromium with a thickness of 2nm on the nano-array pattern by adopting an electron beam evaporation process, and then evaporating gold with a thickness of 20nm on the chromium, wherein the deposition rates of the chromium and the gold are respectively
And
ultrasonically stripping the substrate after metal deposition in a BOE solution for 8 min;
(4) with CHF3Etching the residual negative electron etchant on the gold for 1min by using etching gas to obtain triangular, quadrangular and hexagonal gold nanostructure arrays (as shown in FIG. 2).
Example 2:
the preparation method of the gold nanostructure array comprises the following steps:
the thickness of the negative electron resist is 80nm, the beam spot diameter of the electron beam is 0.5nm, and the exposure dose of the electron beam is 60000 μ C/cm2The size of the obtained nano array pattern is 150 micrometers multiplied by 150 micrometers; washing the developed substrate with pure water for 2min, washing with isopropanol for 1min, and finally blowing with high-purity nitrogen; depositing 20nm thick gold on the nanostructure array pattern at a deposition rate of gold
Otherwise, the same procedure as in example 1 was repeated. The obtained gold nanostructure array is shown in fig. 3, and the line widths of the triangular, quadrangular and hexagonal nano arrays are respectively 8.7nm, 5.8nm and 9.8nm through measurement.
Example 3:
the preparation method of the copper nanostructure array comprises the following steps:
except that the size of the nano-structure array pattern is 150 mu m multiplied by 150 mu m, chromium with the thickness of 8nm is firstly deposited and copper with the thickness of 15nm is then deposited in the electron beam evaporation process, and the deposition rates of the chromium and the copper are respectively
And
otherwise, the same procedure as in example 1 was repeated. The obtained copper nanostructure array is shown in fig. 4, and the line widths of the triangular, quadrangular and hexagonal nano arrays are respectively 5.8nm, 8.7nm and 11.7nm through measurement.
Example 4:
the preparation method of the niobium nitride nano-structure array comprises the following steps:
the exposure dose was 100000. mu.C/cm except for the electron beam2(ii) a Depositing 20nm thick niobium nitride on the nanostructure array pattern by magnetron sputtering at a deposition rate of
Ultrasonically stripping niobium nitride by using acetone for 4 min; the same procedure as in example 1 was repeated except that the negative electron etchant remained on the delaminated niobium nitride was etched with oxygen as the etching gas for 15 seconds.
Example 5:
the preparation method of the alumina nano-structure array comprises the following steps:
(1) cleaning the substrate by adopting an RCA standard cleaning method, and performing oxygen plasma surface treatment on the substrate by using a plasma surface treatment instrument with the power of 50W for 5 min;
(2) spin-coating a negative electronic resist with the thickness of 30nm on the surface of the substrate, then exposing the negative electronic resist by using an electron beam with the beam spot size of 0.5nm and developing, wherein the developing solvent is acetone, the developing time is 0.5min, washing the developed substrate by using pure water for 2min, then washing by using isopropanol for 1min, and finally drying by using high-purity nitrogen to obtain a triangular nano array pattern;
(3) the thermal evaporation process is adopted to form a triangular nano array pattern
The thickness of the deposited alumina is 10nm, the deposited alumina is stripped, the solvent used for stripping is acetone, and the stripping time is 1 min;
(4) etching at a speed of 50nm/min for 5s to remove the residual negative electron resist on the alumina, wherein the etching gas is oxygen, and the alumina triangular nanostructure array with the line width of 3nm is obtained, and the area of the alumina triangular nanostructure array is 100 μm2。
Example 6
The preparation method of the zirconium nitride nano-structure array comprises the following steps:
(1) cleaning the substrate by adopting an RCA standard cleaning method, and performing oxygen plasma surface treatment on the substrate by using a plasma surface treatment instrument with the power of 150W for 0.5 min;
(2) spin-coating a negative electronic resist with the thickness of 300nm on the surface of the substrate, then exposing the negative electronic resist by using an electron beam with the beam spot size of 10nm, developing by using a sodium hydroxide solution for 2min, washing the developed substrate by using pure water for 2min, then washing by using isopropanol for 1min, and finally drying by using high-purity nitrogen to obtain a quadrilateral nano array pattern;
(3) adopting magnetron sputtering technology to form a quadrilateral nano array pattern
Depositing zirconium nitride with a thickness of 100 nm; stripping the deposited zirconium nitride with hydrofluoric acid solution as solventThe time is 10 min;
(4) etching to remove the residual negative electronic resist on the zirconium nitride at a rate of 500nm/min for 5min, wherein the etching gas is trifluoromethane (CHF)3) And argon to obtain a zirconium nitride quadrilateral nanostructure array with the line width of 15nm, wherein the area of the zirconium nitride quadrilateral nanostructure array is 250000 mu m2。
Example 7
The preparation method of the titanium dioxide nano-structure array comprises the following steps:
(1) cleaning the substrate by adopting an RCA standard cleaning method, and performing oxygen plasma surface treatment on the substrate by using a plasma surface treatment instrument with the power of 100W for 2 min;
(2) spin-coating a positive electronic resist with the thickness of 100nm on the surface of a substrate, then exposing the positive electronic resist by using an electron beam with the beam spot size of 5nm and developing, wherein a solvent used for developing is a mixed solution of methyl isobutyl ketone and acetone, the developing time is 2min, washing the developed substrate for 2min by using pure water, then washing for 1min by using isopropanol, and finally drying by using high-purity nitrogen to obtain a hexagonal nano array pattern;
(3) using electron beam evaporation process to form a pentagonal nano-array pattern
Depositing titanium dioxide with a thickness of 30 nm; stripping the deposited titanium dioxide with acetone for 5 min;
(4) etching at a rate of 100nm/min to remove the residual negative electronic resist on the titanium dioxide for 1min, wherein the etching gas is oxygen, and a titanium dioxide hexagonal nanostructure array with a line width of 10nm is obtained, and the area of the titanium dioxide nanostructure array is 100000 mu m2。
The applicant declares that the above description is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and it should be understood by those skilled in the art that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are within the scope and disclosure of the present invention.
Claims (33)
1. A nanostructure array, characterized in that the area of the nanostructure array is 100000-250000 μm2The line width of the nano structure array is 3-8 nm;
the preparation method of the nanostructure array comprises the following steps:
(1) carrying out surface treatment on the substrate;
(2) preparing a nanostructure array pattern on a substrate by adopting an electron beam exposure technology;
(3) depositing a deposition to be deposited on the nanostructure array pattern at a rate of
Stripping the deposit and carrying out post-treatment on the deposit to obtain a nano-structure array;
wherein the surface treatment in the step (1) is as follows: the substrate was cleaned using an RCA standard clean and the surface of the substrate was treated with oxygen plasma.
2. The nanostructure array of claim 1, wherein the nanostructure array has a thickness of 1-100 nm.
3. The nanostructure array of claim 1, wherein the constituent materials of the nanostructure array are any one or a combination of at least two of metals, metal oxides, or semiconductor materials other than metal oxides.
4. The nanostructure array of claim 3, wherein the metal is any one or a combination of at least two of gold, platinum, silver, copper, chromium, aluminum, nickel, titanium, germanium, niobium, or tantalum.
5. The nanostructure array of claim 3, wherein the metal oxide is any one of titanium oxide, zinc oxide, aluminum oxide, cadmium oxide, indium oxide, or a combination of at least two thereof.
6. The nanostructure array of claim 3, wherein the semiconductor material other than metal oxide is any one of niobium nitride, titanium nitride, zirconium nitride, gallium arsenide, indium phosphide, gallium nitride, or a combination of at least two thereof.
7. Method for the preparation of a nanostructure array according to any of claims 1 to 6, characterized in that it comprises the following steps:
(1) carrying out surface treatment on the substrate;
(2) preparing a nanostructure array pattern on a substrate by adopting an electron beam exposure technology;
(3) and depositing a to-be-deposited substance on the nanostructure array pattern, stripping the deposited substance, and performing post-treatment on the deposited substance to obtain the nanostructure array.
8. The method according to claim 7, wherein the substrate of step (1) is silicon, quartz or SOI.
9. The method according to claim 7, wherein the surface treatment of step (1) is: the substrate was cleaned using an RCA standard clean and the surface of the substrate was treated with oxygen plasma.
10. The production method according to claim 9, wherein the oxygen plasma treatment is performed on a plasma surface treatment apparatus.
11. The method according to claim 10, wherein the power of the plasma surface treatment apparatus is 50 to 150W.
12. The method of claim 9, wherein the oxygen plasma treatment time is 0.5 to 5 min.
13. The method according to claim 7, wherein the electron beam exposure technique of step (2) is specifically: the surface-treated substrate is spin-coated with an electron resist, and then the electron resist is exposed by an electron beam and developed.
14. The production method according to claim 13, wherein the electron resist is a negative electron resist.
15. The method according to claim 13, wherein the thickness of the spin-coated electronic resist is 30 to 300 nm.
16. The production method according to claim 13, wherein the electron beam has a beam spot size of 0.5 to 10 nm.
17. A producing method according to claim 13, wherein said developing solution used for development is any one of acetone, an acetone solution, a sodium hydroxide solution, methyl isobutyl ketone, or a methyl isobutyl ketone solution.
18. The production method according to claim 13, wherein the time for the development is 0.5 to 5 min.
19. The method according to claim 7, wherein step (3) deposits the deposit by thermal evaporation, electron beam evaporation or magnetron sputtering.
20. The method according to claim 7, wherein the thickness of the deposit in the step (3) is 1 to 100 nm.
21. The method according to claim 7, wherein the deposit to be deposited in step (3) is any one of a metal, a metal oxide or a semiconductor material other than a metal oxide or a combination of at least two of the above.
22. The method according to claim 21, wherein the metal in step (3) is any one or a combination of at least two of gold, platinum, silver, copper, chromium, aluminum, nickel, titanium, germanium, niobium, or tantalum.
23. The method according to claim 21, wherein the metal oxide in step (3) is any one of titanium oxide, zinc oxide, aluminum oxide, cadmium oxide, and indium oxide, or a combination of at least two thereof.
24. The method according to claim 21, wherein the semiconductor material other than the metal oxide in step (3) is any one of niobium nitride, titanium nitride, zirconium nitride, gallium arsenide, indium phosphide, gallium nitride, or a combination of at least two of them.
25. The method of claim 7, wherein step (3) strips the deposit with acetone, sodium hydroxide solution, or hydrofluoric acid solution.
26. The production method according to claim 7, wherein the peeling time in the step (3) is 1 to 10 min.
27. The method of claim 7, wherein the post-processing of step (3) is: the electronic resist remaining on the deposits is removed.
28. The production method according to claim 27, wherein the electronic resist is removed using an etching method.
29. The method according to claim 28, wherein the etching gas used in the etching method is a mixed gas of trifluoromethane and argon or oxygen.
30. The method of claim 28, wherein the etching time is 5s-5 min.
31. The method of claim 28, wherein the etching is performed at a rate of 50-500 nm/min.
32. The method according to claim 7, characterized in that it comprises the steps of:
(1) carrying out surface treatment on the substrate by adopting an RCA standard cleaning method and oxygen plasma treatment;
(2) spin-coating a negative electronic resist with the thickness of 30-300nm on the surface of the substrate after surface treatment, then exposing the negative electronic resist by using an electron beam with the beam spot size of 0.5-10nm and developing for 0.5-5min to obtain a nano-structure array pattern;
(3) on the nanostructure array pattern
Depositing the deposit to be deposited with the thickness of 1-100nm at the speed of (1), and stripping the deposit to obtain a stripped object;
(4) and etching and removing the residual negative electronic resist on the stripping material at the speed of 50-500nm/min for 5s-5min to obtain the nano-structure array with the line width of 3-8 nm.
33. Use of the nanostructure array according to any one of claims 1 to 6 in the fields of chips, biological and chemical sensing, nano-optics or plasmon resonance.
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| "Direct and Reliable Patterning of Plasmonic Nanostructures with Sub-10-nm Gaps";Huigao Duan, et al.;《ACS Nano》;20110816;第5卷(第9期);第7593页第1段至7596页第1段，正文"METHODS"部分，附图1-2、4 * |
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