CN110993487A - Preparation method and application of sub-10 nanometer gap structure - Google Patents

Preparation method and application of sub-10 nanometer gap structure Download PDF

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Publication number
CN110993487A
CN110993487A CN201911157348.0A CN201911157348A CN110993487A CN 110993487 A CN110993487 A CN 110993487A CN 201911157348 A CN201911157348 A CN 201911157348A CN 110993487 A CN110993487 A CN 110993487A
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electron beam
sub
gap structure
pattern
preparation
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胡海峰
褚卫国
董凤良
闫兰琴
陈佩佩
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National Center for Nanosccience and Technology China
Beijing Institute of Nanoenergy and Nanosystems
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Beijing Institute of Nanoenergy and Nanosystems
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Priority to CN201911157348.0A priority Critical patent/CN110993487A/en
Publication of CN110993487A publication Critical patent/CN110993487A/en
Priority to CN202011099220.6A priority patent/CN112086345B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0277—Electrolithographic processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

The invention provides a preparation method and application of a sub-10 nanometer gap structure, which comprises the following steps: (1) designing an overlapped pattern of the opposite-vertex structure as a mask pattern; (2) and (3) exposing the electron beam glue according to the pattern designed in the step (1) by using an electron beam, and developing and fixing to obtain the sub-10 nanometer gap structure. The preparation method provided by the invention can overcome the underexposure problem when the vertex angle of the designed opposite vertex structure is less than 40 degrees, and successfully prepare the sub-10 nanometer gap structure.

Description

Preparation method and application of sub-10 nanometer gap structure
Technical Field
The invention belongs to the technical field of nano processing, and relates to a preparation method and application of a sub-10 nanometer gap structure.
Background
Electrons have particle property and volatility simultaneously, and in a nanoscale component, the electron transmission process can interfere like light waves, so that the energy dissipation is very little, and the electronic phase information can be stored and transmitted, and the electronic phase component is an ideal information processing element. Nanoelectronic devices, i.e. phase electronic devices, are therefore a necessary consequence of further miniaturization of microelectronic devices. In the manufacture of nano electronic devices, the manufacture of nano counter electrodes with small size, good conductivity and nano-scale gaps is a key and difficult point.
Two-dimensional metal or other material structures with the characteristic dimension of sub-10 nanometers can highly localize an electromagnetic field, generally show physical phenomena such as plasma enhancement, charge tunneling, coulomb blockage, a rattan effect and the like, and are widely concerned in the aspects of foundations and application researches of plasmon devices, enhanced sensing detection, single photon sources/detection, single molecule/single particle quantum devices and the like.
Currently, electron beam exposure is the most direct and effective means for preparing such nanostructures, and although there are disadvantages in terms of complexity of operation and time cost, it is still one of the effective methods in current nanostructure preparation technology. On one hand, the technology does not need a mask, and can process the structure of a pattern with any shape through software design; on the other hand, the nano pattern can be directly prepared and can be subjected to multiple times of alignment. Although the electron beam lithography has a high resolution, there is a great technical difficulty in directly fabricating a sub-10 nm gap due to its proximity effect.
CN101067719A discloses a method for constructing sub-10 nm gap and its array, which utilizes the proximity effect in the electron beam lithography technology to design two patterns to be continuous, and controls the gap of the two patterns to be sub-10 nm by controlling the etching energy of the electron beam and the pattern transfer. CN104465327A discloses a nano counter electrode and a method for making the same, comprising the steps of setting a substrate and setting a resist thereon, determining an exposure layout, wherein the exposure layout has a pattern for forming the nano counter electrode, is composed of two strip-shaped parts extending along a straight line and is in axisymmetric distribution, each strip-shaped part comprises a rectangle and a triangle, the short side of the rectangle coincides with one side of the triangle, the triangles of the two strip-shaped parts face each other, performing electron beam exposure, development and fixation on the resist according to the exposure layout to form an etching groove, depositing metal on the substrate with the etching groove, and dissolving the residual resist to obtain the nano counter electrode. In the above patent, the designed mask patterns have opposite vertical angles of 40 ° or more, and the sub-10 nm gap structure is fabricated using the electron beam proximity effect.
Contrary to the above phenomenon, when designing a vertex structure with a vertex angle of the mask pattern below 40 °, if the electron beam exposure is directly performed according to the above method, an underexposure phenomenon occurs in the middle region, resulting in a middle gap much larger than 10nm, and the sub-10 nm gap structure cannot be prepared. Therefore, how to realize the preparation of the sub-10 nm gap structure when the top angle of the mask pattern is less than 40 ° is a challenge and technical problem for the electron beam exposure technology.
Disclosure of Invention
The invention aims to provide a preparation method and application of a sub-10 nanometer gap structure. The preparation method provided by the invention can overcome the underexposure problem when the vertex angle of the designed opposite vertex structure is less than 40 degrees, and successfully prepare the sub-10 nanometer gap structure.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a method for preparing a sub-10 nm gap structure, comprising the following steps:
(1) designing an overlapped pattern of the opposite-vertex structure as a mask pattern;
(2) and (3) exposing the electron beam glue according to the pattern designed in the step (1) by using an electron beam, and developing and fixing to obtain the sub-10 nanometer gap structure.
The overlapped type figure according to the present invention means that two figures are partially overlapped and the opposite structure means a corner-to-corner type, and therefore, the overlapped type figure according to the present invention means that two figures are overlapped in a corner-to-corner type, and a corner of the overlapped portion is referred to as a vertex angle.
The pattern design of the present invention can be designed using the currently available GDSII software.
According to the invention, electron beams are utilized to expose electron beam glue according to a designed overlapped pattern, the range of underexposure of the central area of an overlapped area is reduced to the sub-10 nanometer size by utilizing the proximity effect of the electron beams, and then the sub-10 nanometer gap structure can be obtained by developing and fixing.
In the present invention, the vertex angle of the opposite vertex structure is 5 to 40 °, for example, 5 °, 10 °, 15 °, 20 °, 25 °, 30 °, 35 °, 40 °, and the like.
Preferably, the length of overlap is 300nm or less, such as 250nm, 220nm, 200nm, 150nm, 100nm, 80nm, 60nm, 50nm, 40nm, 30nm, 20nm, 10nm, 5nm, and the like.
The overlap length in the present invention refers to the horizontal distance between two corners of the overlap region.
Preferably, the electron beam glue is selected from Polymethylmethacrylate (PMMA) or polystyrene copolymer (ZEP).
Preferably, the thickness of the e-beam glue is 50-200nm, such as 60nm, 80nm, 100nm, 120nm, 140nm, 160nm, 180nm, etc.
The polystyrene copolymer of the present invention is preferably ZEP 520.
In the invention, the electron beam glue is polymethyl methacrylate, and the exposure dose of the electron beam is 600-900 mu C/cm2For example 620. mu.C/cm2、640μC/cm2、650μC/cm2、680μC/cm2、700μC/cm2、720μC/cm2、750μC/cm2、780μC/cm2、800μC/cm2、820μC/cm2、850μC/cm2、880μC/cm2And the like.
Preferably, the electron beam gel is polystyrene copolymer, and the exposure dose of the electron beam is 170-300 mu C/cm2E.g. 180. mu.C/cm2、200μC/cm2、220μC/cm2、250μC/cm2、240μC/cm2、260μC/cm2、280μC/cm2And the like.
In the invention, the beam current of the electron beam is 100-500 pA.
Preferably, the step size of the electron beam is 1-4 nm.
Preferably, the acceleration voltage of the electron beam is 100 kV.
The invention obtains the sub-10 nanometer gap structure by controlling the vertex angle degree, the overlapping length, the electron beam step length, the exposure dose and the like.
Exposing the electron beam resist using an electron beam is a conventional process in the prior art, and illustratively, the electron beam resist is spin-coated on a substrate material, dried, and exposed.
Preferably, the development and fixing times are each independently selected from 30-60s, such as 35s, 40s, 45s, 50s, 55s, and the like.
The development and fixing in the present invention are those conventionally used in semiconductor processes in the prior art, and the present invention is not described in detail, but only a few of them are exemplified in the form of specific examples in the detailed description.
In the present invention, the minimum line width dimension of the finally obtained sub-10-nm gap structure is 10nm or less, for example, 9nm, 8nm, 7nm, 6nm, 5nm, 4nm, 3nm, 2nm, 1nm, etc.
The preparation method of the invention can obtain the sub-10 nanometer gap structure without any other exposure dose correction and complex proximity effect dose correction algorithm, and is simple and easy to implement.
In a second aspect, the present invention provides the use of a method of preparation according to the first aspect for the preparation of a material or device having sub-10 nanostructures.
The invention can use the sub-10 nanometer structure obtained by the preparation method provided by the first aspect as a mask, and then use the subsequent conventional processing methods, such as sputtering, evaporation, deposition, etc., to prepare the related material or related device related to the sub-10 nanometer structure.
In a third aspect, the present invention provides a method for preparing a patterned two-dimensional material, wherein a mask used in the method is obtained by the method of the first aspect.
Preferably, the feature size of the pattern is sub-10 nm wide.
Specifically, the method comprises the step of processing the two-dimensional material by using a sub-10 nanometer patterned electron beam glue as a mask and using a chemical or physical method and the like to prepare the two-dimensional material structure with the characteristic dimension of sub-10 nanometer width on the surface of the two-dimensional material according to the preparation method of the first aspect.
In a fourth aspect, the present invention provides a method for producing a metal electrode, wherein a mask used in the production method is obtained by the production method of the first aspect.
Preferably, the metal electrode has a gap structure of 10nm or less.
Compared with the prior art, the invention has the following beneficial effects:
(1) according to the invention, electron beams are utilized to expose electron beam glue according to a designed overlapped pattern, the central area of an overlapped area is sufficiently exposed by utilizing the proximity effect of the electron beams, and then the sub-10 nanometer gap structure can be obtained through development and fixation;
(2) the preparation method provided by the invention can overcome the underexposure problem when the vertex angle of the designed opposite vertex structure is less than 40 degrees, and successfully prepare the sub-10 nanometer gap structure.
Drawings
FIG. 1 is a schematic diagram of an overlapping pattern of the opposite-vertex structures designed in example 1.
Fig. 2 is a schematic diagram of an overlapping pattern of the opposite-vertex structures designed in example 2.
Fig. 3 is a schematic diagram of an overlapping pattern of the opposite-vertex structures designed in example 3.
Fig. 4 is a schematic diagram of an overlapping pattern of the opposite-vertex structures designed in example 4.
Fig. 5 is a schematic diagram of an overlapping pattern of the opposite-vertex structure designed in comparative example 1.
Fig. 6 is a scanning electron micrograph of the metal electrode obtained in application example 1.
Fig. 7 is a scanning electron micrograph of the metal electrode obtained in application example 2.
Fig. 8 is a scanning electron micrograph of the metal electrode obtained in application example 3.
FIG. 9 is a scanning electron micrograph of a metal electrode obtained in application example 4.
Fig. 10 is a scanning electron micrograph of the metal electrode obtained in comparative application example 1.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments. It should be understood by those skilled in the art that the examples are only for the understanding of the present invention and should not be construed as the specific limitations of the present invention.
Example 1
A sub-10 nanometer gap structure is prepared by the following steps:
(1) the overlay pattern of the opposite-vertex structure shown in fig. 1 was designed using GDSII software, wherein the vertex angle was 5 ° and the overlay length was 200 nm.
(2) Soaking a silicon wafer by using acetone, isopropanol and deionized water, ultrasonically cleaning, drying by using nitrogen, then spin-coating a layer of PMMA glue with the thickness of 80nm, and baking on an oven at the baking temperature of 180 ℃ for 5 minutes.
(3) Exposing the substrate with electron beam at an accelerating voltage of 100kV and a beam current of 100pA with an exposure step of 1nm and an exposure dose of 700 uC/cm2。
(4) Developing in a mixed solution of methyl isobutyl pentanone and isopropanol (1:3) for 30s, fixing in an isopropanol liquid for 30s, and lightly drying by nitrogen to obtain the sub-10 nanometer gap structure mask.
Example 2
A sub-10 nanometer gap structure is prepared by the following steps:
(1) the overlay pattern of the opposite-vertex structure shown in fig. 2 was designed using GDSII software, wherein the vertex angle was 10 ° and the overlay length was 40 nm.
(2) Soaking a silicon wafer by using acetone, isopropanol and deionized water, ultrasonically cleaning, drying by using nitrogen, then spin-coating a layer of PMMA glue with the thickness of 80nm, and baking on an oven at the baking temperature of 180 ℃ for 5 minutes.
(3) Exposing the substrate with electron beam at an accelerating voltage of 100kV and a beam current of 100pA with an exposure step of 1nm and an exposure dose of 700 uC/cm2；
(4) Developing in a mixed solution of methyl isobutyl pentanone and isopropanol (1:3) for 30s, fixing in an isopropanol liquid for 30s, and lightly drying by nitrogen to obtain the sub-10 nanometer gap structure mask.
Example 3
A sub-10 nanometer gap structure is prepared by the following steps:
(1) the overlay pattern of the opposite-vertex structure shown in fig. 3 was designed using GDSII software, wherein the vertex angle was 30 ° and the overlay length was 16 nm.
(2) Soaking a silicon wafer by using acetone, isopropanol and deionized water, ultrasonically cleaning, drying by using nitrogen, then spin-coating a layer of PMMA glue with the thickness of 80nm, and baking on an oven at the baking temperature of 180 ℃ for 5 minutes.
(3) Exposing the substrate with electron beam at an accelerating voltage of 100kV and a beam current of 100pA with an exposure step of 1nm and an exposure dose of 700 uC/cm2；
(4) Developing in a mixed solution of methyl isobutyl pentanone and isopropanol (1:3) for 30s, fixing in an isopropanol liquid for 30s, and lightly drying by nitrogen to obtain the sub-10 nanometer gap structure mask.
Example 4
A sub-10 nanometer gap structure is prepared by the following steps:
(1) the overlay pattern of the opposite-vertex structure shown in fig. 4 was designed using GDSII software, wherein the vertex angle was 40 ° and the overlay length was 5 nm.
(2) Soaking a silicon wafer by using acetone, isopropanol and deionized water, ultrasonically cleaning, drying by using nitrogen, then spin-coating a layer of PMMA glue with the thickness of 80nm, and baking on an oven at the baking temperature of 180 ℃ for 5 minutes.
(3) Exposing the substrate with electron beam at an accelerating voltage of 100kV and a beam current of 100pA with an exposure step of 1nm and an exposure dose of 700 uC/cm2；
(4) Developing in a mixed solution of methyl isobutyl pentanone and isopropanol (1:3) for 30s, fixing in an isopropanol liquid for 30s, and lightly drying by nitrogen to obtain the sub-10 nanometer gap structure mask.
Comparative example 1
A sub-10 nanometer gap structure is prepared by the following steps:
(1) the opposite structure as shown in fig. 5 was designed using GDSII software, where the apex angle was 10 ° and the overlap length was 0 nm.
(2) The procedure of CN101067719A example 1 was followed to obtain an electron beam resist with a nanogap structure.
Application examples 1 to 4
A metal electrode is prepared by the following steps:
the electron beam glue with the sub-10 nanometer gap structure obtained in the examples 1-4 is used as a substrate, a layer of metal palladium with the thickness of 5nm is prepared by a vacuum coating method, then a sample is soaked in an acetone solution, ultrasonic treatment is carried out, and the electron beam glue is removed, so that a metal electrode is obtained.
The metal electrode of application example 1 had a 6nm gap structure, the metal electrode of application example 2 had a 5nm gap structure, the metal electrode of application example 3 had a 7nm gap structure, and the metal electrode of application example 4 had an 8nm gap structure.
Application examples 5 to 8
A patterned two-dimensional material prepared by the method of:
(1) a layer of graphene is prepared on the substrate by tearing the adhesive tape from the graphite sheet and transferring the graphene to the substrate, then a layer of PMMA adhesive with the thickness of 80nm is coated on the surface of the graphene, and the graphene is baked on an oven at the baking temperature of 180 ℃ for 5 minutes.
(2) An overlap pattern was designed according to examples 1 to 4, and electron beam exposure was carried out on the electron beam resist using an electron beam acceleration voltage of 100kV, a beam current of 100pA, an exposure step of 1nm, and an exposure dose of 700. mu.C/cm2Preparing a structural mask with gaps of sub-10 nanometers on the graphene;
(3) and removing the exposed graphene by means of oxygen reactive ion etching, finally soaking the graphene in an acetone solution, and heating to remove the electron beam glue to obtain the patterned graphene with the characteristic dimension of sub-10 nanometer width.
Comparative application example 1
The difference from application example 1 is that the electron beam paste obtained in example 1 was replaced with the electron beam paste obtained in comparative example 1.
And (3) performance testing:
the metal electrodes of application examples 1-4 and comparative application example 1 were characterized as follows:
(1) and (3) morphology characterization: observing the specific line width of the nano-gap structure by using a scanning electron microscope;
FIG. 6 is a scanning electron micrograph of the metal electrode obtained in application example 1, showing that the metal electrode has a 6nm gap structure; FIG. 7 is a scanning electron micrograph of the metal electrode obtained in application example 2, showing that the metal electrode has a 5nm gap structure; FIG. 8 is a scanning electron micrograph of the metal electrode obtained in application example 3, showing that the metal electrode has a 7nm gap structure; FIG. 9 is a scanning electron micrograph of a metal electrode obtained in application example 4, which shows that the metal electrode has a gap structure of 8 nm; FIG. 10 is a scanning electron micrograph of a metal electrode obtained in comparative application example 1, and it can be seen that the metal electrode has a 90nm gap structure.
As can be seen from performance tests, the preparation method of the invention can successfully prepare the sub-10 nanometer gap structure, and the designed pattern vertex angle is less than 40 degrees, so that the sub-10 nanometer gap structure can not be prepared by the preparation method in the prior art.
The applicant states that the present invention is illustrated by the above examples to describe the preparation method and application of the sub-10 nm gap structure of the present invention, but the present invention is not limited to the above process steps, i.e. it does not mean that the present invention must rely on the above process steps to be implemented. It will be apparent to those skilled in the art that any modification of the present invention, equivalent substitutions of selected materials and additions of auxiliary components, selection of specific modes and the like, which are within the scope and disclosure of the present invention, are contemplated by the present invention.

Claims (10)

1. A preparation method of a sub-10 nanometer gap structure is characterized by comprising the following steps:
(1) designing an overlapped pattern of the opposite-vertex structure as a mask pattern;
(2) and (3) exposing the electron beam glue according to the pattern designed in the step (1) by using an electron beam, and developing and fixing to obtain the sub-10 nanometer gap structure.
2. The method of claim 1, wherein the apex angle of the opposite-vertex structure is 5-40 °;
preferably, the length of the overlap is 300nm or less.
3. The method according to claim 1 or 2, wherein the electron beam glue is selected from the group consisting of polymethyl methacrylate or polystyrene copolymer;
preferably, the thickness of the electron beam glue is 50-200 nm.
4. The method as claimed in claim 3, wherein the electron beam glue is polymethyl methacrylate, and the exposure dose of the electron beam is 600-900 μ C/cm2；
Preferably, the electron beam gel is polystyrene copolymer, and the exposure dose of the electron beam is 170-300 mu C/cm2。
5. The method according to any one of claims 1-4, wherein the beam current of the electron beam is 100-500 pA;
preferably, the step size of the electron beam is 1-4 nm;
preferably, the acceleration voltage of the electron beam is 100 kV.
6. A production method according to any one of claims 1 to 5, wherein the time of development and fixing is each independently selected from 30 to 60 s.
7. The method of any one of claims 1-6, wherein the gap structure has a minimum line width dimension of 10nm or less.
8. Use of the preparation method according to any one of claims 1 to 7 for the preparation of a material or device having a sub-10 nanostructure.
9. A method for producing a patterned two-dimensional material, characterized in that a mask used in the production method is obtained by the production method according to any one of claims 1 to 7;
preferably, the feature size of the pattern is sub-10 nm wide.
10. A method for producing a metal electrode, characterized in that a mask used in the production method is obtained by the production method according to any one of claims 1 to 7;
preferably, the metal electrode has a gap structure of 10nm or less.
CN201911157348.0A 2019-11-22 2019-11-22 Preparation method and application of sub-10 nanometer gap structure Withdrawn CN110993487A (en)

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CN112051713A (en) * 2020-08-21 2020-12-08 国家纳米科学中心 Electron beam exposure and positioning method with sub-ten nanometer precision
CN114709280A (en) * 2022-03-28 2022-07-05 国家纳米科学中心 Photoelectric detector and preparation method thereof

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JP3487724B2 (en) * 1996-10-11 2004-01-19 沖電気工業株式会社 Method of forming tunnel junction
KR100565174B1 (en) * 2003-11-20 2006-03-30 한국전자통신연구원 Method for manufacturing nano-gap electrode device
CN101246817B (en) * 2008-02-29 2010-06-02 南京大学 Method for producing silicon quantum wire on insulating layer
JP2015077652A (en) * 2013-10-16 2015-04-23 クオンタムバイオシステムズ株式会社 Nano-gap electrode and method for manufacturing same
JP2017067446A (en) * 2014-04-28 2017-04-06 クオンタムバイオシステムズ株式会社 Method of manufacturing nano-gap electrode, side wall spacer and method of manufacturing side wall spacer

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CN112051713A (en) * 2020-08-21 2020-12-08 国家纳米科学中心 Electron beam exposure and positioning method with sub-ten nanometer precision
CN112051713B (en) * 2020-08-21 2022-11-15 国家纳米科学中心 Electron beam exposure and positioning method with sub-ten nanometer precision
CN114709280A (en) * 2022-03-28 2022-07-05 国家纳米科学中心 Photoelectric detector and preparation method thereof

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Application publication date: 20200410