CN105261395B - A kind of chip and its replacement comparison device - Google Patents
A kind of chip and its replacement comparison device Download PDFInfo
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- CN105261395B CN105261395B CN201510627972.8A CN201510627972A CN105261395B CN 105261395 B CN105261395 B CN 105261395B CN 201510627972 A CN201510627972 A CN 201510627972A CN 105261395 B CN105261395 B CN 105261395B
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Abstract
The embodiment of the invention provides a kind of chip and its replacement comparison devices, device includes: M replacement contrast circuit, each replacement contrast circuit has N number of contrast module, each replacement contrast circuit is connected with the main memory of the comparison reset signal circuit of chip, the input address output end of chip, N number of replacement unit of chip and chip respectively, and N number of replacement unit is connected with N number of contrast module one-to-one correspondence.The embodiment of the present invention effectively reduces the load in each replacement contrast circuit, the versus speed and reset speed of replacement contrast circuit is accelerated, to improve the read or write speed of chip.
Description
Technical field
The present invention relates to chip technology field, the replacement more particularly to a kind of chip compares device and a kind of chip.
Background technique
In NAND FLASH chip, (NAND FLASH chip is one kind of FLASH chip, is adopted inside NAND FLASH chip
With non-linear macroelement mode) storage unit might have bad point appearance in manufacturing process, and the storage unit for bad point occur cannot
For storing data, chip interior can be written in test phase in the memory unit address for bad point occur by chip interior.To core
When piece is written and read, the memory unit address of appearance bad point of address that needs can be read and write and record carry out pair
Than.If matched after comparison, the storage unit for bad point occur is replaced with chip interior others storage unit；If comparison
It does not match, then normal operating.After the completion of read-write, last comparing result can be resetted, for next time
Read-write is prepared.
But since in the related technology, the contrast module of the replacement contrast circuit connection of chip is relatively more, lead to total post
Raw capacitor is bigger, therefore, affects the reduced time and resetting time of replacement contrast circuit, the read or write speed of chip is lower.
Summary of the invention
In view of the above problems, the embodiment of the invention provides a kind of replacement for the chip for overcoming the above problem comparison device and
A kind of corresponding chip.
To solve the above-mentioned problems, the embodiment of the invention discloses a kind of replacements of chip to compare device, comprising: M are replaced
Change contrast circuit, each replacement contrast circuit has N number of contrast module, each replacement contrast circuit respectively with chip
Comparison reset signal circuit, the input address output end of chip, N number of replacement unit of chip and chip main memory phase
Even, N number of replacement unit is connected with N number of contrast module one-to-one correspondence, wherein M is the integer greater than 1, and N is greater than 0
Integer.
Preferably, each replacement contrast circuit includes: first switch module, the first end of the first switch module
It is connected with default power supply, the control terminal of the first switch module is connected with the comparison reset signal circuit；Second switch mould
Block, the first end of the second switch module are connected with the second end of the first switch module, the second switch module
Control terminal is connected with the comparison reset signal circuit；Third switch module, the first end ground connection of the third switch module, institute
The second end for stating third switch module is connected with the second end of the second switch module, the control terminal of the third switch module
It is connected with the comparison reset signal circuit；N number of contrast module, each contrast module includes parasitic capacitance, each
The first end of the contrast module is connected with the input address output end, the second end of each contrast module respectively with institute
The first end for stating second switch module is connected with the corresponding replacement unit, the third end of each contrast module with it is described
The second end of second switch module is connected, described when the comparison reset signal of the comparison reset signal circuit output is invalid
First switch module, second switch module closure and the third switch module disconnect, and the default power supply is to N number of described
Parasitic capacitance charging；Latch, the latch respectively with the first end of the second switch module and the main memory phase
Even.
Preferably, when the comparison reset signal is effective, the first switch module, the second switch module are disconnected
And the third switch module closure.
Preferably, the first switch module and the second switch module are PMOS tube, and the third switch module is
NMOS tube.
Preferably, when the comparison reset signal is low level, the comparison reset signal is invalid；When the comparison is multiple
When position signal is high level, the comparison reset signal is effective.
Preferably, when the comparison reset signal is high level, the comparison reset signal is invalid；When the comparison is multiple
When position signal is low level, the comparison reset signal is effective.
Preferably, the replacement of chip compares device further include: phase inverter, the phase inverter is resetted with the comparison respectively to be believed
Number circuit, the control terminal of the first switch module, the control terminal of the second switch module and the third switch module
Control terminal is connected, and the phase inverter is used to carry out the comparison reset signal reversed.
To solve the above-mentioned problems, the embodiment of the invention also discloses a kind of chips, comprising: comparison reset signal circuit,
The replacement of input address output end, M × N number of replacement unit, main memory and the chip compares device, wherein the core
Piece replacement comparison device respectively with the comparison reset signal circuit, the input address output end, the M × N number of replacement
Unit is connected with the main memory.
The embodiment of the present invention includes following advantages:
It includes M replacement contrast circuit that replacement by the way that chip is arranged, which compares device, and each replacement contrast circuit is arranged
With N number of contrast module, each replacement contrast circuit is defeated with the comparison reset signal circuit of chip, the input address of chip respectively
Outlet, chip N number of replacement unit be connected with the main memory of chip, N number of replacement unit and N number of contrast module correspond phase
Even, to realize the load (parasitic capacitance) reduced in each replacement contrast circuit, the comparison for accelerating replacement contrast circuit is realized
Speed and reset speed, and then improve the read or write speed of chip.
Detailed description of the invention
Fig. 1 is a kind of structural block diagram of the replacement comparison Installation practice of chip of the invention；
Fig. 2 is a kind of structural schematic diagram of the replacement comparison Installation practice of chip of the invention；
Fig. 3 is a kind of structural block diagram of chip embodiment of the invention.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
One of the core concepts of the embodiments of the present invention is, reduces the load replaced in contrast circuit in the related technology and (posts
Raw capacitor), to realize the versus speed and reset speed for accelerating replacement contrast circuit, and then improve the read or write speed of chip.
Referring to Fig.1, a kind of structural block diagram of replacement comparison 1 embodiment of device of chip of the invention is shown, specifically may be used
With include: M replacement contrast circuit for example replace contrast circuit 101 ..., replacement contrast circuit 10M, each replacement comparison is electric
Road have N number of contrast module, such as replacement contrast circuit 101 N number of contrast module be contrast module 111 ..., contrast module
11N ... ..., replacement contrast circuit 10M N number of contrast module be contrast module 1M1 ..., contrast module 1MN, each replacement
Contrast circuit respectively with the comparison reset signal circuit 2 of chip, the input address output end 3 of chip, chip N number of replacement unit
It is connected with the main memory 5 of chip, N number of replacement unit is connected with N number of contrast module one-to-one correspondence, such as contrast module
111 ..., contrast module 11N respectively with replacement unit 411 ..., replacement unit 41N one-to-one correspondence be connected ... ..., compare
Module 1M1 ..., contrast module 1MN respectively with replacement unit 4M1 ..., replacement unit 4MN one-to-one correspondence be connected.Wherein, M
For the integer greater than 1, N is the integer greater than 0.
Since M × N number of contrast module to be separately positioned in M replacement contrast circuit, compared with replacement in the related technology
Circuit is compared, and the load (parasitic capacitance) replaced in contrast circuit in the replacement comparison device 1 of the chip of the embodiment of the present invention has
Effect is reduced, to realize the versus speed and reset speed for accelerating replacement contrast circuit, improves the read or write speed of chip.
Specifically, the chip in the embodiment of the present invention can be NAND FLASH chip or other chips.In addition, M × N number of
Contrast module for recording M in main memory 5 × N number of memory unit address (each contrast module correspondence for bad point occur respectively
One there is the memory unit address of bad point in record main memory 5).Wherein, the value of M and N can be by contrast module in chip
Number and replacement unit number determine, for example, when chip have 128 contrast modules and 128 replacement units when, i.e. M
× N=128, at this point, it can be 4, N 32 or M can be 8, N be 16 etc. that M, which can be 2, N 64 or M,.
Preferably, each replacement contrast circuit may include: that first switch module 11, second switch module 12, third are opened
Close module 13, N number of contrast module and latch 14.Wherein, the first end of first switch module 11 is connected with default power supply VCC,
The control terminal of first switch module 11 is connected with comparison reset signal circuit 2, and the comparison output comparison of reset signal circuit 2 resets letter
Number.The first end of second switch module 12 is connected with the second end of first switch module 11, the control terminal of second switch module 12
It is connected with comparison reset signal circuit 2.The first end of third switch module 13 is grounded, the second end of third switch module 13 and the
The second end of two switch modules 12 is connected, and the control terminal of third switch module 13 is connected with comparison reset signal circuit 2.It is each right
It include parasitic capacitance than module, the first end of each contrast module is connected with input address output end 3, is written and read to chip
When operation, input address output end 3 is used to export the input address for needing to read and write, the second end difference of each contrast module
It is connected with the first end of second switch module 12 and corresponding replacement unit, the third end of each contrast module and second switch mould
The second end of block 12 is connected, when the comparison reset signal for comparing the output of reset signal circuit 2 is invalid, first switch module 11,
The closure of second switch module 12 and the disconnection of third switch module 13, default power supply VCC charge to N number of parasitic capacitance.Latch 14
It is connected respectively with the first end of second switch module 12 and main memory 5.
Wherein, when comparison reset signal is invalid, due to first switch module 11, the closure of second switch module 12 and third
Switch module 13 disconnects, and the first end of second switch module 12 is high level, and latch 14 is overturn, and the value of latch 14 is low electricity
Flat, latch 14, which is realized, to be resetted.Wherein, during latch 14 resets, since the load in replacement contrast circuit is (parasitic
Capacitor) it effectively reduces, first switch module 11,12 closing speed of second switch module, 13 opening velocity of third switch module add
Fastly, to realize the reset speed for accelerating replacement contrast circuit.
Preferably, when comparison reset signal is effective, first switch module 11, second switch module 12 disconnect and third is opened
Module 13 is closed to be closed.At this point, occurring in the main memory 5 of input address and record that each contrast module respectively reads and writes needs
The memory unit address of bad point compares, and when the comparing result of any contrast module is matching, that is, need to read and write is defeated
It is identical to enter to occur in address and the main memory 5 that the contrast module records the memory unit address of bad point, matches accordingly
Contrast module exports low level, and the first end level of second switch module 12 is pulled low, i.e., the input signal of latch 14 is low
Level, latch 14 are overturn, and the value of latch 14 is high level, and the value of latch 14 is exported to main memory 5, main memory 5
The middle corresponding storage unit of memory unit address for bad point occur is shielded, and data can not be read and write.Meanwhile contrast module is corresponding
Occurs the corresponding storage unit of memory unit address of bad point in replacement unit replacement main memory 5, read-write needs to read and write defeated
Enter the corresponding data in address.
Wherein, since the load (parasitic capacitance) in replacement contrast circuit effectively reduces, each contrast module is respectively to need
Occurs the speed, first that the memory unit address of bad point compares in the main memory 5 of the input address and record to be read and write
12 opening velocity of switch module 11 and second switch module, 13 closing speed of third switch module are accelerated, and add to realize
The versus speed of fast replacement contrast circuit and the read or write speed for improving chip.
Due to presetting power supply VCC and charging to N number of parasitic capacitance, therefore, when N number of when comparison reset signal is invalid
In contrast module, there is bad point in the main memory 5 of input address and record that each contrast module respectively reads and writes needs
When memory unit address compares, it is shared that N number of parasitic capacitance not will do it charge.To in pair of no any contrast module
It is when matching than result, latch 14 will not be shared due to charge and mistake is overturn, and effectively increases each in the embodiment of the present invention
Replace the accuracy of contrast circuit.
Preferably, in one embodiment of the invention, when compare reset signal be high level when, comparison reset signal without
Effect；When comparing reset signal is low level, comparison reset signal is effective.Preferably, referring to Fig. 2, in a reality of the invention
Apply in example, the replacement of chip comparison device 1 can also include phase inverter 20, phase inverter 20 respectively with comparison reset signal circuit 2,
The control terminal of first switch module 11, the control terminal of second switch module 12 are connected with the control terminal of third switch module 13, instead
Phase device 20 is used to carry out comparison reset signal reversed.Preferably, referring to Fig. 2, in one embodiment of the invention, first is opened
Closing module 11 and second switch module 12 can be PMOS tube P1 and PMOS tube P2, and PMOS tube P1 and PMOS tube P2 can be identical,
Third switch module 13 can be NMOS tube N1.
Preferably, in another embodiment of the present invention, when comparing reset signal is low level, reset signal is compared
In vain；When comparing reset signal is high level, comparison reset signal is effective.
The embodiment of the present invention includes following advantages:
It includes M replacement contrast circuit that replacement by the way that chip is arranged, which compares device, and each replacement contrast circuit is arranged
With N number of contrast module, each replacement contrast circuit is defeated with the comparison reset signal circuit of chip, the input address of chip respectively
Outlet, chip N number of replacement unit be connected with the main memory of chip, N number of replacement unit and N number of contrast module correspond phase
Even.To replace the load in contrast circuit in the replacement comparison device of chip compared with replacing contrast circuit in the related technology
(parasitic capacitance) effectively reduces, to realize the versus speed and reset speed for accelerating replacement contrast circuit, improves chip
Read or write speed；
Each replacement contrast circuit have second switch module, second switch module respectively with first switch module, third
Switch module is connected with comparison reset signal circuit, and by each contrast module respectively with the first end of second switch module and the
Two ends are connected, and when comparison reset signal is invalid, first switch module, second switch module closure and third switch module are disconnected
It opens, default power supply charges to N number of parasitic capacitance.Thus when the comparing result of no any contrast module is matching, latch
It will not be shared and mistake overturning due to charge, greatly improve the accuracy of replacement contrast circuit.
In addition, the embodiment of the invention also discloses a kind of chips referring to Fig. 3, comprising: comparison reset signal circuit 2, input
Address output end 3, M × N number of replacement unit, 5 sum of main memory chip replacement compare device 1.Wherein, the replacement pair of chip
Than device 1 respectively with comparison reset signal circuit 2, input address output end 3, M × N number of replacement unit such as replacement unit
411 ..., replacement unit 41N ..., replacement unit 4M1 ..., replacement unit 4MN is connected with main memory 5.
The chip of the embodiment of the present invention includes following advantages:
M × N number of contrast module is separately positioned in the M replacement contrast circuit of replacement comparison device of chip, thus
Compared with replacing contrast circuit in the related technology, the load (parasitic capacitance) in each replacement contrast circuit is effectively reduced, and is realized
The versus speed and reset speed for accelerating replacement contrast circuit, improve the read or write speed of chip；
When comparison reset signal is invalid, charge to each parasitic capacitance in the replacement comparison device of chip.To when pair
When more effective than reset signal, avoid each parasitic capacitance charge in each replacement contrast circuit and share and cause to replace in contrast circuit
The overturning of latch mistake, greatly improves the accuracy of chip.
For chip embodiment, since the replacement that it includes chip compares Installation practice, so the comparison of description
Simply, related place illustrates referring to the part of Installation practice.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.
Although the preferred embodiment of the embodiment of the present invention has been described, once a person skilled in the art knows bases
This creative concept, then additional changes and modifications can be made to these embodiments.So the following claims are intended to be interpreted as
Including preferred embodiment and fall into all change and modification of range of embodiment of the invention.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or terminal device including a series of elements not only wrap
Those elements are included, but also including other elements that are not explicitly listed, or further includes for this process, method, article
Or the element that terminal device is intrinsic.In the absence of more restrictions, being wanted by what sentence "including a ..." limited
Element, it is not excluded that there is also other identical elements in process, method, article or the terminal device for including the element.
Above to a kind of the replacement comparison device and a kind of chip of chip provided by the present invention, it is described in detail,
Used herein a specific example illustrates the principle and implementation of the invention, and the explanation of above embodiments is only used
In facilitating the understanding of the method and its core concept of the invention；At the same time, for those skilled in the art, according to the present invention
Thought, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification should not be construed as
Limitation of the present invention.
Claims (8)
1. a kind of replacement of chip compares device characterized by comprising
M replacement contrast circuit, each replacement contrast circuit have N number of contrast module, each replacement contrast circuit
Respectively with the comparison reset signal circuit of chip, the input address output end of chip, N number of replacement unit of chip and the master of chip
Memory is connected, and N number of replacement unit is connected with N number of contrast module one-to-one correspondence, wherein M is the integer greater than 1, N
For the integer greater than 0；
Each replacement contrast circuit includes:
The first end of first switch module, the first switch module is connected with default power supply, the control of the first switch module
End processed is connected with the comparison reset signal circuit；
Second switch module, the first end of the second switch module is connected with the second end of the first switch module, described
The control terminal of second switch module is connected with the comparison reset signal circuit；
Third switch module, the third switch module first end ground connection, the second end of the third switch module with it is described
The second end of second switch module is connected, and the control terminal of the third switch module is connected with the comparison reset signal circuit；
N number of contrast module, each contrast module includes parasitic capacitance, the first end of each contrast module and institute
State input address output end be connected, the second end of each contrast module respectively with the first end of the second switch module and
The corresponding replacement unit is connected, the second end phase at the third end of each contrast module and the second switch module
Even, when the comparison reset signal of the comparison reset signal circuit output is invalid, the first switch module, described second are opened
It closes module closure and the third switch module disconnects, the default power supply charges to N number of parasitic capacitance.
2. the apparatus according to claim 1, which is characterized in that each replacement contrast circuit further include:
Latch, the latch are connected with the first end of the second switch module and the main memory respectively.
3. the apparatus of claim 2, which is characterized in that when the comparison reset signal is effective, described first is opened
Close module, the second switch module disconnects and the third switch module is closed.
4. device according to claim 2 or 3, which is characterized in that the first switch module and the second switch mould
Block is PMOS tube, and the third switch module is NMOS tube.
5. device according to claim 3, which is characterized in that
When the comparison reset signal is low level, the comparison reset signal is invalid；
When the comparison reset signal is high level, the comparison reset signal is effective.
6. device according to claim 3, which is characterized in that
When the comparison reset signal is high level, the comparison reset signal is invalid；
When the comparison reset signal is low level, the comparison reset signal is effective.
7. device according to claim 6, which is characterized in that further include:
Phase inverter, the phase inverter control terminal, described with the comparison reset signal circuit, the first switch module respectively
The control terminal of second switch module is connected with the control terminal of the third switch module, and the phase inverter is used for multiple to the comparison
Position signal carries out reversed.
8. a kind of chip characterized by comprising comparison reset signal circuit, input address output end, M × N number of replacement are single
The replacement of first, main memory and according to claim 1 chip described in any one of -7 compares device, wherein the chip
Replacement comparison device respectively with the comparison reset signal circuit, the input address output end, the M × N number of replacement unit
It is connected with the main memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510627972.8A CN105261395B (en) | 2015-09-28 | 2015-09-28 | A kind of chip and its replacement comparison device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510627972.8A CN105261395B (en) | 2015-09-28 | 2015-09-28 | A kind of chip and its replacement comparison device |
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| CN105261395A CN105261395A (en) | 2016-01-20 |
| CN105261395B true CN105261395B (en) | 2019-08-30 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH1139861A (en) * | 1997-07-16 | 1999-02-12 | Toshiba Corp | Dynamic semiconductor memory device |
| JP2003045196A (en) * | 2001-08-02 | 2003-02-14 | Fujitsu Ltd | Memory circuit having block address switching function |
| US6480429B2 (en) * | 2001-02-12 | 2002-11-12 | Micron Technology, Inc. | Shared redundancy for memory having column addressing |
| CN103235760B (en) * | 2013-01-31 | 2016-05-04 | 苏州国芯科技有限公司 | High usage NorFLASH memory interface chip based on CLB bus |
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