CN202018827U

CN202018827U - Antifuse memory unit suitable for memorizer

Info

Publication number: CN202018827U
Application number: CN2011200695958U
Authority: CN
Inventors: 曹靓; 封晴
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2011-03-16
Filing date: 2011-03-16
Publication date: 2011-10-26
Anticipated expiration: 2021-03-16

Abstract

The utility model relates to an antifuse memory unit suitable for a memorizer. The antifuse memory unit comprises a first antifuse unit, a second antifuse unit, a first high-voltage NMOS (N-Mental-Oxide-Semiconductor) tube and a second high-voltage NMOS tube both under programmed control, a third PMOS (P-channel Metal Oxide Semiconductor) tube and a fourth PMOS tube both carrying out antifuse protection, two reversers, and a comparison output stage formed by a fifth NMOS tube and a sixth NMOS tube, wherein the first high-voltage NMOS tube and the second high-voltage NMOS tube adopt complementary signal programming; the third PMOS tube and the fourth PMOS tube carry out voltage protection to the unprogrammed antifuse in work; and the fifth NMOS tube and the sixth NMOS tube form a bistable comparison circuit comparison output. The utility model has the advantage that the circuit adopts the complementary signal programming and bistable comparison circuit output, as well as antifuse protection tube structure, so that the memory unit can realize the one-step programming memorizer with high reliability and long service life.

Description

Be applicable to the anti-fuse storage unit of storer

Technical field

The utility model relates to a kind of anti-fuse storage unit, belongs to CMOS integrated circuit (IC) design technical field.

Background technology

Anti-fuse is for traditional fuse-wires structure.The fundamental of anti-fuse is to utilize the particular electrical medium with two electrodes separately.In the ordinary course of things, this dielectric can show the impedance of G Ω level, isolated electrode effectively.But, after applying a suitable program voltage and electric current, dielectric can form the conduction pathway (＜1k Ω) of a connection electrode, with two electrode conductions, utilizes the conducting of anti-fuse whether to realize information stores.Anti-fuse is compared with the traditional cmos structure memory as a kind of novel storage organization, and it can provide a kind of high current densities, low-power consumption, the combination of non-volatile programming and high reliability, high life.

Anti-fuse is subjected to factor affecting such as process conditions and programmed environment, conducting resistance can be floated between hundreds of to a kilo-ohm, and the anti-fuse of not programming works long hours security risk also arranged under high voltage, and these problems can have influence on the reliability and the life-span of circuit under certain situation.

Summary of the invention

The purpose of this utility model is to overcome the deficiencies in the prior art, a kind of anti-fuse storage unit that is applicable to storer is provided, can effectively overcome the above problems, adopt the storage unit of this design can realize high reliability, the one-time programming storer of high life.

The technical scheme that provides according to the utility model, the described anti-fuse storage unit of storer that is applicable to comprises: first anti-fuse cell, second anti-fuse cell, the first high pressure NMOS pipe of programming Control and the second high pressure NMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe; Described first anti-fuse cell, one termination high level, the source electrode of another termination the 3rd PMOS pipe and the drain electrode of the first high pressure NMOS pipe, second anti-fuse cell, one termination high level, the source electrode of another termination the 4th PMOS pipe and the drain electrode of the second high pressure NMOS pipe, the first high pressure NMOS tube grid connects the first programming data input port, the second high pressure NMOS tube grid connects the second programming data input port, the 3rd gate pmos utmost point extremely links to each other with the 4th gate pmos and is connected reading control, the drain electrode of the 3rd PMOS pipe connects the drain electrode of the 5th NMOS pipe, the drain electrode of the 4th PMOS pipe connects the drain electrode of the 6th NMOS pipe, the 6th NMOS tube grid connects first data-out port by first reverser, and the 5th NMOS tube grid connects second data-out port by second reverser; The first high pressure NMOS pipe source electrode, the second high pressure NMOS pipe source electrode, the 5th NMOS manages source electrode, and the 6th NMOS manages source ground; The data of the described first programming data input port and the second programming data input port always occur with the form of complementary pair, and the output data of first data-out port and second data-out port also is the form output with complementary pair.

The utility model has the advantages that: adopt the bistable state comparator circuit as output stage, and be provided with protection tube and when work, anti-fuse protected; Its cellular construction has high current densities, low-power consumption, the characteristics of non-volatile programming and high reliability, high life.

Description of drawings

Fig. 1 is the anti-fuse memory cell circuit schematic diagram of the utility model.

Embodiment

The utility model is described in further detail below in conjunction with drawings and Examples.

As shown in Figure 1, each storage unit described in the utility model comprises: two anti-fuse cell FUSE1, FUSE2; The high pressure NMOS pipe M1 of programming Control, M2; The PMOS pipe M3 of protection control, M4; Two reversers and NMOS pipe M5, the comparison output stage that M6 constitutes.Be specially: the first anti-fuse cell FUSE1, one termination high level VCC, the drain electrode (claiming circuit node A) of the source electrode of another termination the 3rd PMOS pipe M3 and the first high pressure NMOS pipe M1, the second anti-fuse cell FUSE2, one termination high level VCC, the drain electrode (claiming circuit node B) of the source electrode of another termination the 4th PMOS pipe M4 and the second high pressure NMOS pipe M2, the first high pressure NMOS pipe M1 grid meets the first programming data input port P1, the second high pressure NMOS pipe M2 grid meets the second programming data input port P2, the 3rd PMOS pipe M3 grid links to each other with the 4th PMOS pipe M4 grid and is connected reading control C, the 3rd PMOS pipe M3 drain electrode connects the 5th NMOS pipe M5 drain electrode, the 4th PMOS pipe M4 drain electrode connects the 6th NMOS pipe M6 drain electrode, the 6th NMOS pipe M6 grid connects the first data-out port O1 by the first reverser T1, and the 5th NMOS pipe M5 grid connects the second data-out port O2 by the second reverser T2; The first high pressure NMOS pipe M1 source electrode, the second high pressure NMOS pipe M2 source electrode, the 5th NMOS pipe M5 source electrode, the 6th NMOS pipe M6 source ground GND.

Programming data input port P1, the data of two ports of P2 always occur with the form of complementary pair, and promptly a port is input as logical one, and another port is a logical zero just.Reading control C control data read output.Equally, data-out port O1, the output data of O2 also is the form output with complementary pair, and promptly a port is output as logical one, and another port output is logical zero just.

Programming Control high pressure NMOS pipe M1, M2 adopt the complementary signal programming; By anti-fuse protected PMOS pipe M3, M4 carries out voltage protection to the anti-fuse of not programming in the work; By NMOS pipe M5, M6 constitutes the bistable state comparator circuit and relatively exports.Described anti-fuse storage unit reduces the pressure drop at anti-fuse two ends in the course of the work by the PMOS protection tube, protect the anti-fuse of not programming to avoid the mistake programming; In mode of or not of a programming, utilize comparative result with two anti-fuse cells as canned data; Adopt bistable circuit that the programme anti-fuse path and the anti-fuse path of not programming are compared in output stage, utilize comparative result as output, the complementary pair signal is adopted in output.

Circuit working has two stages: programming phases and fetch phase.

1. programming phases

Programming phases is that the storage unit of sky is carried out the process that data write.In programming phases, port C input high voltage is managed M3 with PMOS, and M4 closes.The data that need write are by P1, the input of P2 port, and the input data must be with the form input of complementary pair, i.e. a port input logic " 1 ", another port input logic " 0 ".P1, P2 port input signal can be managed M1 with NMOS, opens for one among the M2, and another is closed.Because PMOS pipe M3, M4 closes, so NMOS pipe M1, anti-fuse (FUSE1 or the FUSE2) two ends that pipe of opening among the M2 links to each other are programmed because the high pressure drop of VCC to GND is arranged, and become Low ESR; And the anti-fuse that links to each other with the pipe of closing does not have the path of VCC to GND, so there is not high pressure drop, presents the not high impedance of programming.Simultaneously, NMOS pipe M1 is set reasonably, the breadth length ratio of M2 plays the effect of current limliting, guarantees that the programming electric current meets anti-fuse programming requirement.

The data that no matter write are logical zero or logical one, and anti-fuse FUSE1 and FUSE2 always have one to be programmed.The needed voltage of programming, electric current and programming time are depended on used technology.

2. fetch phase

Fetch phase is the process that the data in the anti-fuse storage unit that programming is finished are read.At fetch phase, programming data input port P1, the equal input logic of P2 " 0 " the NMOS pipe M1 that will programme, M2 closes.Port C manages M3 with PMOS, and M4 opens.Because anti-fuse FUSE1 and FUSE2 programming always, a not programming is equivalent to one tunnel conducting one tunnel and ends, and therefore conduction downwards is one road high level, one tunnel low level.NMOS manages M5, and the bistable circuit that M6 forms compares through reverser T1 two-way voltage, T2 output.

Adopt this comparative structure as output stage following consideration to be arranged: the performance of anti-fuse in its working range of having programmed be as stable a, linear resistor reliably, and can keep its low resistance all the time at the life period of device.But, if the anti-fuse cell of having programmed is damaged, it can present a kind of non-linear behavior, and it is unstable that its resistance will become.The variation that the resistance of the anti-fuse of programming of a damage may occur from up to a hundred to up to ten thousand ohm.If anti-fuse is directly to connect a high or low logic gate, so, the anti-fuse of damage may make it remain on wrong logic level.And the essence of this comparative structure is that programme the anti-fuse and the anti-fuse of not programming are carried out resistance value ratio, even mutation to a certain degree appears in the anti-fuse of having programmed, with the impedance phase of anti-fuse G Ω level of not programming be the difference that the order of magnitude is arranged than all, can not influence the relatively result of output, so can effectively improve reliability and serviceable life.

PMOS manages M3, and M4 also plays the effect of the anti-fuse of protection except as the read switch.The intermediate level that port C is provided by the outside acts on PMOS pipe M3, on the M4, the current potential of node A and Node B is raised.Make like this do not programme anti-fuse at the bias voltage at fetch phase two ends well below supply voltage, the risk that the anti-fuse of having avoided not programming works long hours and programmed under the power supply bias voltage by mistake.

Claims

1. be applicable to the anti-fuse storage unit of storer, it is characterized in that: comprise first anti-fuse cell (FUSE1), second anti-fuse cell (FUSE2), the first high pressure NMOS pipe (M1) of programming Control and the second high pressure NMOS pipe (M2), the 3rd PMOS manages (M3), the 4th PMOS manages (M4), and the 5th NMOS manages (M5), and the 6th NMOS manages (M6);

Described first anti-fuse cell (FUSE1) termination high level (VCC), the source electrode of another termination the 3rd PMOS pipe (M3) and the drain electrode of the first high pressure NMOS pipe (M1), second anti-fuse cell (FUSE2) termination high level (VCC), the source electrode of another termination the 4th PMOS pipe (M4) and the drain electrode of the second high pressure NMOS pipe (M2), first high pressure NMOS pipe (M1) grid connects the first programming data input port (P1), second high pressure NMOS pipe (M2) grid connects the second programming data input port (P2), it is continuous and be connected reading control (C) that the 3rd PMOS pipe (M3) grid and the 4th PMOS manages (M4) grid, the 3rd PMOS pipe (M3) drain electrode connects the 5th NMOS pipe (M5) drain electrode, the 4th PMOS pipe (M4) drain electrode connects the 6th NMOS pipe (M6) drain electrode, the 6th NMOS pipe (M6) grid connects first data-out port (O1) by first reverser (T1), and the 5th NMOS pipe (M5) grid connects second data-out port (O2) by second reverser (T2); First high pressure NMOS pipe (M1) source electrode, second high pressure NMOS pipe (M2) source electrode, the 5th NMOS manages (M5) source electrode, and the 6th NMOS manages (M6) source ground (GND); The data of the described first programming data input port (P1) and the second programming data input port (P2) always occur with the form of complementary pair, and first data-out port (O1) also is to export with the form of complementary pair with the output data of second data-out port (O2).