CN105261395A - Chip and replacement and comparison apparatus thereof - Google Patents
Chip and replacement and comparison apparatus thereof Download PDFInfo
- Publication number
- CN105261395A CN105261395A CN201510627972.8A CN201510627972A CN105261395A CN 105261395 A CN105261395 A CN 105261395A CN 201510627972 A CN201510627972 A CN 201510627972A CN 105261395 A CN105261395 A CN 105261395A
- Authority
- CN
- China
- Prior art keywords
- contrast
- switch module
- reset signal
- chip
- replacement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Read Only Memory (AREA)
- Electronic Switches (AREA)
Abstract
Embodiments of the invention provide a chip and a replacement and comparison apparatus thereof. The apparatus comprises M replacement and comparison circuits, wherein each replacement and comparison circuit is provided with N comparison modules; each replacement and comparison circuit is connected with a comparison reset signal circuit of the chip, an input address output end of the chip, N replacement units of the chip and a main memory of the chip; and the N replacement units are connected with the N comparison modules in a one-to-one correspondence manner. According to the chip and the replacement and comparison apparatus thereof provided by the embodiments of the invention, a load on each replacement and comparison circuit is reduced, and the comparison speed and the reset speed of the replacement and comparison circuit are increased, so that the read/write speed of the chip is increased.
Description
Technical field
The present invention relates to chip technology field, particularly relate to a kind of replacement compare device of chip and a kind of chip.
Background technology
At NANDFLASH chip, (NANDFLASH chip is the one of FLASH chip, NANDFLASH chip internal adopts non-linear macroelement pattern) storage unit may have bad point and occurs in manufacture process, occur that the storage unit of bad point can not be used for storing data, chip internal can occurring that the memory unit address of bad point writes chip internal at test phase.When carrying out read-write operation to chip, the memory unit address of the appearance bad point of the address and record that need read-write can be contrasted.If matched after contrast, replace by other storage unit of chip internal the storage unit occurring bad point; If contrast does not match, then normal running.After read-write completes, can reset to the comparing result of last time, think that read-write is next time prepared.
But due in correlation technique, the contrast module that the replacement contrast circuit of chip connects is many, causes total stray capacitance larger, and therefore, have impact on the reduced time and reset time of replacing contrast circuit, the read or write speed of chip is lower.
Summary of the invention
In view of the above problems, the replacement compare device of a kind of chip overcoming the problems referred to above and corresponding a kind of chip is embodiments provided.
In order to solve the problem, the embodiment of the invention discloses a kind of replacement compare device of chip, comprise: replace contrast circuit for M, each described replacement contrast circuit has N number of contrast module, each described replacement contrast circuit is connected with the primary memory of chip with the contrast reset signal circuit of chip, the Input Address output terminal of chip, N number of replacement unit of chip respectively, described N number of replacement unit is connected with described N number of contrast module one_to_one corresponding, wherein, M be greater than 1 integer, N be greater than 0 integer.
Preferably, each described replacement contrast circuit comprises: the first switch module, and the first end of described first switch module is connected with default power supply, and the control end of described first switch module is connected with described contrast reset signal circuit, second switch module, the first end of described second switch module is connected with the second end of described first switch module, and the control end of described second switch module is connected with described contrast reset signal circuit, 3rd switch module, the first end ground connection of described 3rd switch module, the second end of described 3rd switch module is connected with the second end of described second switch module, and the control end of described 3rd switch module is connected with described contrast reset signal circuit, described N number of contrast module, each described contrast module comprises stray capacitance, the first end of each described contrast module is connected with described Input Address output terminal, second end of each described contrast module is connected with corresponding described replacement unit with the first end of described second switch module respectively, 3rd end of each described contrast module is connected with the second end of described second switch module, when the contrast reset signal that described contrast reset signal circuit exports is invalid, described first switch module, described second switch module closes and described 3rd switch module disconnects, described default power supply is to N number of described stray capacitance charging, latch, described latch is connected with described primary memory with the first end of described second switch module respectively.
Preferably, when described contrast reset signal is effective, described first switch module, described second switch module disconnect and described 3rd switch module closes.
Preferably, described first switch module and described second switch module are PMOS, and described 3rd switch module is NMOS tube.
Preferably, when described contrast reset signal is low level, described contrast reset signal is invalid; When described contrast reset signal is high level, described contrast reset signal is effective.
Preferably, when described contrast reset signal is high level, described contrast reset signal is invalid; When described contrast reset signal is low level, described contrast reset signal is effective.
Preferably, the replacement compare device of chip also comprises: phase inverter, described phase inverter is connected with the control end of described 3rd switch module with the control end of described contrast reset signal circuit, described first switch module, the control end of described second switch module respectively, and described phase inverter is used for carrying out oppositely described contrast reset signal.
In order to solve the problem, the embodiment of the invention also discloses a kind of chip, comprise: the replacement compare device of contrast reset signal circuit, Input Address output terminal, M × N number of replacement unit, primary memory and described chip, wherein, the replacement compare device of described chip is connected with described primary memory with described contrast reset signal circuit, described Input Address output terminal, described M × N number of replacement unit respectively.
The embodiment of the present invention comprises following advantage:
Comprise M by the replacement compare device arranging chip and replace contrast circuit, and each replacement contrast circuit is set there is N number of contrast module, each replacement contrast circuit is connected with the primary memory of chip with the contrast reset signal circuit of chip, the Input Address output terminal of chip, N number of replacement unit of chip respectively, N number of replacement unit is connected with N number of contrast module one_to_one corresponding, thus realize reducing the load (stray capacitance) in each replacement contrast circuit, realize versus speed and the reset speed of accelerating replacement contrast circuit, and then improve the read or write speed of chip.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the replacement compare device embodiment of a kind of chip of the present invention;
Fig. 2 is the structural representation of the replacement compare device embodiment of a kind of chip of the present invention;
Fig. 3 is the structured flowchart of a kind of chip embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
One of core idea of the embodiment of the present invention is, reduces the load (stray capacitance) of replacing in correlation technique in contrast circuit, thus realizes versus speed and the reset speed of accelerating replacement contrast circuit, and then improves the read or write speed of chip.
With reference to Fig. 1, show the structured flowchart of replacement compare device 1 embodiment of a kind of chip of the present invention, specifically can comprise: replace contrast circuit for M and such as replace contrast circuit 101, replace contrast circuit 10M, each replacement contrast circuit has N number of contrast module, such as, replace N number of contrast module of contrast circuit 101 for contrast module 111, contrast module 11N ..., replace N number of contrast module of contrast circuit 10M for contrast module 1M1, contrast module 1MN, each replacement contrast circuit respectively with the contrast reset signal circuit 2 of chip, the Input Address output terminal 3 of chip, N number of replacement unit of chip is connected with the primary memory 5 of chip, and N number of replacement unit is connected with N number of contrast module one_to_one corresponding, such as, contrast module 111, contrast module 11N respectively with replacement unit 411, replacement unit 41N one_to_one corresponding is connected ..., contrast module 1M1, contrast module 1MN respectively with replacement unit 4M1, replacement unit 4MN one_to_one corresponding is connected.Wherein, M be greater than 1 integer, N be greater than 0 integer.
Replace in contrast circuit owing to M × N number of contrast module to be separately positioned on M, with replace compared with contrast circuit in correlation technique, the load (stray capacitance) of replacing in the replacement compare device 1 of the chip of the embodiment of the present invention in contrast circuit effectively reduces, thus achieve the versus speed and reset speed of accelerating to replace contrast circuit, improve the read or write speed of chip.
Particularly, the chip in the embodiment of the present invention can be NANDFLASH chip or other chip.In addition, M × N number of contrast module is used for recording M × N number of memory unit address (in each contrast module corresponding record primary memory 5, occurs the memory unit address of bad point) occurring bad point in primary memory 5 respectively.Wherein, the value of M and N can be determined by the number of the number and replacement unit that contrast module in chip, such as, when chip has 128 contrast modules and 128 replacement units, i.e. M × N=128, now, M can be 2, N is 64, or M can be 4, N is 32, or M can be 8, N is 16 etc.
Preferably, each replacement contrast circuit can comprise: the first switch module 11, second switch module 12, the 3rd switch module 13, N number of contrast module and latch 14.Wherein, the first end of the first switch module 11 is connected with default power supply VCC, and the control end of the first switch module 11 is connected with contrast reset signal circuit 2, and contrast reset signal circuit 2 exports contrast reset signal.The first end of second switch module 12 is connected with the second end of the first switch module 11, and the control end of second switch module 12 is connected with contrast reset signal circuit 2.The first end ground connection of the 3rd switch module 13, the second end of the 3rd switch module 13 is connected with the second end of second switch module 12, and the control end of the 3rd switch module 13 is connected with contrast reset signal circuit 2.Each contrast module comprises stray capacitance, the first end of each contrast module is connected with Input Address output terminal 3, when carrying out read-write operation to chip, Input Address output terminal 3 needs the Input Address of read-write for exporting, second end of each contrast module is connected with corresponding replacement unit with the first end of second switch module 12 respectively, 3rd end of each contrast module is connected with the second end of second switch module 12, when the contrast reset signal contrasting the output of reset signal circuit 2 is invalid, first switch module 11, second switch module 12 closes and the 3rd switch module 13 disconnects, preset power supply VCC to charge to N number of stray capacitance.Latch 14 is connected with primary memory 5 with the first end of second switch module 12 respectively.
Wherein, when contrasting reset signal and being invalid, due to the first switch module 11, second switch module 12 closes and the 3rd switch module 13 disconnects, the first end of second switch module 12 is high level, latch 14 overturns, and the value of latch 14 is low level, and latch 14 realizes resetting.Wherein, in the process that latch 14 resets, because the load (stray capacitance) of replacing in contrast circuit effectively reduces, first switch module 11, second switch module 12 closing speed, the 3rd switch module 13 opening velocity are accelerated, thus achieve the reset speed of accelerating to replace contrast circuit.
Preferably, when contrasting reset signal and being effective, the first switch module 11, second switch module 12 disconnect and the 3rd switch module 13 closes.Now, to in the primary memory 5 of the Input Address and record that need read-write, each contrast module occurs that the memory unit address of bad point contrasts respectively, and when the comparing result of arbitrary contrast module is for coupling, namely the Input Address read and write is needed to occur that the memory unit address of bad point is identical with the primary memory 5 of this contrast module record, the contrast module output low level matched accordingly, the first end level of second switch module 12 is dragged down, namely the input signal of latch 14 is low level, latch 14 overturns, the value of latch 14 is high level, the value of latch 14 exports primary memory 5 to, the storage unit conductively-closed that the memory unit address of bad point is corresponding is there is in primary memory 5, cannot read and write data.Meanwhile, the replacement unit that contrast module is corresponding is replaced in primary memory 5 and is occurred the storage unit that the memory unit address of bad point is corresponding, the data that read-write needs the Input Address of read-write corresponding.
Wherein, because the load (stray capacitance) of replacing in contrast circuit effectively reduces, there is speed, the first switch module 11 and second switch module 12 opening velocity that the memory unit address of bad point contrasts in the primary memory 5 of each contrast module respectively to the Input Address and record that need read-write, the 3rd switch module 13 closing speed all accelerates, thus achieve and accelerate replace the versus speed of contrast circuit and improve the read or write speed of chip.
Due to when contrasting reset signal and being invalid, preset power supply VCC to charge to N number of stray capacitance, therefore, when in N number of contrast module, when occurring that the memory unit address of bad point contrasts in the primary memory 5 of each contrast module respectively to the Input Address and record that need read-write, N number of stray capacitance can not be carried out electric charge and be shared.Thus when the comparing result without any contrast module is for coupling, latch 14 can not be shared and mistake upset due to electric charge, effectively improves each accuracy of replacing contrast circuit in the embodiment of the present invention.
Preferably, in one embodiment of the invention, when contrast reset signal is high level, contrast reset signal is invalid; When contrast reset signal is low level, contrast reset signal is effective.Preferably, with reference to Fig. 2, in one embodiment of the invention, the replacement compare device 1 of chip can also comprise phase inverter 20, phase inverter 20 is connected with the control end of the 3rd switch module 13 with the control end of contrast reset signal circuit 2, first switch module 11, the control end of second switch module 12 respectively, and phase inverter 20 is for carrying out oppositely contrast reset signal.Preferably, with reference to Fig. 2, in one embodiment of the invention, the first switch module 11 and second switch module 12 can be that PMOS P1 and PMOS P2, PMOS P1 and PMOS P2 can be identical, and the 3rd switch module 13 can be NMOS tube N1.
Preferably, in another embodiment of the present invention, when contrast reset signal is low level, contrast reset signal is invalid; When contrast reset signal is high level, contrast reset signal is effective.
The embodiment of the present invention comprises following advantage:
Comprise M by the replacement compare device arranging chip and replace contrast circuit, and each replacement contrast circuit is set there is N number of contrast module, each replacement contrast circuit is connected with the primary memory of chip with the contrast reset signal circuit of chip, the Input Address output terminal of chip, N number of replacement unit of chip respectively, and N number of replacement unit is connected with N number of contrast module one_to_one corresponding.Thus with replace compared with contrast circuit in correlation technique, the load (stray capacitance) of replacing in the replacement compare device of chip in contrast circuit effectively reduces, thus achieve the versus speed and reset speed of accelerating to replace contrast circuit, improve the read or write speed of chip;
Each replacement contrast circuit has second switch module, second switch module is respectively with the first switch module, the 3rd switch module with contrast reset signal circuit and be connected, and each contrast module is connected with the second end with the first end of second switch module respectively, and when contrasting reset signal and being invalid, first switch module, second switch module close and the 3rd switch module disconnects, and preset power supply and charge to N number of stray capacitance.Thus when the comparing result without any contrast module is for coupling, latch can not be shared and mistake upset due to electric charge, drastically increases the accuracy of replacing contrast circuit.
In addition, with reference to Fig. 3, the embodiment of the invention also discloses a kind of chip, comprising: contrast reset signal circuit 2, Input Address output terminal 3, M × N number of replacement unit, primary memory 5 and the replacement compare device 1 of chip.Wherein, the replacement compare device 1 of chip respectively with contrast reset signal circuit 2, Input Address output terminal 3, M × N number of replacement unit such as replacement unit 411 ..., replacement unit 41N ..., replacement unit 4M1 ..., replacement unit 4MN is connected with primary memory 5.
The chip of the embodiment of the present invention comprises following advantage:
Replace in contrast circuit for M that M × N number of contrast module is separately positioned on the replacement compare device of chip, thus with replace compared with contrast circuit in correlation technique, load (stray capacitance) in each replacement contrast circuit effectively reduces, achieve the versus speed and reset speed of accelerating to replace contrast circuit, improve the read or write speed of chip;
When contrasting reset signal and being invalid, to stray capacitance charging each in the replacement compare device of chip.Thus when contrasting reset signal and being effective, avoid each stray capacitance electric charge in each replacement contrast circuit and share and cause replacing latch mistake upset in contrast circuit, drastically increase the accuracy of chip.
For chip embodiment, because it comprises the replacement compare device embodiment of chip, so description is fairly simple, relevant part illustrates see the part of device embodiment.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
Although described the preferred embodiment of the embodiment of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of embodiment of the present invention scope.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or terminal device and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or terminal device.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the terminal device comprising described key element and also there is other identical element.
Above to replacement compare device and a kind of chip of a kind of chip provided by the present invention, be described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (8)
1. a replacement compare device for chip, is characterized in that, comprising:
Replace contrast circuit for M, each described replacement contrast circuit has N number of contrast module, each described replacement contrast circuit is connected with the primary memory of chip with the contrast reset signal circuit of chip, the Input Address output terminal of chip, N number of replacement unit of chip respectively, described N number of replacement unit is connected with described N number of contrast module one_to_one corresponding, wherein, M be greater than 1 integer, N be greater than 0 integer.
2. device according to claim 1, is characterized in that, each described replacement contrast circuit comprises:
First switch module, the first end of described first switch module is connected with default power supply, and the control end of described first switch module is connected with described contrast reset signal circuit;
Second switch module, the first end of described second switch module is connected with the second end of described first switch module, and the control end of described second switch module is connected with described contrast reset signal circuit;
3rd switch module, the first end ground connection of described 3rd switch module, the second end of described 3rd switch module is connected with the second end of described second switch module, and the control end of described 3rd switch module is connected with described contrast reset signal circuit;
Described N number of contrast module, each described contrast module comprises stray capacitance, the first end of each described contrast module is connected with described Input Address output terminal, second end of each described contrast module is connected with corresponding described replacement unit with the first end of described second switch module respectively, 3rd end of each described contrast module is connected with the second end of described second switch module, when the contrast reset signal that described contrast reset signal circuit exports is invalid, described first switch module, described second switch module closes and described 3rd switch module disconnects, described default power supply is to N number of described stray capacitance charging,
Latch, described latch is connected with described primary memory with the first end of described second switch module respectively.
3. circuit according to claim 2, is characterized in that, when described contrast reset signal is effective, described first switch module, described second switch module disconnect and described 3rd switch module closes.
4. the circuit according to Claims 2 or 3, is characterized in that, described first switch module and described second switch module are PMOS, and described 3rd switch module is NMOS tube.
5. circuit according to claim 3, is characterized in that,
When described contrast reset signal is low level, described contrast reset signal is invalid;
When described contrast reset signal is high level, described contrast reset signal is effective.
6. circuit according to claim 3, is characterized in that,
When described contrast reset signal is high level, described contrast reset signal is invalid;
When described contrast reset signal is low level, described contrast reset signal is effective.
7. circuit according to claim 6, is characterized in that, also comprises:
Phase inverter, described phase inverter is connected with the control end of described 3rd switch module with the control end of described contrast reset signal circuit, described first switch module, the control end of described second switch module respectively, and described phase inverter is used for carrying out oppositely described contrast reset signal.
8. a chip, it is characterized in that, comprise: the replacement compare device of contrast reset signal circuit, Input Address output terminal, M × N number of replacement unit, primary memory and the chip according to any one of claim 1-7, wherein, the replacement compare device of described chip is connected with described primary memory with described contrast reset signal circuit, described Input Address output terminal, described M × N number of replacement unit respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510627972.8A CN105261395B (en) | 2015-09-28 | 2015-09-28 | A kind of chip and its replacement comparison device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510627972.8A CN105261395B (en) | 2015-09-28 | 2015-09-28 | A kind of chip and its replacement comparison device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105261395A true CN105261395A (en) | 2016-01-20 |
| CN105261395B CN105261395B (en) | 2019-08-30 |
Family
ID=55101043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510627972.8A Active CN105261395B (en) | 2015-09-28 | 2015-09-28 | A kind of chip and its replacement comparison device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105261395B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110827878A (en) * | 2018-08-08 | 2020-02-21 | 华邦电子股份有限公司 | Memory device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5991218A (en) * | 1997-07-16 | 1999-11-23 | Kabushiki Kaisha Toshiba | Dynamic random access memory |
| US20020105840A1 (en) * | 2001-02-08 | 2002-08-08 | Fujitsu Limited | Memory circuit having block address switching function |
| US20030086310A1 (en) * | 2001-02-12 | 2003-05-08 | Jones William F. | Shared redundancy for memory having column addressing |
| CN103235760A (en) * | 2013-01-31 | 2013-08-07 | 苏州国芯科技有限公司 | CLB-bus-based NorFLASH memory interface chip with high utilization ratio |
-
2015
- 2015-09-28 CN CN201510627972.8A patent/CN105261395B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5991218A (en) * | 1997-07-16 | 1999-11-23 | Kabushiki Kaisha Toshiba | Dynamic random access memory |
| US20020105840A1 (en) * | 2001-02-08 | 2002-08-08 | Fujitsu Limited | Memory circuit having block address switching function |
| US20030086310A1 (en) * | 2001-02-12 | 2003-05-08 | Jones William F. | Shared redundancy for memory having column addressing |
| CN103235760A (en) * | 2013-01-31 | 2013-08-07 | 苏州国芯科技有限公司 | CLB-bus-based NorFLASH memory interface chip with high utilization ratio |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110827878A (en) * | 2018-08-08 | 2020-02-21 | 华邦电子股份有限公司 | Memory device |
| CN110827878B (en) * | 2018-08-08 | 2021-09-14 | 华邦电子股份有限公司 | Memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105261395B (en) | 2019-08-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101645308B (en) | Shift register comprising multiple stage circuit units | |
| US8742830B2 (en) | Fuse sensing circuits | |
| CN102522123B (en) | Method for increasing read-write test efficiency of storage equipment by utilizing data generator module | |
| US9118315B2 (en) | Scheme to improve the performance and reliability in high voltage IO circuits designed using low voltage devices | |
| CN112929012A (en) | Leakage compensation latch, data operation unit and chip | |
| CN104112466A (en) | Sense amplifier applied to MTP (Mail Transfer Protocol) storage | |
| CN203313151U (en) | Device and system for improving load independent buffers | |
| CN105261395A (en) | Chip and replacement and comparison apparatus thereof | |
| CN104051023A (en) | Detecting circuit and detecting method | |
| CN101825939B (en) | Digital system and power on reset circuit thereof | |
| US9450587B2 (en) | Test circuit and test method of semiconductor apparatus | |
| US9479151B2 (en) | Apparatuses and methods for controlling delay circuits during an idle state to reduce degradation of an electrical characteristic | |
| US20150162077A1 (en) | Static memory cell | |
| CN105261396A (en) | Chip and replacement and comparison circuit thereof | |
| CN104979011B (en) | Optimize data reading circuit in data storage type flash memory | |
| US9275758B2 (en) | Error detection circuit and semiconductor integrated circuit using the same | |
| CN103744640B (en) | Circuit, CAM, TLB, memorizer and microprocessor are searched in position | |
| US20160111144A1 (en) | Pulse width modulation device | |
| CN203465714U (en) | Bit finding circuit, bypass conversion buffer, storage and microprocessor | |
| CN206370683U (en) | It is a kind of to be used for the light-coupled isolation lightning protection circuit of practical On-off signal data signal | |
| CN102789408B (en) | System detection method and device based on NAND (Not And) Flash | |
| US10109338B2 (en) | Semiconductor devices and semiconductor systems generating internal address | |
| CN103413567A (en) | Reference voltage supply circuit | |
| JP2014131283A (en) | Crystal oscillator frequency adjustment device | |
| US11715548B2 (en) | Repair circuit and memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |