CN105253853A - Method for preventing ICP excessive etching in SOG-MEMS chip - Google Patents
Method for preventing ICP excessive etching in SOG-MEMS chip Download PDFInfo
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- CN105253853A CN105253853A CN201510701040.3A CN201510701040A CN105253853A CN 105253853 A CN105253853 A CN 105253853A CN 201510701040 A CN201510701040 A CN 201510701040A CN 105253853 A CN105253853 A CN 105253853A
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Abstract
The invention provides a method for preventing ICP excessive etching in an SOG-MEMS chip. For simultaneously etching multiple rectangles and through etching multiple line shapes with the same line width or different line widths, a central non-exposed area (12) is arranged in each rectangle needing to be etched on a photoetching board and forms a to-be-etched exposed area with the middle of the frame, that is, an external non-exposed area (11) of the rectangle, and the width of the to-be-etched exposed area is equal to the line width of the minimum line shape to be through etched; the uniform of the etching strip width is guaranteed, and the problem of an Lag effect in the etching process of the structure with the different strip widths is solved; meanwhile, when etching is completed, the central non-exposed areas (12) fall onto supporting layers (1) under the central non-exposed areas (12), and therefore the fact that etching is completed can be accurately judged. The method has the advantages that seriously excessive etching of the MEMS structure with the different etching strip width in ICP etching can be effectively prevented from being caused.
Description
Technical field
The present invention relates to a kind of method preventing ICP overetch in SOG-MEMS chip, the invention belongs to MEMS (MEMS) device fabrication field, particularly for the dry etching technology of si-glass structure fabrication MEMS, relate in a kind of SOG-MEMS chip the method preventing or reduce overetch in ICP etching and carry out end point determination.
Background technology
SOG-MEMS structure based on silicon on glass bonding and the dark silicon etching of ICP is widely used in inertia device and other sensors.In processes process, need first the silicon layer with anchor point to be bonded to glassy layer, glassy layer plays the effect of support, photoetching is carried out when desired thickness is thinned to silicon face, use inductively coupled plasma (ICP) equipment to carry out dry etching to silicon structural layer again, complete silicon structure release.
In ICP processes process, there are two subject matters.One, because MEMS comprises the three-dimensional structure of different etching depth-to-width ratio, in structure release process, the lines etch rate of different size is variant, namely there is Lag effect; Its two, have in narrow linewidth structure as wide in 2 ~ 5 μm, accurately judging that whether silicon structure discharges by ICP completely and become difficult.Its reason is, the channel structure of the high-aspect-ratio in MEMS structure is difficult to use the equipment such as step instrument to measure its degree of depth, light microscope and ESEM also cannot observe the bottom of etching groove, therefore accurately etching terminal cannot be determined, easily cause etching not complete or overetch, affect the performance of device.In the ICP etching apparatus of some advanced person, whether the device that can be fitted through monitoring feature product, to carry out endpoint monitoring, nonetheless, due to the existence of Lag effect, also still needs to carry out etching after being taken out by chip to check completely and confirm.On the other hand, so strong investment of putting the equipment of too increasing is increased.In order to improve uniformity and the controllability of whole technical process, needing to take measures, reducing Lag effect, can detect accurately etching terminal simultaneously, effectively to prevent structure from spending quarter, guarantee crudy.
In order to suppress Lag effect, at present, general employing regulates etching technics pressure, the isoparametric method of air-flow.But these methods are mainly based on the basis of experiment, and can not eliminate Lag effect completely.
In order to determine whether etching completes, have data to describe structure and inspection method that a kind of judgement is etched to oxide layer, but the method is the MEMS based on soi structure, and there is not silicon dioxide layer in SOG structure, the method cannot be utilized to carry out terminal inspection.At present, determine that the method for etching terminal is, determines the time required for certain etching depth by destructive testing, but the etch rate of ICP is unstable, cannot ensure the repeatability of each etching.
Summary of the invention
In the ICP process of SOG base MEMS, because the existence of Lag effect and etching terminal are difficult to the problem that judges, cause MEMS structure overetch.The present invention proposes a kind of method preventing ICP overetch based on SOG silicon chip.
Technical solution of the present invention is: linear for the multiple rectangle of eating away in the same time and the saturating multiple same live width of etching or different live width composition, in conjunction with the rectangular dimension that graphics chip will etch away and the linear live width that will etch, repartition rectangle, the reticle after utilizing rectangle to repartition carries out photoetching, development and ICP etching to chip.By to the homogenization control of exposed region width and the accurate measurements of etching terminal, effectively solve the problem of ICP overetch.
When the figure of chip comprise etch away multiple rectangle and the saturating multiple same live width composition of etching linear time, concrete steps are as follows:
(1) SOG-MEMS chip to be processed, comprising: supporting layer (1), structure sheaf (2), mask layer (3); Structure sheaf (2) is positioned between mask layer (3) and supporting layer (1), etch multiple anchor point (4) at structure sheaf (2) towards the side of supporting layer (1), between every two anchor points (4), produce isolation channel (5); Supporting layer (1) and structure sheaf (2) are bonded together and carry out thinning to structure sheaf, to required thickness; Mask layer (3) is spin-coated on structure sheaf (2);
(2) when needing the figure by SOG-MEMS chip to be processed, comprise the linear of the multiple rectangle of eating away in the same time and the saturating multiple same live width composition of etching, and the length of side of the most minor face of this rectangle is greater than 2 times of live widths; Wear quarter and refer to saturating structure sheaf at quarter; Each rectangle photolithography plate will carved in multiple rectangle is arranged center non exposed region (12), make the frame of center non exposed region (12) and this rectangle, i.e. outside non exposed region (11), the exposed region (13) that middle formation is to be etched, and the width of exposed region to be etched equals to carve the linear live width of wearing;
Utilize the photolithography plate of this figure to the mask layer of step (1) SOG-MEMS chip to be processed, carry out photoetching, development, mask layer is made by lithography outside non exposed region (11), center non exposed region (12) and exposed region (13), outside non exposed region (11) and center non exposed region (12) are exposed region (13) separately; Structure sheaf under exposed region (13) exposes;
(3) to the structure sheaf that step (2) is exposed from exposed region (13), carry out ICP etching, namely perpendicular to the surface of structure sheaf, etch to supporting layer, until form the raceway groove perpendicular to structure sheaf surface, this raceway groove is communicated with the isolation channel of step (1), center non exposed region (12) on mask layer and the structure sheaf immediately below center non exposed region (12) form hanging structure, hanging structure drops on supporting layer (1), stop etching, now etch simultaneously multiple same live width composition linear under structure sheaf, complete etching.
(4) the SOG-MEMS chip upside down to be processed after step (3) being processed, the hanging structure of step (3) drops, and obtains the SOG-MEMS chip that step (2) needs processing.
When the figure of chip comprise etch away multiple rectangle and the saturating multiple different live width composition of etching linear time, concrete steps are as follows:
(1) SOG-MEMS chip to be processed, comprising: supporting layer (1), structure sheaf (2), mask layer (3); Structure sheaf (2) is positioned between mask layer (3) and supporting layer (1), etch multiple anchor point (4) at structure sheaf (2) towards the side of supporting layer (1), between every two anchor points (4), produce isolation channel (5); Supporting layer (1) and structure sheaf (2) are bonded together and carry out thinning to structure sheaf, to required thickness; Mask layer (3) is spin-coated on structure sheaf (2);
(2) when needing the mask layer by SOG-MEMS chip to be processed, comprise and fall multiple rectangle in the same time and etch the linear of multiple different live width composition, maximum line width in different live width is greater than minimum feature 1 times and is less than or equal to twice, and the length of side of the most minor face of this rectangle is greater than 2 times of the linear middle minimum feature of different live width composition; Wear quarter and refer to that this minimum feature carves structure sheaf; Each rectangle photolithography plate will carved in multiple rectangle is arranged center non exposed region (12), make the frame of center non exposed region (12) and this rectangle, i.e. outside non exposed region (11), the exposed region (13) that middle formation is to be etched, and the width of exposed region to be etched equals to carve the minimum linear live width of wearing;
Utilize this photolithography plate to the mask layer of step (1) SOG-MEMS chip to be processed, carry out photoetching, development, mask layer is made by lithography outside non exposed region (11), center non exposed region (12) and exposed region (13), outside non exposed region (11) and center non exposed region (12) are exposed region (13) separately; Structure sheaf under exposed region (13) exposes;
(3) to the structure sheaf that step (2) is exposed from exposed region (13), carry out ICP etching, namely perpendicular to the surface of structure sheaf, etch to supporting layer, until form the raceway groove perpendicular to structure sheaf surface, this raceway groove is communicated with the isolation channel of step (1), center non exposed region (12) on mask layer and the structure sheaf immediately below center non exposed region (12) form hanging structure, hanging structure drops on supporting layer (1), stop etching, now etch simultaneously multiple same live width composition linear under structure sheaf, complete etching.
(4) the SOG-MEMS chip upside down to be processed after step (3) being processed, the hanging structure of step (3) drops, and obtains the SOG-MEMS chip that step (2) needs processing.
The present invention compared with prior art beneficial effect is:
(1) considered the rectangular dimension needing to etch away in the present invention and needed to etch saturating linear live width, the width of the exposed region needing etching has been unified, prevent produce due to Lag effect in etching process cross problem at quarter;
(2) hanging structure that will etch away the center of rectangular area in the present invention drops on supporting layer (1), stop etching, now etch simultaneously multiple same live width composition linear under structure sheaf, complete etching, there is the judgement utilizing etching terminal, prevent the overetch that continuation increase etch period causes.
(3) adopt SOG structure in the present invention, relative to soi structure and silicon-silicon structure, cost reduces, and meanwhile, adopt anode linkage in the preparation process of SOG structure, para-linkage conditional request is low, improves yield rate.
(4) in the present invention, the height of anchor point (4) is less than the height of hanging structure, and hanging structure drops when supporting layer (1) is upper, transverse shifting can not occur.
Accompanying drawing explanation
Fig. 1 is SOG chip manufacture flow chart in the present invention;
Fig. 2 comprises the linear patterned surface structural representation etching away multiple rectangle and the saturating multiple same live width composition of etching simultaneously in the present invention;
Fig. 3 comprises the linear patterned surface structural representation etching away multiple rectangle and the saturating multiple different live width composition of etching simultaneously in the present invention, Fig. 3 (a) etches away multiple rectangle and the linear patterned surface structural representation etching saturating multiple different live width composition for the first comprises simultaneously, and Fig. 3 (b) etches away the linear patterned surface structural representation that multiple rectangle forms with the saturating multiple different live width of etching for the second comprises simultaneously;
Fig. 4 comprises the linear showing methods process cross sectional representation etching away multiple rectangle and the saturating multiple same live width composition of etching simultaneously in the present invention, Fig. 4 (a) etches away multiple rectangle and the linear showing methods process cross sectional representation etching saturating multiple same live width composition for the first comprises simultaneously, and Fig. 4 (b) etches away the linear showing methods process cross sectional representation that multiple rectangle forms with the saturating multiple same live width of etching for the second comprises simultaneously;
Fig. 5 comprises the linear showing methods process cross sectional representation etching away multiple rectangle and the saturating multiple different live width composition of etching simultaneously in the present invention, Fig. 5 (a) etches away the linear figure first stage process cross sectional representation of multiple rectangle and the saturating multiple different live width composition of etching for comprising in the present invention simultaneously, Fig. 5 (b) etches away the linear figure second stage process cross sectional representation of multiple rectangle and the saturating multiple different live width composition of etching for comprising in the present invention simultaneously, Fig. 5 (c) etches away the linear figure phase III process cross sectional representation of multiple rectangle and the saturating multiple different live width composition of etching for comprising in the present invention simultaneously, Fig. 5 (d) etches away the linear figure fourth stage process cross sectional representation of multiple rectangle and the saturating multiple different live width composition of etching for comprising in the present invention simultaneously, Fig. 5 (d) etches away the linear figure five-stage process cross sectional representation of multiple rectangle and the saturating multiple different live width composition of etching for comprising in the present invention simultaneously,
Fig. 6 is the photoetching of SOG chip of the present invention, each stage schematic diagram of development step; The photoetching of Fig. 6 (a) for SOG chip of the present invention, the first stage schematic diagram of development step, the photoetching of Fig. 6 (b) for SOG chip of the present invention, the second stage schematic diagram of development step, the photoetching of Fig. 6 (c) for SOG chip of the present invention, the phase III schematic diagram of development step, the photoetching of Fig. 6 (d) for SOG chip of the present invention, the fourth stage schematic diagram of development step, 6 (e) is the photoetching of SOG chip of the present invention, the five-stage schematic diagram of development step.
Detailed description of the invention
Basic ideas of the present invention are: the method preventing inductively coupled plasma (ICP) overetch in a kind of SOG (silicon is on glass)-MEMS chip.Linear for the multiple rectangle of eating away in the same time and the saturating multiple same live width of etching or different live width composition, each rectangle photolithography plate will carved in multiple rectangle is arranged center non exposed region 12, make the frame of center non exposed region 12 and this rectangle, i.e. outside non exposed region 11, the exposed region 14 that middle formation is to be etched, and the width of exposed region to be etched equals to carve the minimum linear live width of wearing; The method ensures the homogeneity of etching wide of bar, and solve the problem with Lag effect in the wide structure etching process of different bar, meanwhile, when the etch is completed, center non exposed region 12 can drop on supporting layer 1 below, accurately can judge that etching completes.The present invention effectively prevents having the wide MEMS structure of different etching bar and cause serious overetch in ICP etching.
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail,
Embodiment one: graphics processing comprises the linear chip etching away multiple rectangle and the saturating multiple same live width composition of etching simultaneously.Work flow as shown in Figure 1.
1, the preparation of SOG chip.
SOG structure as shown in Figure 2, comprises supporting layer 1, structure sheaf 2, mask layer 3; Supporting layer 1 is glass material, structure sheaf 2 is silicon materials, mask layer 3 is photoresist.Etch multiple anchor point 4 at silicon layer towards the side of glassy layer, anchor height is generally 5-30um, and in this example, anchor height is set to 10um, and produce isolation channel 5 between every two anchor points 4, silicon chip is linked together by anchor point and sheet glass; Glassy layer and silicon layer be bonded together and utilize chemical-mechanical polisher to carry out thinning to silicon layer, to required thickness, be generally 40-80um, in this example, silicon wafer thickness is 55um, and in the sheet of silicon wafer thickness, uniformity is less than ± 5um; Mask layer photoresist sol evenning machine is spin-coated on structure sheaf silicon.
2, the type of graphics chip is judged.
The figure of this chip comprises simultaneously and etches away the linear of 2 rectangles and etching saturating 16 same live widths composition, and surface texture schematic diagram is as shown in Fig. 3 (a).In figure, white rectangle region is the region etched away, and the length of side of the most minor face of rectangle is 50um, and in red wire frame, the linear width of same live width composition is 3um.The length of side of the most minor face of this rectangle is greater than 2 times of linear live widths.
3, to needing the region etched away split and prepare reticle
Each rectangle in photolithography plate will be carved 2 rectangles is arranged center non exposed region 12, make the frame of center non exposed region 12 and this rectangle, i.e. outside non exposed region 11, the exposed region 13 that middle formation is to be etched, and the width of exposed region to be etched equals the linear live width that will etch, as shown in Fig. 3 (b).And utilize the method for electron beam exposure to prepare the reticle of this figure.The linear width that 2 rectangle exposed areas in figure before repartitioning form much larger than same live width, in ICP process, the rectangular area etch rate that exposed area is larger is fast, about 2um/min, and the less linear etch rate of exposed area is slow, about 1.5um/min, the rectangular area that exposed area is large has first etched, but little linear of exposed area has not etched.When continuing etching little linear of exposed area, can etch further the sidewall of the rectangular area etched, producing the overetch to rectangular area.In figure after repartitioning, the linear exposure width that the width of rectangular shaped rim exposed region is saturating with needing etching is consistent, prevents the problem at quarter excessively due to the generation of Lag effect in etching process;
4, reticle is utilized to carry out photoetching to SOG chip, development
Utilize the photolithography plate in step 3 to the mask layer of step (1) SOG-MEMS chip to be processed, carry out photoetching, development, as shown in Fig. 5 (a), make the rectangular area of mask layer by lithography outside non exposed region 11, center non exposed region 12 and exposed region 13, outside non exposed region 11 and center non exposed region 12 are exposed region 13 separately; Structure sheaf under exposed region 13 exposes;
5, ICP etching is carried out to exposed region
The Bosch technique that etching/passivation hockets is adopted to carry out dark silicon etching in this example.This technique can obtain high etch rate and anisotropy.Sulfur hexafluoride (SF is adopted in etching process
6) as etching gas, octafluoroization four carbon (C
4f
8) as protective gas.C
4f
8issue solution estranged in plasmoid, and react with silicon face, form (CF
2)
npassivating film.SF
6the F produced
-etch away passivating film, and form escaping gas CF
x, then carry out silicon materials etching, produce escaping gas SiF
x.As shown in Fig. 5 (b).
The reaction equation of passivating process is as follows:
C
4F
8↑→4CF
2↑(1)
n×CF
2↑→(CF
2)n(2)
The reaction equation of etching process is as follows:
SF
6↑→SxFy↑+SxFy+↑+F
-↑(3)
(CF
2)n+F
-↑→CFx↑(4)
Si+F
-→SiFx↑(5)
Etch process parameters is as shown in table 1.In etching process, pass into a certain proportion of oxygen, like this, in etching process, exposed silicon is out oxidized under the irradiation of oxygen plasma, forms skim silica oxide layer, like this, and silica and passivating film (CF
2)
nform double shielding at sidewall silicon, improve the perpendicularity of etching structure.Use these process conditions can obtain depth-to-width ratio and be greater than 20, the structure of verticality of side wall up to 89.9 °, can effectively improve MEMS performance.
Table 1ICP etch process parameters
| Parameter | Etching | Passivation |
| Gas flow [sccm] | 125SF 6/14O 2 | 80C 4F 8 |
| Process time [s] | 10 | 5 |
| Gas pressure [mTorr] | 5 | 3 |
| Upper electrode power [W] | 600 | 600 |
| Lower electrode power [W] | 14 | Off |
| Temperature [DEG C] | 20 | 20 |
6, ICP etching terminal detects
The time required for etching is calculated according to etch rate and silicon wafer thickness.In this example, silicon wafer thickness is 40um, and etch rate is 1.5um/min, therefore the etch period needed is approximately 30min.After time to be etched to 30min, take out chip, multiplication factor is utilized to be the microscope of 500 times, focus on the hanging structure in rectangular area under non exposed region in chip, if there is difference in height between the non-exposed region field surface of the surface of hanging structure and rectangular shaped rim, illustrate that the hanging structure in rectangular area under non exposed region drops, determine that etching completes, as shown in Fig. 5 (c).If there is not difference in height between the non-exposed region field surface of the surface of hanging structure and rectangular shaped rim, illustrate that the hanging structure in rectangular area under non exposed region does not drop, etching does not complete, need to continue again to increase etch period, but now etch period general control is in 1-3min, takes out chip and again use microscopic examination, repeatedly carry out etching-observe step, prevent because too much increase etch period causes overetch.
7, by chip upside down, hanging structure is dropped
The chip etched, the hanging structure in rectangular area under non exposed region has dropped on supporting layer glass.Due to the height 10um of anchor point, be less than the height 45um of hanging structure, the hanging structure dropped on glassy layer can not laterally be moved.By the chip upside down after having etched, hanging structure drops under gravity, as shown in Fig. 5 (d).The final graphic chips obtaining needs.
Embodiment two: graphics processing comprises simultaneously and etches away multiple rectangle and the linear chip etching multiple different live width composition.
Work flow as shown in Figure 1.
1, the preparation of SOG chip is with embodiment one;
2, the type of graphics chip is judged.
The figure of this chip comprises simultaneously and etches away the linear of 4 rectangles and etching saturating 16 different live widths composition, and surface texture schematic diagram is as shown in Fig. 4 (a).In figure, white rectangle region is the region etched away, the minimum length of side of rectangle is 45um, region in red wire frame is the linear of different live width composition, live width in a of region is minimum, is 3um, and the live width in the b of region is 4um, live width in the b of region is 5um, live width in the c of region is 5um, and the live width in the d of region is maximum, is 6um.The length of side of the most minor face of this rectangle is greater than 2 times of linear live width 6um.
3, to needing the region etched away split and prepare reticle
In this figure, the division methods of rectangular area is identical with embodiment one.The center non exposed region 12 of rectangular area and the frame of this rectangle is with the difference in embodiment one, i.e. outside non exposed region 11, the exposed region 13 that middle formation is to be etched, and the width of exposed region to be etched equals the minimum linear live width that will etch, as shown in Fig. 4 (b), 4 rectangles in figure are all repartitioned.Other linear width of different live width are greater than 1 times and are less than 2 times of minimum feature, cannot repartition.But because the linear width difference of different live width is less, in ICP etching process, etch rate difference is not obvious, therefore, linear of different live width introduce due to Lag effect cross problem not serious at quarter.
4, identical with embodiment one of the photoetching of SOG chip, development step, as shown in Fig. 6 (a).
5, ICP etching is carried out to exposed region
Identical with embodiment one of etching principle and technological parameter.In etching process, larger linear of exposed region width first etches silicon structural layer, then increases etch period 3-5min, and minimum linear of the exposed region 13 in rectangular area and live width etch saturating simultaneously, and etching process is as shown in Fig. 6 (b).
What 6, ICP etching terminal detected with embodiment one is identical, as shown in Fig. 6 (c).
7, by chip upside down, what make hanging structure drop with embodiment one is identical, as Fig. 6 (d), 6
Shown in (e).
Embodiment three: the chip processing other linear structures
Linear structure can be H-shaped, and also can be other shape, linear end can be rectangle, also can be circular arc.These structures are all widely used in MEMS.
All the other steps are with embodiment one.
Non-elaborated part of the present invention belongs to techniques well known.
Claims (10)
1. prevent a method for ICP overetch in SOG-MEMS chip, it is characterized in that: step is as follows:
(1) SOG-MEMS chip to be processed, comprising: supporting layer (1), structure sheaf (2), mask layer (3); Structure sheaf (2) is positioned between mask layer (3) and supporting layer (1), etch multiple anchor point (4) at structure sheaf (2) towards the side of supporting layer (1), between every two anchor points (4), produce isolation channel (5); Supporting layer (1) and structure sheaf (2) are bonded together and carry out thinning to structure sheaf, to required thickness; Mask layer (3) is spin-coated on structure sheaf (2);
(2) when needing the figure by SOG-MEMS chip to be processed, comprise the linear of the multiple rectangle of eating away in the same time (6) and the saturating multiple same live width composition of etching, and the length of side of the most minor face of this rectangle is greater than 2 times of live widths; Etching refers to thoroughly carves saturating structure sheaf; Each rectangle photolithography plate will carved in multiple rectangle is arranged center non exposed region (12), make the frame of center non exposed region (12) and this rectangle, i.e. outside non exposed region (11), the exposed region (13) that middle formation is to be etched, and the width of exposed region to be etched equals to carve the linear live width of wearing;
Utilize the photolithography plate of this figure to the mask layer of step (1) SOG-MEMS chip to be processed, carry out photoetching, development, mask layer is made by lithography outside non exposed region (11), center non exposed region (12) and exposed region (13), outside non exposed region (11) and center non exposed region (12) are exposed region (13) separately; Structure sheaf under exposed region (13) exposes;
(3) to the structure sheaf that step (2) is exposed from exposed region (13), carry out ICP etching, namely perpendicular to the surface of structure sheaf, etch to supporting layer, until form the raceway groove perpendicular to structure sheaf surface, this raceway groove is communicated with the isolation channel of step (1), center non exposed region (12) on mask layer and the structure sheaf immediately below center non exposed region (12) form hanging structure, hanging structure drops on supporting layer (1), stop etching, now etch simultaneously multiple same live width composition linear under structure sheaf, complete etching,
(4) the SOG-MEMS chip upside down to be processed after step (3) being processed, the hanging structure of step (3) drops, and obtains the SOG-MEMS chip that step (2) needs processing.
2. prevent the method for ICP overetch in a kind of SOG-MEMS chip according to claim 1, it is characterized in that: described supporting layer (1) is glassy layer, structure sheaf (2) is silicon layer, and mask layer (3) is photoresist.
3. a kind of method preventing overetch in etching process according to claim 1, it is characterized in that: the anchor point (4) of described chip directly can be connected with outside non exposed region (11), also indirectly can be connected by other outside non exposed region, the height of anchor point is less than the height of hanging structure.
4. a kind of method preventing overetch in etching process according to claim 1, it is characterized in that: in described step (3), after etching into the scheduled time, chip is taken out, be placed on basis of microscopic observation, if find that the structure of hanging structure and outside non exposed region (11) exists difference in height, and lower than the structure of periphery, show that etching is complete.
5. a kind of method preventing overetch in etching process according to claim 1, it is characterized in that: when the height of anchor point (4), namely when hanging structure drops on supporting layer, when difference in height between hanging structure upper surface and chip upper surface is 5-80um, described microscope is be greater than the metallographic microscope of 500 times, can determine the height difference on different structure surface by observing focusing surface.
6. prevent a method for ICP overetch in SOG-MEMS chip, it is characterized in that: step is as follows:
(1) SOG-MEMS chip to be processed, comprising: supporting layer (1), structure sheaf (2), mask layer (3); Structure sheaf (2) is positioned between mask layer (3) and supporting layer (1), etch multiple anchor point (4) at structure sheaf (2) towards the side of supporting layer (1), between every two anchor points (4), produce isolation channel (5); Supporting layer (1) and structure sheaf (2) are bonded together and carry out thinning to structure sheaf, to required thickness; Mask layer (3) is spin-coated on structure sheaf (2);
(2) when needing the mask layer by SOG-MEMS chip to be processed, comprise and fall multiple rectangle in the same time and etch the linear of multiple different live width composition, maximum line width in different live width is greater than minimum feature 1 times and is less than or equal to twice, and the length of side of the most minor face of this rectangle is greater than 2 times of the linear middle minimum feature of different live width composition; Etching refers to that this minimum feature carves structure sheaf thoroughly; Each rectangle photolithography plate will carved in multiple rectangle is arranged center non exposed region (12), make the frame of center non exposed region (12) and this rectangle, i.e. outside non exposed region (11), the exposed region (14) that middle formation is to be etched, and the width of exposed region to be etched equals to carve the minimum linear live width of wearing;
Utilize this photolithography plate to the mask layer of step (1) SOG-MEMS chip to be processed, carry out photoetching, development, mask layer is made by lithography outside non exposed region (11), center non exposed region (12) and exposed region (13), outside non exposed region (11) and center non exposed region (12) are exposed region (13) separately; Structure sheaf under exposed region (13) exposes;
(3) to the structure sheaf that step (2) is exposed from exposed region (13), carry out ICP etching, namely perpendicular to the surface of structure sheaf, etch to supporting layer, until form the raceway groove perpendicular to structure sheaf surface, this raceway groove is communicated with the isolation channel of step (1), center non exposed region (12) on mask layer and the structure sheaf immediately below center non exposed region (12) form hanging structure, hanging structure drops on supporting layer (1), stop etching, now etch simultaneously multiple same live width composition linear under structure sheaf, complete etching,
(4) the SOG-MEMS chip upside down to be processed after step (3) being processed, the hanging structure of step (3) drops, and obtains the SOG-MEMS chip that step (2) needs processing.
7. prevent the method for ICP overetch in a kind of SOG-MEMS chip according to claim 6, it is characterized in that: described supporting layer (1) is glassy layer, structure sheaf (2) is silicon layer, and mask layer (3) is photoresist.
8. a kind of method preventing overetch in etching process according to claim 6, it is characterized in that: the anchor point (4) of described chip directly can be connected with outside non exposed region (11), also indirectly can be connected by other outside non exposed region, the height of anchor point is less than the height of hanging structure.
9. a kind of method preventing overetch in etching process according to claim 6, it is characterized in that: in described step (3), after etching into the scheduled time, chip is taken out, be placed on basis of microscopic observation, if find that the structure of hanging structure and outside non exposed region (11) exists difference in height, show that etching is complete.
10. a kind of method preventing overetch in etching process according to claim 6, it is characterized in that: when the height of anchor point (4), namely when hanging structure drops on supporting layer, when difference in height between hanging structure upper surface and chip upper surface is 5-80um, described microscope is be greater than the metallographic microscope of 500 times, can determine the height difference on different structure surface by observing focusing surface.
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| CN111006182A (en) * | 2018-10-04 | 2020-04-14 | Zkw集团有限责任公司 | Projection arrangement for a light module of a motor vehicle headlight and method for producing a projection arrangement |
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| US20080099436A1 (en) * | 2006-10-30 | 2008-05-01 | Michael Grimbergen | Endpoint detection for photomask etching |
| CN102508203A (en) * | 2011-11-17 | 2012-06-20 | 西北工业大学 | Novel MEMS (microelectromechanical systems) bionic acoustic vector sensor and manufacturing method thereof |
| CN104211010A (en) * | 2013-06-03 | 2014-12-17 | 中国科学院微电子研究所 | Etching method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080099436A1 (en) * | 2006-10-30 | 2008-05-01 | Michael Grimbergen | Endpoint detection for photomask etching |
| CN102508203A (en) * | 2011-11-17 | 2012-06-20 | 西北工业大学 | Novel MEMS (microelectromechanical systems) bionic acoustic vector sensor and manufacturing method thereof |
| CN104211010A (en) * | 2013-06-03 | 2014-12-17 | 中国科学院微电子研究所 | Etching method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111006182A (en) * | 2018-10-04 | 2020-04-14 | Zkw集团有限责任公司 | Projection arrangement for a light module of a motor vehicle headlight and method for producing a projection arrangement |
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