CN102543667A - Forming method of graph of aligned layer on silicon chip - Google Patents
Forming method of graph of aligned layer on silicon chip Download PDFInfo
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- CN102543667A CN102543667A CN2010105782628A CN201010578262A CN102543667A CN 102543667 A CN102543667 A CN 102543667A CN 2010105782628 A CN2010105782628 A CN 2010105782628A CN 201010578262 A CN201010578262 A CN 201010578262A CN 102543667 A CN102543667 A CN 102543667A
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Abstract
The invention discloses a forming method of a graph of an aligned layer on a silicon chip. Compared with the prior art, the forming method is characterized in that the steps of secondary photoetching and etching are omitted, and a way of performing low-temperature pretreatment on the silicon chip is adopted in the forming method, so that the single contrast of the graph of an overlay target of the graph of the aligned layer is enhanced, and the graph is easier and clearer to be recognized.
Description
Technical field
The present invention relates in a kind of photoetching process by the formation method of alignment figure.
Background technology
Photoetching is the technical process that the circuit structure of the last graphic form of mask (mask) is transferred to the silicon chip surface that scribbles photoresist through steps such as aligning, exposure, developments.Photoetching process can form one deck photoresist masking figure (litho pattern) at silicon chip surface, and its subsequent technique is that etching or ion inject.
The manufacturing of any semiconductor device all comprises the photoetching process of multistep; Except that first step photoetching; The litho pattern of current layer all will be measured with the alignment precision of being undertaken by the alignment figure of anterior layer during later per step photoetching, guarantees between the multistep photoetching aligning of figure on the silicon chip.Said by alignment figure silicon slice pattern normally, all to form overlay mark at each layer on by the alignment figure.
See also Fig. 1, at present, in technologies such as CMOS, germanium silicon (SiGe), BCD (Bipolar CMOS DMOS), EEPROM, formation is comprised the steps: by the method for alignment figure
In the 1st step, deposit one deck first dielectric layer 11 is generally silicon nitride on substrate 10.
The 2nd step, adopt photoetching and etching technics on substrate 10, to etch groove 12, etching is accomplished back removal photoresist, and in the bottom of groove 12 and the sidewall one deck cushion oxide layer (Liner Oxide) 13 of growing.Groove 12 is as the overlay mark of this layer pattern on the silicon chip, and this overlay mark possibly be a kind of lines or shape (like square annular, cross etc.) from the silicon chip vertical view, but is exactly groove from the silicon chip cutaway view.By the alignment figure is the silicon slice pattern that on the overlay mark basis, forms.Etching groove 12 can adopt shallow-trench isolation (STI, shallow trench insulation) technology.
The 3rd step at silicon chip surface deposit one deck second dielectric layer 14, was generally silica, and filling to major general's groove 12 expires.
In the 4th step, adopt direct chemical mechanical lapping (DCMP, Direct Chemical MechanicalPlanarization) technology to grind second dielectric layer 14, until the flush of second dielectric layer 14 and first dielectric layer 11.Have only this moment and be filled with second dielectric layer 14 in the groove 12.
In the 5th step, remove first dielectric layer 11 with hot phosphoric acid with wet corrosion technique.
The 6th step, adopt photoetching and etching technics on substrate 10, to etch groove 15 once more, the position of groove 15 overlaps with groove 12 fully, but the degree of depth of groove 15 is less than groove 12.Why will carry out etching once more to overlay mark (being groove 12 positions) once more, be to be identified more easily and to measure in order to make by the edge of alignment figure.
The 7th step at silicon chip surface deposit one deck the 3rd dielectric layer 16, can be any of polysilicon, germanium silicon (SiGe), carbon germanium silicon (SiGeC).The 3rd dielectric layer 16 is used to form a new layer pattern as the material of a layer pattern new on the silicon chip.The 3rd dielectric layer 16 is exactly by the alignment figure, and this moment, the upper surface of the 3rd dielectric layer 16 recessed step conduct occurred by the overlay mark of alignment figure at groove 15 corresponding positions, and this is a benchmark of measuring alignment precision.
In the 8th step,, adopt photoetching process to form new one deck litho pattern at silicon chip surface spin coating photoresist 17.
At this moment, the current layer figure just need and be carried out the measurement of alignment precision between the alignment figure.Usually the method for measuring alignment precision is: measure current layer figure (promptly forming the photoresist 17 of new one deck litho pattern) edge and by the distance between alignment figure (i.e. the recessed ledge frame of the 3rd dielectric layer 16 upper surfaces) edge, calculate alignment precision again.
By the formation method of alignment figure, need carry out Twi-lithography technology on the above-mentioned silicon chip, this has increased the cost of technology, and makes manufacturing time longer.
Summary of the invention
Technical problem to be solved by this invention provides on a kind of silicon chip by the formation method of alignment figure, compares the step that can reduce a photoetching and etching with conventional method.
For solving the problems of the technologies described above, comprised the steps: by the formation method of alignment figure on the silicon chip of the present invention
The 1st step, deposit one deck first dielectric layer on substrate;
The 2nd step, adopt photoetching and etching technics on substrate, to etch groove, etching is accomplished back removal photoresist, and in the bottom of groove and sidewall one deck cushion oxide layer of growing; Said groove is as the overlay mark of this layer pattern on the silicon chip;
The 3rd step,, full to the said trench fill of major general at silicon chip surface deposit one deck second dielectric layer;
In the 4th step, adopt the direct chemical mechanical milling tech to grind said second dielectric layer, until the flush of said second dielectric layer and said first dielectric layer.Have only this moment and be filled with said second dielectric layer in the said groove;
In the 5th step, remove said first dielectric layer with wet corrosion technique;
In the 6th step, silicon chip is carried out the low temperature preliminary treatment;
The 7th step, earlier silicon chip is carried out preliminary treatment, for example carry out 1045～1055 ℃ preliminary drying.Again at silicon chip surface deposit one deck the 3rd dielectric layer, said the 3rd dielectric layer as one deck new on the silicon chip by the material of alignment figure; This moment, the upper surface of said the 3rd dielectric layer recessed step conduct occurred by the overlay mark of alignment figure at the corresponding position of said groove;
In the 8th step,, adopt photoetching process to form new one deck litho pattern at silicon chip surface spin coating photoresist.
On the silicon chip of the present invention by the formation method of alignment figure; Can let and strengthened by the contrast of the figure signal of the overlay mark on the alignment figure; Thereby can be more easily, more clearly recognized, and compare the step of having omitted photoetching for the second time and etching with existing method.This method is also applicable in the technologies such as CMOS, germanium silicon, BCD, EEPROM.
Description of drawings
Fig. 1 is existing by each step sketch map of the formation method of alignment figure;
Fig. 2 is that the present invention is by each step sketch map of the formation method of alignment figure.
Description of reference numerals among the figure:
10 is substrate; 11 is first dielectric layer; 12 is groove; 13 is cushion oxide layer; 14 is second dielectric layer; 15 is groove; 16 is the 3rd dielectric layer; 17 is photoresist.
Embodiment
See also Fig. 2, comprised the steps: by the formation method of alignment figure on the silicon chip of the present invention
In the 1st step, deposit one deck first dielectric layer 11 on substrate 10 for example is a silicon nitride.
The 2nd step, adopt photoetching and etching technics on substrate 10, to etch groove 12, etching is accomplished back removal photoresist, and in the bottom of groove 12 and the sidewall one deck cushion oxide layer (Liner Oxide) 13 of growing.Etching groove 12 can adopt shallow-trench isolation (STI) technology.
The 3rd step at silicon chip surface deposit one deck second dielectric layer 14, for example was a silica, and filling to major general's groove 12 expires.
In the 4th step, adopt direct chemical mechanical lapping (DCMP) technology to grind second dielectric layer 14, until the flush of second dielectric layer 14 and first dielectric layer 11.Have only this moment and be filled with second dielectric layer 14 in the groove 12.
In the 5th step, remove first dielectric layer 11 with wet corrosion technique.When first dielectric layer 11 is silicon nitride, adopt hot phosphoric acid soup.
The 6th step, silicon chip is carried out the low temperature preliminary treatment, for example silicon chip being carried out temperature is 865～875 ℃ preliminary drying.Existing method also need be carried out preliminary treatment to silicon chip before deposit the 3rd dielectric layer 16, promptly carry out 1045～1055 ℃ preliminary drying.Pretreatment temperature is starkly lower than existing method among the application, therefore is called " low temperature " preliminary treatment.
The 7th step at silicon chip surface deposit one deck the 3rd dielectric layer 16, for example was any one of polysilicon, germanium silicon, carbon germanium silicon.The 3rd dielectric layer 16 is used to form new one deck silicon slice pattern as the material of a layer pattern new on the silicon chip.The 3rd dielectric layer 16 is exactly by the alignment figure, and this moment, the upper surface of the 3rd dielectric layer 16 recessed step conduct occurred by the overlay mark of alignment figure at groove 15 corresponding positions, and this is a benchmark of measuring alignment precision.
In the 8th step,, adopt photoetching process to form new one deck litho pattern at silicon chip surface spin coating photoresist 17.
Said the 3rd dielectric layer 16 is deposited on the silicon chip, and the 3rd dielectric layer 16 can be the material that germanium silicon, germanium silicon-carbon etc. contain Ge element, and interface between the two is the interface of heterojunction.Under high temperature (as 1050 ℃), react easily between the two, and high temperature can cause phenomenons such as diffusion of impurities, lattice dislocation, thereby influence the surface topography of overlay mark.Under low temperature (as 870 ℃), just react not too easily between the two, the surface topography of overlay mark just can be kept preferably.
On the silicon chip of the present invention by the formation method of alignment figure; Can let and strengthened by the contrast of the figure signal of the overlay mark on the alignment figure; Thereby can be more easily, more clearly recognized, and compare with existing method and to have omitted a photoetching and etch step.
Claims (5)
- On the silicon chip by the formation method of alignment figure, it is characterized in that, comprise the steps:The 1st step, deposit one deck first dielectric layer on substrate;The 2nd step, adopt photoetching and etching technics on substrate, to etch groove, etching is accomplished back removal photoresist, and in the bottom of groove and sidewall one deck cushion oxide layer of growing; Said groove is as the overlay mark of this layer pattern on the silicon chip;The 3rd step,, full to the said trench fill of major general at silicon chip surface deposit one deck second dielectric layer;In the 4th step, adopt the direct chemical mechanical milling tech to grind said second dielectric layer, until the flush of said second dielectric layer and said first dielectric layer.Have only this moment and be filled with said second dielectric layer in the said groove;In the 5th step, remove said first dielectric layer with wet corrosion technique;In the 6th step, silicon chip is carried out the low temperature preliminary treatment;The 7th step, earlier silicon chip is carried out preliminary treatment, for example carry out 1045～1055 ℃ preliminary drying.Again at silicon chip surface deposit one deck the 3rd dielectric layer, said the 3rd dielectric layer as one deck new on the silicon chip by the material of alignment figure; This moment, the upper surface of said the 3rd dielectric layer recessed step conduct occurred by the overlay mark of alignment figure at the corresponding position of said groove;In the 8th step,, adopt photoetching process to form new one deck litho pattern at silicon chip surface spin coating photoresist.
- 2. by the formation method of alignment figure, it is characterized in that on the silicon chip according to claim 1 that said method is in the 6th step, saidly silicon chip is carried out the low temperature preliminary treatment be meant that it is 865～875 ℃ preliminary drying that silicon chip is carried out temperature.
- 3. by the formation method of alignment figure, it is characterized in that on the silicon chip according to claim 1 that said first dielectric layer is a silicon nitride.
- 4. by the formation method of alignment figure, it is characterized in that on the silicon chip according to claim 1 that said second dielectric layer is a silica.
- 5. by the formation method of alignment figure, it is characterized in that said the 3rd dielectric layer or germanium silicon or carbon germanium silicon on the silicon chip according to claim 1.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104181016A (en) * | 2013-05-22 | 2014-12-03 | 上海华虹宏力半导体制造有限公司 | Physical analysis method for positioning deep trench bottom of deep trench product |
| CN104655006A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting alignment between device graph on front face of wafer and back hole on back face |
| CN104765254A (en) * | 2015-04-29 | 2015-07-08 | 上海华虹宏力半导体制造有限公司 | Overlay alignment mark |
| CN112216604A (en) * | 2020-10-10 | 2021-01-12 | 上海威固信息技术股份有限公司 | High-security packaging method and device for memory chip |
| CN117410173A (en) * | 2023-12-15 | 2024-01-16 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
| WO2024060361A1 (en) * | 2022-09-20 | 2024-03-28 | 中国科学院光电技术研究所 | Alignment mark structure and forming method therefor |
| US11984406B2 (en) | 2020-03-30 | 2024-05-14 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for manufacturing same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1329357A (en) * | 2000-06-08 | 2002-01-02 | 株式会社东芝 | Aligning method, alignment checking method and photomask |
| CN1458667A (en) * | 2002-05-17 | 2003-11-26 | 台湾积体电路制造股份有限公司 | Method for producing alignment mark |
| US20040115878A1 (en) * | 2002-12-13 | 2004-06-17 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for manufacturing a silicon germanium based device with crystal defect prevention |
| CN101201544A (en) * | 2006-12-11 | 2008-06-18 | 上海华虹Nec电子有限公司 | Semiconductor photolithography method |
-
2010
- 2010-12-08 CN CN201010578262.8A patent/CN102543667B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1329357A (en) * | 2000-06-08 | 2002-01-02 | 株式会社东芝 | Aligning method, alignment checking method and photomask |
| CN1458667A (en) * | 2002-05-17 | 2003-11-26 | 台湾积体电路制造股份有限公司 | Method for producing alignment mark |
| US20040115878A1 (en) * | 2002-12-13 | 2004-06-17 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for manufacturing a silicon germanium based device with crystal defect prevention |
| CN101201544A (en) * | 2006-12-11 | 2008-06-18 | 上海华虹Nec电子有限公司 | Semiconductor photolithography method |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104181016A (en) * | 2013-05-22 | 2014-12-03 | 上海华虹宏力半导体制造有限公司 | Physical analysis method for positioning deep trench bottom of deep trench product |
| CN104181016B (en) * | 2013-05-22 | 2016-11-02 | 上海华虹宏力半导体制造有限公司 | The Physical Analysis Methods of the location, deep trench bottom of deep trench product |
| CN104655006A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting alignment between device graph on front face of wafer and back hole on back face |
| CN104655006B (en) * | 2013-11-19 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | The detection method that the component graphics of wafer frontside are aligned with the dorsal pore at the back side |
| CN104765254A (en) * | 2015-04-29 | 2015-07-08 | 上海华虹宏力半导体制造有限公司 | Overlay alignment mark |
| US11984406B2 (en) | 2020-03-30 | 2024-05-14 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for manufacturing same |
| CN112216604A (en) * | 2020-10-10 | 2021-01-12 | 上海威固信息技术股份有限公司 | High-security packaging method and device for memory chip |
| CN112216604B (en) * | 2020-10-10 | 2021-04-02 | 上海威固信息技术股份有限公司 | Packaging method and device for improving safety of memory chip |
| WO2024060361A1 (en) * | 2022-09-20 | 2024-03-28 | 中国科学院光电技术研究所 | Alignment mark structure and forming method therefor |
| CN117410173A (en) * | 2023-12-15 | 2024-01-16 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
| CN117410173B (en) * | 2023-12-15 | 2024-03-08 | 中晶新源(上海)半导体有限公司 | Manufacturing method of trench semiconductor device with stepped dielectric layer |
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