CN104181016A - Physical analysis method for positioning deep trench bottom of deep trench product - Google Patents
Physical analysis method for positioning deep trench bottom of deep trench product Download PDFInfo
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- CN104181016A CN104181016A CN201310192500.5A CN201310192500A CN104181016A CN 104181016 A CN104181016 A CN 104181016A CN 201310192500 A CN201310192500 A CN 201310192500A CN 104181016 A CN104181016 A CN 104181016A
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Abstract
The invention discloses a physical analysis method for positioning deep trench bottom of a deep trench product. the method comprises the following steps: an analytical trench graph is defined on a mask plate for defining an analytical trench graph while a deep trench and an analytical trench are formed by etching; the analytical trench is filled with a dielectric layer; the deep trench is filled with a silicon epitaxy layer; a deep trench product is formed; an analytical sample is prepared; the analytical sample is grounded and the deep trench bottom is found; the depth of the deep trench is positioned by the utilization of the characteristic that the dielectric layer filled in the analytical trench can directly be distinguished from silicon visually during the grinding process; and the positioned deep trench bottom undergoes physical analysis. According to the invention, accurate positioning of the deep trench bottom can be realized during the preparation process of the analytical sample. Thus, the problem of structural analysis and failure analysis of a deep trench product in sample preparation is solved, product quality can be raised, and the technology can be improved.
Description
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit) method of manufacturing technology, particularly relate to a kind of Physical Analysis Methods of location, deep trench bottom of deep trench product.
Background technology
Deep trench product comprises the high tension apparatus such as super-junction device, and deep trench product all needs to use deep trench processes.As shown in Figure 1A, be the deep groove structure schematic diagram of existing deep trench product; In existing deep trench processes, need first on silicon substrate 101, to adopt chemical wet etching technique to form deep trench 102, the degree of depth of deep trench 102, according to device performance needs, can reach tens of microns.As shown in Figure 1B, be the structural representation after the deep trench of existing deep trench product is filled; In deep trench 102, fill afterwards silicon layer 103, the doping type of silicon layer 103 and silicon substrate 101 is contrary, and as when silicon substrate 101 adulterates for N-type, silicon layer 103 is the doping of P type.By deep trench processes, can on silicon substrate 101, form like this structure of P type thin layer and the arrangement of N-type interlaminate.
The impact of particular importance is arranged product performance at the deep trench bottom of above-mentioned deep trench product: 1, deep trench bottom is the terminal of etching, the starting point that silicon is filled, important PN junction physical connection face.2, deep trench bottom is the most easily to cause contamination, particle residue, stress relief etc.So it is extremely important that physics when deep trench bottom is carried out conventional physical features monitoring or lost efficacy is resolved (as tem analysis etc.).Because the main material inside and outside groove is all silicon, when needs are monitored channel bottom situation, the sample preparation in the time of can be to correlation analysis brings very large difficulty:
When 1, section SEM observes, often need to add chemical staining to process, just can observe bottom; Chemical staining can destroy the features such as initial pattern of channel bottom simultaneously, and this can cause seeing the primitive character of channel bottom.
2,, during tem analysis, need to prepare applicable thin slice sample.The use degree of depth of traditional direct FIB sample preparation is below several microns, cannot realize bottom and observe.If sample is ground to delamination to be processed, being difficult to judgement sample has been processed near deep trench bottom position, as shown in Figure 1 C, because silicon layer 103 and silicon substrate 101 are silicon material entirely, in fact in process of lapping, visually silicon layer 103 and silicon substrate 101 cannot be made a distinction, therefore have no idea to judge the degree of depth of silicon layer 103 in process of lapping.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of Physical Analysis Methods of location, deep trench bottom of deep trench product, can in analytic sample preparation process, realize the accurate location to deep trench low side, thereby can solve the structure analysis of deep trench product, a difficult problem for sample preparation that failure analysis is, and can bring the quality of product to promote and process improving.
For solving the problems of the technologies described above, the Physical Analysis Methods of location, the deep trench bottom of deep trench product provided by the invention comprise the steps:
Step 1, when layout design and mask plate are tailor-made, on the mask plate one of the deep trench figure of definition deep trench product, define analysis groove figure.
Step 2, utilize the definition of described mask plate one, adopt the chip region of chemical wet etching technique on silicon chip to form the deep trench of deep trench product, the scribe line district on described silicon chip forms and analyzes groove simultaneously; The width of described analysis groove and described deep trench is identical; Overlook on face, described chip region is rectangle or square, and described analysis groove is arranged on the side of one or more in the four edges of described chip region, and the length of described analysis groove equals the length on limit of described chip region of place side and parallel with this limit; On section, the top width of described analysis groove is even, and the bottom of described analysis groove is a radian and bottom width can be from the size reduction to 0 of top width.
Step 3, in described analysis groove filled media layer, in described deep trench, do not form described dielectric layer; The material requirements of described dielectric layer cannot form silicon epitaxy layer at its top, and the thickness requirement of described dielectric layer at least will fill up the bottom of described analysis groove completely.
Step 4, employing epitaxy technique are filled full silicon epitaxy layer in described deep trench, and are formed described deep trench product.
Step 5, described deep trench product is analyzed, is comprised step by step:
Step 51, prepare analytic sample, by cutting into slices and form described analytic sample being formed with the silicon chip of described deep trench product, this analytic sample comprises the described analysis groove of He Gai chip region, a chip region to be analyzed week side.
Step 52, described analytic sample is ground and is found the bottom of described deep trench, utilize the described dielectric layer of filling in described analysis groove to the degree of depth of described deep trench, to position with the characteristic of silicon direct vision difference, when described analysis groove arrives bottom, at the width of overlooking the described dielectric layer of the above analysis groove of face, can dwindle, and described in during the closer to lowermost end, the reduced width of dielectric layer is more obvious, utilize the obvious characteristic of reduced width of described dielectric layer to judge that described analytic sample has been ground to the bottom of described analysis groove, because the bottom degree of depth of described deep trench is identical with the bottom degree of depth of described analysis groove, by drawing horizontal line mode to position the bottom of described deep trench from the bottom of described analysis groove.
Step 53, physical analysis is carried out in the bottom of the described deep trench of having good positioning.
Further improving is that dielectric layer described in step 3 fills up described analysis groove completely; Thereby in described analysis groove, forming protective seam during filled media layer in described chip region makes described deep trench not form described dielectric layer.
Further improving is that the material of described dielectric layer is monox or silicon nitride.
Further improving is by optical microscope or scanning electron microscope, to come observation post to state the width of dielectric layer in step 52.
Further improving is, in step 53, the physical analysis of the bottom of the described deep trench of having good positioning is comprised to tem analysis.
The present invention passes through at all side settings of chip region analysis groove identical with deep trench width and in analyzing groove filled media layer, can utilize the characteristic of dielectric layer energy and the difference of silicon direct vision to realize with the bottom of analyzing location, the bottom deep trench of groove, can in analytic sample preparation process, realize the accurate location to deep trench low side, thereby can solve the structure analysis of deep trench product, a difficult problem for the sample preparation that failure analysis is, thereby can realize, the lower surface of deep trench is carried out to the most true physical analysis, and can bring the quality of product to promote and process improving.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Figure 1A is the deep groove structure schematic diagram of existing deep trench product;
Figure 1B is the structural representation after the deep trench of existing deep trench product is filled;
Fig. 1 C is the structural representation that the actual observation of Figure 1B is arrived;
Fig. 2 is embodiment of the present invention method flow diagram;
Fig. 3 A is the vertical view of deep trench after forming in embodiment of the present invention method;
Fig. 3 B is the partial enlarged drawing in Fig. 3 A;
Fig. 4 A is the sectional view along AA ' in Fig. 3 B;
Fig. 4 B is the sectional view after the analysis trench fill dielectric layer in Fig. 4 A;
Fig. 4 C is that the deep trench in Fig. 4 B is filled the sectional view after silicon epitaxy layer;
Fig. 5 A is the bottom judgement schematic diagram of deep trench in the embodiment of the present invention;
Fig. 5 B is the structural representation that the actual observation of Fig. 5 A is arrived;
Fig. 5 C carries out from surface, approaching in process of lapping the monitoring schematic diagram of deep trench bottom to analytic sample in the embodiment of the present invention.
Embodiment
As shown in Figure 2, be embodiment of the present invention method flow diagram; The Physical Analysis Methods of deep trench 5 location, bottom of embodiment of the present invention deep trench product comprise the steps:
Step 1, when layout design and mask plate are tailor-made, on the mask plate one of the deep trench figure of definition deep trench product, define analysis groove figure.
Step 2, is as shown in Figure 3A the vertical view of deep trench after forming in embodiment of the present invention method; Fig. 3 B is that the partial enlarged drawing in Fig. 3 A is the partial enlarged drawing in region shown in dotted line frame 4.
Utilize the definition of described mask plate one, adopt the chip region 2 of chemical wet etching technique on silicon chip 1 to form the deep trench 5 of deep trench product, the scribe line district on described silicon chip 1 forms and analyzes groove 3 simultaneously; Wherein said scribe line district is the perimeter that is positioned at described chip region 2.
Described analysis groove 3 is identical with the width of described deep trench 5; Overlook on face, described chip region 2 is rectangle or square, described analysis groove 3 is arranged on the side of one or more in the four edges of described chip region 2, and the length of described analysis groove 3 equals the length on limit of described chip region 2 of place side and parallel with this limit; As shown in Figure 4 A, on section, the top width of described analysis groove 3 is even, and the bottom of described analysis groove 3 is a radian and bottom width can be from the size reduction to 0 of top width.Because described analysis groove 3 is identical with the width of described deep trench 5, and be that etching forms simultaneously, therefore the degree of depth of described analysis groove 3 and described deep trench 5 is also identical.
Step 3, as shown in Figure 4 B, filled media layer in described analysis groove 3, fills described analysis groove 3 after described dielectric layer and is labeled as and analyzes groove 3a, in described deep trench 5, does not form described dielectric layer; The material requirements of described dielectric layer cannot form silicon epitaxy layer at its top, and the thickness requirement of described dielectric layer at least will fill up the bottom of described analysis groove 3 completely.
Be preferably, described dielectric layer fills up described analysis groove 3 completely; Thereby in described analysis groove 3, forming protective seams during filled media layer in described chip region 2 makes described deep trench 5 not form described dielectric layer.The material of described dielectric layer is monox or silicon nitride.
Step 4, as shown in Figure 4 C, adopts epitaxy technique to fill full silicon epitaxy layer in described deep trench 5, and the described deep trench 5 that is filled with described silicon epitaxy layer is labeled as deep trench 5a.Adopt afterwards the formation technique of described deep trench product to form described deep trench product.
Step 5, described deep trench product is analyzed, is comprised step by step:
Step 51, prepare analytic sample, by cutting into slices and form described analytic sample being formed with the silicon chip 1 of described deep trench product, this analytic sample comprises the described analysis groove 3 of a chip region 2 to be analyzed and the 2 weeks sides in this chip region, if cut into slices and obtain described analytic sample along the dotted line frame 4 in Fig. 3 A.
Step 52, described analytic sample is ground and is found the bottom of described deep trench 5a, as shown in Figure 5A, in the embodiment of the present invention, by first finding the bottom of described analysis groove 3a, by draw horizontal line from the bottom of described analysis groove 3a, be then the bottom that the method for dotted line BB ' is located described deep trench 5a; As shown in Figure 5 B, in region 7, be in fact to have the described deep trench 5a shown in Fig. 5 A, but because the silicon epitaxy layer in described deep trench 5a and described silicon chip 1 are all silicon materials, both visually cannot distinguish and come.
Utilize the described dielectric layer of filling in described analysis groove 3a to the degree of depth of described deep trench 5a, to position with the characteristic of silicon direct vision difference, when described analysis groove 3a arrives bottom, at the width of overlooking the described dielectric layer of the above analysis groove 3a of face, can dwindle, and described in during the closer to lowermost end, the reduced width of dielectric layer is more obvious, utilize the obvious characteristic of reduced width of described dielectric layer to judge that described analytic sample has been ground to the bottom of described analysis groove 3a, because the bottom degree of depth of described deep trench 5a is identical with the bottom degree of depth of described analysis groove 3a, by drawing horizontal line mode to position the bottom of described deep trench 5 from the bottom of described analysis groove 3a.As shown in Figure 5 C, in process of lapping, from the surface grinding of described analytic sample to CC ' line during the corresponding degree of depth of the surface of the corresponding degree of depth and DD ' line surperficial, observe overlooking on face, described analysis groove 3a width does not change substantially, when arriving the bottom of described analysis groove 3a, described analysis groove 3a width can obviously diminish, the feature that can obviously diminish by described analysis groove 3a width just can determine that grinding has reached the bottom of described analysis groove 3a, by drawing horizontal mode also just can determine the bottom of described deep trench 5a.Be preferably, in the embodiment of the present invention, by optical microscope or scanning electron microscope, observe the width of the described dielectric layer of described analysis groove 3a.
Step 53, physical analysis is carried out in the bottom of the described deep trench 5 of having good positioning, described physical analysis comprises tem analysis.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (5)
1. Physical Analysis Methods for location, the deep trench bottom of deep trench product, is characterized in that, comprise the steps:
Step 1, when layout design and mask plate are tailor-made, on the mask plate one of the deep trench figure of definition deep trench product, define analysis groove figure;
Step 2, utilize the definition of described mask plate one, adopt the chip region of chemical wet etching technique on silicon chip to form the deep trench of deep trench product, the scribe line district on described silicon chip forms and analyzes groove simultaneously; The width of described analysis groove and described deep trench is identical; Overlook on face, described chip region is rectangle or square, and described analysis groove is arranged on the side of one or more in the four edges of described chip region, and the length of described analysis groove equals the length on limit of described chip region of place side and parallel with this limit; On section, the top width of described analysis groove is even, and the bottom of described analysis groove is a radian and bottom width can be from the size reduction to 0 of top width;
Step 3, in described analysis groove filled media layer, in described deep trench, do not form described dielectric layer; The material requirements of described dielectric layer cannot form silicon epitaxy layer at its top, and the thickness requirement of described dielectric layer at least will fill up the bottom of described analysis groove completely;
Step 4, employing epitaxy technique are filled full silicon epitaxy layer in described deep trench, and are formed described deep trench product;
Step 5, described deep trench product is analyzed, is comprised step by step:
Step 51, prepare analytic sample, by cutting into slices and form described analytic sample being formed with the silicon chip of described deep trench product, this analytic sample comprises the described analysis groove of He Gai chip region, a chip region to be analyzed week side;
Step 52, described analytic sample is ground and is found the bottom of described deep trench, utilize the described dielectric layer of filling in described analysis groove to the degree of depth of described deep trench, to position with the characteristic of silicon direct vision difference, when described analysis groove arrives bottom, at the width of overlooking the described dielectric layer of the above analysis groove of face, can dwindle, and described in during the closer to lowermost end, the reduced width of dielectric layer is more obvious, utilize the obvious characteristic of reduced width of described dielectric layer to judge that described analytic sample has been ground to the bottom of described analysis groove, because the bottom degree of depth of described deep trench is identical with the bottom degree of depth of described analysis groove, by drawing horizontal line mode to position the bottom of described deep trench from the bottom of described analysis groove,
Step 53, physical analysis is carried out in the bottom of the described deep trench of having good positioning.
2. a method of claim 1, is characterized in that: dielectric layer described in step 3 fills up described analysis groove completely; Thereby in described analysis groove, forming protective seam during filled media layer in described chip region makes described deep trench not form described dielectric layer.
3. a method as claimed in claim 1 or 2, is characterized in that: the material of described dielectric layer is monox or silicon nitride.
4. a method of claim 1, is characterized in that: in step 52, by optical microscope or scanning electron microscope, come observation post to state the width of dielectric layer.
5. a method of claim 1, is characterized in that: in step 53, the physical analysis of the bottom of the described deep trench of having good positioning is comprised to tem analysis.
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| CN105699139A (en) * | 2016-01-20 | 2016-06-22 | 西安电子科技大学 | Preparation method of GaN thin film transmission electron microscope cross-section sample based on reactive ion etching |
| CN108375871A (en) * | 2018-02-06 | 2018-08-07 | 武汉新芯集成电路制造有限公司 | A kind of mask plate, production method and the method for alignment |
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| CN105699139A (en) * | 2016-01-20 | 2016-06-22 | 西安电子科技大学 | Preparation method of GaN thin film transmission electron microscope cross-section sample based on reactive ion etching |
| CN105699139B (en) * | 2016-01-20 | 2019-04-23 | 西安电子科技大学 | GaN film transmission electron microscope cross-sectional sample preparation method based on reactive ion etching |
| CN108375871A (en) * | 2018-02-06 | 2018-08-07 | 武汉新芯集成电路制造有限公司 | A kind of mask plate, production method and the method for alignment |
| CN108375871B (en) * | 2018-02-06 | 2021-08-24 | 武汉新芯集成电路制造有限公司 | Mask plate, manufacturing method and alignment method |
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