CN112185836B - Load effect monitoring method and layout - Google Patents
Load effect monitoring method and layout Download PDFInfo
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- CN112185836B CN112185836B CN202011021122.0A CN202011021122A CN112185836B CN 112185836 B CN112185836 B CN 112185836B CN 202011021122 A CN202011021122 A CN 202011021122A CN 112185836 B CN112185836 B CN 112185836B
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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Abstract
The application discloses a monitoring method and a layout of a load effect, wherein the method comprises the following steps: forming at least two types of device graphs and measuring graphs on a wafer through a photoetching process, wherein the characteristic sizes of the graphs of different types are different, and the characteristic size of the measuring graph is larger than that of the device graph; etching, etching the region of the wafer exposed by the device pattern to form a device groove, and etching the region of the wafer exposed by the measurement pattern to form a measurement groove; and measuring the depth of the measuring groove by using an atomic force microscope, and monitoring the load effect between different types of device grooves according to the depth of the measuring groove. This application obtains the degree of depth of measurationing the groove through atomic force microscope measurationing, and the depth through the measurationing groove of different grade type monitors the load effect between the device groove of different grade type, owing to need not carry out the section to the wafer, has solved among the correlation technique and has measurationed the time longer with the control load effect to the section sample through TEM, and the lower problem of monitoring efficiency.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method and a layout for monitoring a channel load effect of a semiconductor device.
Background
In an etching process of semiconductor manufacture, when a pattern to be etched is exposed to a reactive gas or a solution, a pattern with a larger Critical Dimension (CD) is etched at a lower rate than a pattern with a smaller critical dimension, because the pattern with the larger critical dimension is consumed to a greater extent than the pattern with the smaller critical dimension, resulting in a lower concentration of a reactant, and the etching rate is proportional to the concentration of the reactant, which is called a loading effect (loading effect)
On a wafer integrated with a semiconductor power device, trench structures (e.g., Deep Trench Isolation (DTI) structures) with different feature sizes are usually included, and due to a load effect, depths of the trench structures with different feature sizes are different, and when the depth difference of the trench structures with different feature sizes is too large due to a large influence of the load effect, a breakdown voltage of the device is low, and stability of the device is reduced.
In view of this, in the related art, the wafer is usually sliced to obtain sliced samples, and the sliced samples are measured by a Transmission Electron Microscope (TEM) to obtain depths of trench structures with different feature sizes, so as to monitor loading effects of the depths of the trenches with different feature sizes.
However, the time for measuring the slice sample by the TEM is long, and the monitoring efficiency is low; meanwhile, real-time monitoring of the load effect cannot be realized, and the monitoring timeliness is poor.
Disclosure of Invention
The application provides a load effect monitoring method and a layout, which can solve the problems of long time and low efficiency of monitoring the load effect through a TEM (transmission electron microscope) in the related technology.
In one aspect, an embodiment of the present application provides a method for monitoring a load effect, including:
forming a device graph and a measurement graph on a wafer through a photoetching process, wherein the device graph comprises at least two types of device graphs, the measurement graph comprises at least two types of measurement graphs, the feature sizes of the device graphs of different types are different, the feature sizes of the measurement graphs of different types are different, and the feature size of the measurement graph is larger than that of the device graph for any one of the device graphs and the measurement graphs;
etching is carried out, the region of the wafer exposed by the device pattern is etched to form a device groove, the device groove comprises at least two types of device grooves, the region of the wafer exposed by the measurement pattern is etched to form a measurement groove, the measurement groove comprises at least two types of measurement grooves, the characteristic sizes of the different types of device grooves are different, and the characteristic sizes of the different types of measurement grooves are different;
and measuring the depth of the measuring groove through an atomic force microscope, and monitoring the load effect among different types of device grooves according to the depth of the measuring groove.
Optionally, the monitoring the loading effect between the different types of device trenches according to the depth of the metrology trench includes:
and monitoring the load effect between the different types of device trenches according to the ratio of the depths of the different types of measurement trenches.
Optionally, the device patterns include a first type device pattern and a second type device pattern, and the metrology patterns include a first type metrology pattern and a second type metrology pattern;
the device grooves comprise a first type device groove and a second type device groove, the measuring grooves comprise a first type measuring groove and a second type measuring groove, the first type device groove is obtained by etching the first type device groove, and the second type device groove is obtained by etching the second type device groove;
monitoring loading effects between the different types of device trenches according to the ratio of the depths of the different types of metrology trenches includes:
calculating a ratio of depths of the first type of metrology trench and the second type of metrology trench;
determining that a loading effect between the first type of device trench and the second type of device trench does not meet a manufacturing standard when the ratio is greater than a ratio threshold.
Optionally, the monitoring the loading effect between the different types of device trenches according to the depth of the metrology trench includes:
and monitoring the load effect between different types of device trenches according to the difference of the depths of different types of measuring trenches.
Optionally, the device patterns include a first type device pattern and a second type device pattern, and the metrology patterns include a first type metrology pattern and a second type metrology pattern;
the device grooves comprise a first type device groove and a second type device groove, the measuring grooves comprise a first type measuring groove and a second type measuring groove, the first type device groove is obtained by etching the first type device groove, and the second type device groove is obtained by etching the second type device groove;
the monitoring of the loading effect between different types of device trenches according to the difference of the depths of the different types of measurement trenches includes:
calculating a difference in depth between the first type of metrology trench and the second type of metrology trench;
determining that a loading effect between the first type of device trench and the second type of device trench does not meet a manufacturing standard when the difference is greater than a difference threshold.
Optionally, the device pattern is formed in a first region of the wafer, the measurement pattern is formed in a second region of the wafer, and the first region and the second region do not overlap.
Optionally, the second region includes at least two sub-regions, the feature size of the measurement pattern formed in each sub-region is the same, and the feature size of the measurement pattern between different sub-regions is different.
Optionally, the metrology patterns include a first type of metrology pattern and a second type of metrology pattern, the first type of metrology pattern having a feature size of 13 micrometers (μm) to 20 μm.
Optionally, the feature size of the second type of measurement pattern is 4 to 12 microns.
In another aspect, an embodiment of the present application provides a layout of a semiconductor device, including:
the semiconductor device manufacturing method comprises the steps that device graphs comprise at least two types of device graphs, the feature sizes of the different types of device graphs are different, in the manufacturing process of the semiconductor device, the device graphs are transmitted to a wafer through a photoetching process, the region of the wafer exposed by the device graphs is etched to form a device groove, and the device groove comprises at least two types of device grooves;
measuring patterns, wherein the measuring patterns comprise at least two types of measuring patterns, the characteristic dimension of each type of measuring pattern is different, the measuring patterns are transferred onto the wafer through a photoetching process in the preparation process of the semiconductor device, the region of the wafer exposed by the measuring patterns is etched to form measuring grooves, the measuring grooves comprise at least two types of measuring grooves, the depth of the measuring grooves is measured through an atomic force microscope, and the load effect between the device grooves of different types is monitored according to the depth of the measuring grooves;
wherein, for any of the device patterns and the metrology patterns, the feature size of the metrology pattern is larger than the device pattern.
Optionally, the measurement pattern is rectangular.
Optionally, the device pattern is disposed in a first region of the layout, the measurement pattern is disposed in a second region of the layout, and the first region and the second region are not overlapped.
Optionally, the second region includes at least two sub-regions, the feature size of the measurement pattern formed in each sub-region is the same, and the feature size of the measurement pattern between different sub-regions is different.
Optionally, the measurement patterns include a first type of measurement pattern and a second type of measurement pattern, and a feature size of the first type of measurement pattern is 13 micrometers to 20 micrometers.
Optionally, the feature size of the second type of measurement pattern is 4 to 12 microns.
The technical scheme at least comprises the following advantages:
the method comprises the steps of forming a measuring graph with the characteristic dimension larger than that of a device graph when the device graph is formed on a wafer through a photoetching process, forming different types of device grooves and different types of measuring grooves after etching, measuring the depth of the measuring groove through an atomic force microscope, and monitoring the load effect among the different types of device grooves through the depth of the measuring groove; meanwhile, the load effect between the device grooves of different types is monitored through the measuring grooves on the same wafer, so that the real-time monitoring of the load effect is realized.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method for monitoring the effect of a load provided by an exemplary embodiment of the present application;
FIG. 2 is a cross-sectional view of a device pattern and metrology pattern formed on a wafer as provided by an exemplary embodiment of the present application;
FIG. 3 is a schematic top view of a device pattern and metrology pattern formed on a wafer as provided by an exemplary embodiment of the present application;
FIG. 4 is a schematic top view of a device pattern and metrology pattern formed on a wafer as provided by another exemplary embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a device trench and a metrology trench formed after an etch is performed as provided by an exemplary embodiment of the present application;
FIG. 6 is a schematic diagram of a layout of a semiconductor device provided in an exemplary embodiment of the present application;
fig. 7 is a schematic diagram of a layout of a semiconductor device provided in another exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for monitoring a load effect provided by an exemplary embodiment of the present application is shown. The method can be applied to monitoring the load effect of the depth of the groove formed by etching in the preparation process of the semiconductor device, and comprises the following steps:
Referring to fig. 2, a cross-sectional view of a device pattern and metrology pattern formed on a wafer is shown, according to an exemplary embodiment of the present application. It should be noted that fig. 2 illustrates the formation of a device pattern and a metrology pattern on the substrate 210, and the device pattern and the metrology pattern may also be formed on a dielectric layer, a metal layer, or other thin film layer.
As shown in fig. 2, a device pattern and a metrology pattern are formed on the substrate 210 by a photolithography process, wherein the device pattern includes at least two types of device patterns (illustrated in fig. 2 by a first type of device pattern 221 and a second type of device pattern 222, the feature size of the first type of device pattern 221 is different from the feature size of the second type of device pattern 222), and the metrology pattern includes at least two types of metrology patterns (illustrated in fig. 2 by a first type of metrology pattern 231 and a second type of metrology pattern 232, the feature size of the first type of metrology pattern 231 is different from the feature size of the second type of metrology pattern 232).
In the embodiment of the application, the type of the graph takes the characteristic size as a classification standard, the characteristic sizes of the graphs of different types are different, and the characteristic sizes of the graphs of the same type are the same. For any device pattern and metrology pattern, the feature size of the metrology pattern is larger than the device pattern, e.g., in fig. 2, the feature size of the first type of metrology pattern 231 is larger than the feature size of the second type of device pattern 222, the feature size of the first type of metrology pattern 231 is larger than the feature size of the first type of device pattern 221, the feature size of the second type of metrology pattern 232 is larger than the feature size of the second type of device pattern 222, and the feature size of the second type of metrology pattern 232 is larger than the feature size of the first type of device pattern 221.
Referring to fig. 3, a schematic top view of a device pattern and metrology pattern formed on a wafer is shown provided by an exemplary embodiment of the present application; referring to fig. 4, a schematic top view of a device pattern and metrology pattern formed on a wafer is shown, provided by another exemplary embodiment of the present application. As shown in fig. 3 and 4, the device pattern is formed in a first region 201 of the wafer 100, and the metrology pattern is formed in a second region 202 of the wafer 100, where the first region 201 and the second region 202 do not overlap.
As shown in fig. 3, a distribution diagram of a metrology pattern is shown, in which the second region 202 comprises at least two sub-regions (exemplarily illustrated by two sub-regions 2021 and 2022 in fig. 3), the feature size of the metrology pattern formed in each sub-region is the same, and the feature size of the metrology pattern between each sub-region is different. For example, in fig. 3, the first type measurement pattern 231 is formed in the sub-region 2021, the second type measurement pattern 232 is formed in the sub-region 2022, the feature sizes of the first type measurement pattern 231 in the sub-region 2021 are the same, the feature sizes of the second type measurement pattern 232 in the sub-region 2022 are the same, and the feature sizes of the first type measurement pattern 231 in the sub-region 2021 and the second type measurement pattern 232 in the sub-region 2022 are different.
As shown in fig. 4, a distribution diagram of another metrology pattern is shown, in which metrology patterns of different feature sizes (illustrated in fig. 4 as a first type of metrology pattern 231 and a second type of metrology pattern 232) are distributed in the second region 202.
Optionally, in the embodiment of the present application, the feature size of the first type of measurement pattern 231 is 4 microns to 12 microns (for example, may be 8 microns); optionally, the feature size of the second type of metrology pattern 232 is 13 microns to 20 microns (e.g., may be 16 microns).
Optionally, in this embodiment, the feature size of the measurement pattern may be a width of the measurement pattern.
And 102, etching is carried out, the region of the wafer exposed by the device graph is etched to form a device groove, the device groove comprises at least two types of device grooves, the region of the wafer exposed by the measurement graph is etched to form a measurement groove, the measurement groove comprises at least two types of measurement grooves, the characteristic sizes of the different types of device grooves are different, and the characteristic sizes of the different types of measurement grooves are different.
Referring to fig. 5, a schematic cross-sectional view of a device trench and a metrology trench formed after etching is shown. As shown in fig. 5, a first device trench 241 is formed under the first-type device pattern 221, a second device trench 242 is formed under the second-type device pattern 222, a first metrology trench 251 is formed under the first-type metrology pattern 231, and a second metrology trench 252 is formed under the second-type metrology pattern 232. Due to the loading effect, the depth h1 of the first device trench 241, the depth h2 of the second device trench 242, the depth h3 of the first measurement trench 251, and the depth h4 of the second measurement trench 252 are different.
And 103, measuring the depth of the measuring groove through an atomic force microscope, and monitoring the load effect among different types of device grooves according to the depth of the measuring groove.
Since it is difficult for the afm to measure the trench having a small width, it is difficult to directly measure the device trenches (e.g., the first device trench 241 and the second device trench 242), so that the loading effect between different types of device trenches can be monitored by an indirect measurement method of measuring the measurement trenches (e.g., the first measurement trench 251 and the second measurement trench 252).
Optionally, in step 103, "monitoring the loading effect between different types of device trenches according to the depth of the measurement trench" includes but is not limited to: and monitoring the load effect between different types of device trenches according to the ratio of the depths of the different types of measurement trenches.
For example, monitoring may be by: calculating a ratio (h3/h4) of depths of the first type of metrology trench 251 and the second type of metrology trench 252; when the ratio is greater than the ratio threshold, it is determined that the loading effect between the first-type device trenches 241 and the second-type device trenches 242 does not meet the manufacturing standard.
Optionally, in step 103, "monitoring the loading effect between different types of device trenches according to the depth of the measurement trench" includes but is not limited to: and monitoring the load effect between different types of device trenches according to the difference of the depths of different types of measuring trenches.
For example, monitoring may be by: calculating the difference in depth of the first type of metrology trench 251 and the second type of metrology trench 252 (h3-h 4); when the difference is greater than the difference threshold, it is determined that the loading effect between the first-type device trenches 241 and the second-type device trenches 242 does not meet the manufacturing standard.
Optionally, the semiconductor device in this embodiment of the present application is a metal-oxide-semiconductor (MOS) device.
In summary, in the embodiment of the present application, a measurement pattern with a characteristic dimension larger than that of a device pattern is formed when the device pattern is formed on a wafer through a photolithography process, different types of device trenches and different types of measurement trenches are formed after etching, the depth of the measurement trench is obtained through measurement by an atomic force microscope, and the load effect between the different types of device trenches is monitored through the depth of the measurement trench, so that the wafer does not need to be sliced through the measurement trench by the atomic force microscope, and the problems of long measurement time and low monitoring efficiency of a slice sample through TEM in the related art are solved; meanwhile, the load effect between the device grooves of different types is monitored through the measuring grooves on the same wafer, so that the real-time monitoring of the load effect is realized.
Referring to fig. 6, a schematic diagram of a layout of a semiconductor device provided by an exemplary embodiment of the present application is shown. The layout of the semiconductor device can be applied to the preparation process in any of the above embodiments, which includes:
at least two types of device patterns (a first type of device pattern 621 and a second type of device pattern 622 are exemplarily illustrated in fig. 6), feature sizes of each type of device pattern are different, in a manufacturing process of a semiconductor device corresponding to the layout, the device patterns are transferred onto a wafer through a photolithography process, regions of the wafer exposed by the device patterns are etched to form device trenches, and the formed device trenches include at least two types of trenches.
At least two types of measurement patterns (the first type of measurement pattern 631 and the second type of measurement pattern 632 are exemplarily illustrated in fig. 6), each type of measurement pattern having a different feature size, wherein during the fabrication of the semiconductor device corresponding to the layout, the measurement patterns are transferred onto a wafer through a photolithography process, an area of the wafer exposed by the measurement patterns is etched to form measurement trenches, the formed measurement trenches include at least two types of measurement trenches, the depth of the measurement trenches is measured through an atomic force microscope, and a loading effect between the different types of device trenches is monitored according to the depth of the measurement trenches.
In the embodiment of the application, the type of the graph takes the characteristic size as a classification standard, the characteristic sizes of the graphs of different types are different, and the characteristic sizes of the graphs of the same type are the same. Wherein, for any device pattern and the measurement pattern, the feature size of the measurement pattern is larger than that of the device pattern. For example, in FIG. 6, the feature size of the first type of metrology pattern 631 is larger than the feature size of the second type of device pattern 622, the feature size of the first type of metrology pattern 631 is larger than the feature size of the first type of device pattern 621, the feature size of the second type of metrology pattern 632 is larger than the feature size of the second type of device pattern 622, and the feature size of the second type of metrology pattern 632 is larger than the feature size of the first type of device pattern 621.
Alternatively, referring to fig. 6, the device pattern is disposed in a first region 601 of the layout, and the measurement pattern is disposed in a second region 602 of the layout, where the first region 601 and the second region 602 do not overlap.
Referring to fig. 7, a schematic diagram of a layout of a semiconductor device provided in another embodiment of the present application is shown. The difference between the embodiment of fig. 7 and the embodiment of fig. 6 is that: the second region 602 includes at least two sub-regions (a first sub-region 6021 and a second sub-region 6022 are illustrated in fig. 7), and the feature size of the metrology pattern formed in each sub-region is the same, and the feature size of the metrology pattern differs between different sub-regions. For example, in fig. 7, the first type of measurement pattern 631 is formed in the sub-region 6021, the second type of measurement pattern 632 is formed in the sub-region 6022, the feature sizes of the first type of measurement pattern 631 in the sub-region 6021 are the same, the feature sizes of the second type of measurement pattern 632 in the sub-region 6022 are the same, and the feature sizes of the first type of measurement pattern 631 in the sub-region 6021 and the second type of measurement pattern 632 in the sub-region 6022 are different.
Optionally, in the embodiment of the present application, the feature size of the first type of measurement pattern 631 is 13 microns to 20 microns; optionally, the feature size of the second type of metrology pattern 632 is 4 microns to 12 microns.
Optionally, in the embodiment of the present application, the measurement pattern is a rectangle; optionally, the wide range of the measurement pattern is 40 to 60 micrometers (for example, 50 micrometers); optionally, the length of the measurement pattern ranges from 70 micrometers to 100 micrometers (for example, may be 80 micrometers).
Optionally, in this embodiment, the feature size of the measurement pattern may be a width of the measurement pattern.
Optionally, in this embodiment of the present application, the semiconductor device applied to the semiconductor device layout is a power MOS device.
In summary, in the embodiment of the present application, a layout including a device pattern and a measurement pattern is used for photolithography, the measurement pattern with a characteristic dimension larger than that of the device pattern is formed when the device pattern is formed on a wafer, a device trench and a measurement trench are formed after etching, the depth of the measurement trench is obtained through measurement by an atomic force microscope, and the depth of the device trench is monitored through the depth of the measurement trench, so that the wafer does not need to be sliced through the measurement trench by the atomic force microscope, and the problems of long time for measuring a slice sample through a TEM and low monitoring efficiency in the related art are solved; meanwhile, the device groove is monitored through the measuring groove on the same wafer, so that the device groove is monitored in real time.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (15)
1. A method for monitoring a loading effect, comprising:
forming a device graph and a measurement graph on a wafer through a photoetching process, wherein the device graph comprises at least two types of device graphs, the measurement graph comprises at least two types of measurement graphs, the feature sizes of the device graphs of different types are different, the feature sizes of the measurement graphs of different types are different, and the feature size of the measurement graph is larger than that of the device graph for any one of the device graphs and the measurement graphs;
etching is carried out, the region of the wafer exposed by the device pattern is etched to form a device groove, the device groove comprises at least two types of device grooves, the region of the wafer exposed by the measurement pattern is etched to form a measurement groove, the measurement groove comprises at least two types of measurement grooves, the characteristic sizes of the different types of device grooves are different, and the characteristic sizes of the different types of measurement grooves are different;
and measuring the depth of the measuring groove through an atomic force microscope, and monitoring the load effect among different types of device grooves according to the depth of the measuring groove.
2. The method of claim 1 wherein said monitoring loading effects between different types of said device trenches based on a depth of said metrology trench comprises:
and monitoring the load effect between the different types of device trenches according to the ratio of the depths of the different types of measurement trenches.
3. The method of claim 2, wherein the device patterns comprise a first type of device pattern and a second type of device pattern, and the metrology patterns comprise a first type of metrology pattern and a second type of metrology pattern;
the device grooves comprise a first type device groove and a second type device groove, the measuring grooves comprise a first type measuring groove and a second type measuring groove, the first type device groove is obtained by etching the first type device groove, and the second type device groove is obtained by etching the second type device groove;
monitoring loading effects between the different types of device trenches according to the ratio of the depths of the different types of metrology trenches includes:
calculating a ratio of depths of the first type of metrology trench and the second type of metrology trench;
determining that a loading effect between the first type of device trench and the second type of device trench does not meet a manufacturing standard when the ratio is greater than a ratio threshold.
4. The method of claim 1 wherein said monitoring loading effects between different types of said device trenches based on a depth of said metrology trench comprises:
and monitoring the load effect between different types of device trenches according to the difference of the depths of different types of measuring trenches.
5. The method of claim 2, wherein the device patterns comprise a first type of device pattern and a second type of device pattern, and the metrology patterns comprise a first type of metrology pattern and a second type of metrology pattern;
the device grooves comprise a first type device groove and a second type device groove, the measuring grooves comprise a first type measuring groove and a second type measuring groove, the first type device groove is obtained by etching the first type device groove, and the second type device groove is obtained by etching the second type device groove;
the monitoring of the loading effect between different types of device trenches according to the difference of the depths of the different types of measurement trenches includes:
calculating a difference in depth of the first type of metrology trench and the second type of metrology trench;
determining that a loading effect between the first type of device trench and the second type of device trench does not meet a manufacturing standard when the difference is greater than a difference threshold.
6. The method of any of claims 1 to 5, wherein the device pattern is formed in a first area of the wafer and the metrology pattern is formed in a second area of the wafer, the first area and the second area not overlapping.
7. The method of claim 6, wherein the second region comprises at least two sub-regions, wherein the feature size of the metrology pattern formed in each sub-region is the same, and wherein the feature size of the metrology pattern differs between different sub-regions.
8. The method of claim 7, wherein the metrology pattern comprises a first type of metrology pattern and a second type of metrology pattern, the first type of metrology pattern having a feature size of 13-20 microns.
9. The method of claim 8, wherein the feature size of the second type of metrology feature is from 4 microns to 12 microns.
10. A layout of a semiconductor device, comprising:
the device comprises a semiconductor device, a device graph and a control circuit, wherein the device graph comprises at least two types of device graphs, the characteristic size of each type of device graph is different, in the preparation process of the semiconductor device, the device graph is transferred to a wafer through a photoetching process, the region of the wafer exposed by the device graph is etched to form a device groove, and the device groove comprises at least two types of device grooves;
measuring patterns, wherein the measuring patterns comprise at least two types of measuring patterns, the characteristic dimension of each type of measuring pattern is different, the measuring patterns are transferred onto the wafer through a photoetching process in the preparation process of the semiconductor device, the region of the wafer exposed by the measuring patterns is etched to form measuring grooves, the measuring grooves comprise at least two types of measuring grooves, the depth of the measuring grooves is measured through an atomic force microscope, and the load effect between the device grooves of different types is monitored according to the depth of the measuring grooves;
wherein, for any of the device patterns and the metrology patterns, the feature size of the metrology pattern is larger than the device pattern.
11. The layout of claim 10, wherein the metrology pattern is rectangular.
12. The layout according to claim 11, wherein the device pattern is disposed in a first region of the layout, and the measurement pattern is disposed in a second region of the layout, the first region and the second region not overlapping.
13. The layout according to claim 12, wherein the second region includes at least two sub-regions, the feature size of the measurement pattern formed in each sub-region is the same, and the feature size of the measurement pattern differs between different sub-regions.
14. The layout according to claim 13, wherein the measurement patterns comprise a first type of measurement pattern and a second type of measurement pattern, and the feature size of the first type of measurement pattern is 13 to 20 μm.
15. The layout according to claim 14, wherein the feature size of the second type of metrology feature is from 4 microns to 12 microns.
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| CN102097287A (en) * | 2009-12-15 | 2011-06-15 | 北大方正集团有限公司 | Method for monitoring chip groove depth and wafer |
| CN104701212A (en) * | 2015-03-30 | 2015-06-10 | 上海华力微电子有限公司 | Method for detecting etching load effects |
| CN111029271A (en) * | 2019-12-26 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Method for monitoring depth of groove |
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| JP2005191331A (en) * | 2003-12-26 | 2005-07-14 | Nec Electronics Corp | Method for manufacturing semiconductor device |
| KR100706811B1 (en) * | 2006-02-08 | 2007-04-12 | 삼성전자주식회사 | Test pattern and method for measuring silicon etching depth |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102097287A (en) * | 2009-12-15 | 2011-06-15 | 北大方正集团有限公司 | Method for monitoring chip groove depth and wafer |
| CN104701212A (en) * | 2015-03-30 | 2015-06-10 | 上海华力微电子有限公司 | Method for detecting etching load effects |
| CN111029271A (en) * | 2019-12-26 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Method for monitoring depth of groove |
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