CN105245091B - A power converter gate drive circuit power mos tube - Google Patents

A power converter gate drive circuit power mos tube Download PDF

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Publication number
CN105245091B
CN105245091B CN201510703629.7A CN201510703629A CN105245091B CN 105245091 B CN105245091 B CN 105245091B CN 201510703629 A CN201510703629 A CN 201510703629A CN 105245091 B CN105245091 B CN 105245091B
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m0s
power
gate
connected
tube
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CN105245091A (en
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钱钦松
刘鹏
俞居正
刘斯扬
孙伟锋
陆生礼
时龙兴
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东南大学
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Abstract

一种功率变换器中功率MOS管的栅极驱动电路,包括直流电压源V、MOS管Q1、储能电容C、储能电感L、MOS管Q2和MOS管Q3,直流电压源V的正极连接MOS管Q1的漏极,MOS管Q1的栅极连接外接控制信号I,MOS管Q1的源极连接储能电容C的一端和储能电感L的一端,储能电容C的另一端接地,储能电感L的另一端连接MOS管Q2的漏极和MOS管Q3的源极,MOS管Q2的栅极连接外接控制信号II,MOS管Q2的源极连接直流电压源V的负极并接地,MOS管Q3的栅极连接外接控制信号III,MOS管Q3的漏极连接功率变换器中功率MOS管Q4的栅极;外接控制信号I、外接控制信号II和外接控制信号III都是由占空比可调的波形发生器所提供。 The gate drive circuit for a power converter with power MOS transistors, comprising a DC voltage source V, the MOS transistor Q1, the storage capacitor C, inductor L, the MOS transistor Q2 and MOS transistor Q3, the positive electrode is connected to a DC voltage source V drain of the MOS transistor Q1, the gate of the MOS transistor Q1 is connected to an external control signal I, source of MOS transistor Q1 is connected to other end of the storage capacitor C one end of the inductor L and one end of the storage capacitor C, a reservoir MOS transistor Q3 and a drain of the inductor L can be connected to the other end of MOS transistor Q2, a gate MOS transistor Q2 is connected to an external control signal II, source of the MOS transistor Q2 is connected to the negative pole of the direct voltage source V and to ground, MOS the gate of transistor Q3 is connected to an external control signal III, the gate of the power MOS transistor Q4 is connected to the drain of the power MOS transistor Q3 converter; external control signals I, II, and an external control signal is an external control signal by the duty cycle III an adjustable waveform generator is provided.

Description

一种功率变换器中功率MOS管的栅极驱动电路 A power converter gate drive circuit of the power MOS

技术领域 FIELD

[0001] 本发明涉及开关变换器,尤其涉及一种功率变换器中功率M0S管的栅极驱动电路。 [0001] The present invention relates to a switching converter, in particular, it relates to a gate driving circuit for a power converter power M0S tube.

背景技术 Background technique

[0002] 近年来,在功率变换器中为了进一步减小无源器件的体积,提高功率变换器的功率密度,人们设计的变换器开关频率越来越高。 [0002] In recent years, in the power converter in order to further reduce the volume of passive components and increases the power density of a power converter, the converter switching frequency have been designed more and more. 一般情况下,随着开关频率的增加,变换器中的功率M0S管的开关损耗以及栅极驱动电路的损耗都会随之增加,导致整个系统的效率降低。 In general, as the switching frequency increases, the switching loss in the inverter power loss will M0S tube and the gate drive circuit increases, resulting in reduced efficiency of the entire system. 这样,在高频应用场合中,即使在轻载情况下,由于开关损耗以及栅极驱动电路损耗的增加,系统的可靠性也不能够保证。 Thus, high frequency applications, even at light load conditions, due to increased switching losses and gate drive circuit loss, the system reliability is not guaranteed. 如果不能有效减小这些损耗,就有可能导致相关器件失效、系统的可靠性降低,甚至会导致整个系统不能正常工作。 If not effectively reduce these losses, it is possible to cause the associated device failure, reducing the reliability of the system, and even cause the entire system does not work.

[0003] 尤其是变换器中的功率M0S管,要保证电路中有能量从输入端传递到输出端,功率M0S管的可靠性必须得到保证。 [0003] In particular, the power converter is M0S tube, to ensure that the energy transfer circuit from the input terminal to the output terminal, reliability of the power M0S tube must be guaranteed. 而对于M0S管的损耗主要来源包括两个:开关损耗和导通损耗。 As for the loss of the main tube comprises two sources M0S: conduction losses and switching losses. M0S管的导通损耗由M0S管自身的导通电阻以及流过的电流决定的,由于M0S管的导通电阻是由M0S管自身的性能决定的,而且基本上是处于零点几欧姆级别左右。 M0S tube M0S conduction losses by the tube itself and the on-resistance of the current flowing through the decision, since the on-resistance of the tube is made M0S M0S tube itself determines the performance of, and essentially at the level of about a few tenths of ohms. 因此正常情况下,M0S管的导通损耗是可以接受的。 Thus under normal circumstances, M0S tube conduction loss is acceptable. 但是,M0S管的开关损耗在很大程度上取决于M0S管的栅极驱动电路。 However, switching losses M0S tube depends largely on the gate drive circuit M0S tube. 如果M0S管的栅极驱动电路设计的不合理,那么由此造成的M0S管的开关损耗非常有可能导致M0S管的失效。 If the gate driving circuit M0S tube improper design, then the resulting pipe is very M0S switching losses may cause failure M0S tube.

[0004] 目前,对于传统的功率M0S管栅极驱动电路的设计方案,大多数采用电压源通过串接一个栅极驱动电阻,然后对功率M0S管的栅极进行充放电。 [0004] Currently, the traditional design for tube M0S power gate drive circuit, a voltage source in most cases by a gate resistor connected in series, and the gate of the power tube M0S charging and discharging. 这种驱动电路的设计方案虽然简单且容易实现,但是驱动电流在对M0S管的栅极进行充放电的同时,也流经了栅极驱动电阻,这样就会不可避免的增加栅极驱动电路的损耗。 This design of the driving circuit is simple and easy to implement, but at the same time the gate driving current M0S charge and discharge tubes, also flows through the gate resistor, this will inevitably increase the gate driving circuit loss. 而且,传统M0S管栅极驱动电路的设计, 在M0S管需要关断时,驱动电路是将M0S管栅极上面的电荷经过地线泄放掉,明显增加了栅极驱动电路的损耗,不利于功率变换器整体效率的提高。 Furthermore, the conventional gate driving circuit M0S tube design, the tube when required M0S off, the gate driving circuit is charged through the tube above the ground M0S vent let go, significantly increasing the loss of the gate driving circuit, is not conducive to improve the overall efficiency of the power converter.

[0005]除此之外,有人针对降低栅极驱动电路的损耗还提出根据负载输出情况的不同而调节功率M0S管的开关频率,这样虽然从一个周期整体来看,有助于降低驱动电路的损耗, 但是这种方案不仅电路实现较为复杂,而且还会导致输出电压有较大的纹波和较为严重的EMI。 [0005] In addition, it was directed to reducing further loss of the gate driving circuit made according to different load conditions the output of the switching frequency of the power adjusting M0S tube, so that although the overall cycle point of view, helps to reduce the driving circuit loss, but this solution is not only more complex circuit implementation, but also lead to a larger output voltage ripple and more serious EMI. 因此,设计一种结构简单,又具有高效率的M0S管栅极驱动电路,是要解决的一大问题。 Thus, to design a simple structure, and a high efficiency of the tube M0S gate driving circuit, is a big problem to be solved.

发明内容 SUMMARY

[0006]本发明目的在于提供一种功率变换器中功率M0S管的栅极驱动电路,以降低M0S管的损耗,尤其是降低M0S管的开关损耗,进一步提高变换器的效率,增加系统的可靠性。 [0006] The object of the present invention is to provide a gate drive circuit for a power converter M0S power tube to reduce the loss M0S tube, in particular to reduce the switching loss M0S tube, to further improve the efficiency of the converter, to increase the system reliability sex.

[0007] 本发明为实现上述目的,采用如下技术方案:一种功率变换器中功率M0S管的栅极驱动电路,其特征在于:包括直流电压源¥、1;108管&、储能电容C、储能电感L、M0S管Q2和M0S管Q3,直流电压源V的正极连接M0S管&的漏极,1;105管&的栅极连接外接控制信号I,M0S管&的源极连接储能电容C的一端和储能电感L的一端,储能电容C的另一端接地,储能电感L的另一端连接M0S管Q2的漏极和M0S管Q3的源极,M0S管Q2的栅极连接外接控制信号II,M0S管Q2的源极连接直流电压源V的负极并接地,MOS管Q3的栅极连接外接控制信号III,MOS管Q3的漏极作为驱动电路的输出,连接功率变换器中功率M0S管Q4的栅极;外接控制信号I、外接控制信号II和外接控制信号III都是由占空比可调的波形发生器所提供; [0007] To achieve the above object of the present invention, the following technical solution: a gate driving circuit for a power converter power M0S tube, characterized by: a DC voltage source ¥, 1; 108 Tube & amp ;, the storage capacitor drain, 1;; C, inductor L, M0S transistor Q2 and M0S tube Q3, the positive electrode connecting M0S DC voltage source V tube & amp 105 tube & amp; gate connected to an external control signal I, M0S tube & amp; the M0S drain of transistor Q3 and one end of the L, the other end of the storage capacitor C, inductor L and the other end connected to the source end of the storage capacitor C and the inductor electrode connected to the transistor Q2 M0S, tube M0S the gate of Q2 is connected to an external control signal II, M0S source connected to the negative electrode of transistor Q2 is a DC voltage source V and to ground, gate of the MOS transistor Q3 is connected to an external control signal III, the drain of the MOS transistor Q3 as a drive circuit output, a power converter connected to the power gate of Q4 is M0S; external control signals I, II external control signal and an external control signal III are provided by a variable duty cycle waveform generator;

[0008] 上述驱动电路在开关电源中功率M0S管Q4的一个开关周期内,]«03管&只开关一次, 在功率M0S管Q4开通过程中,储能电容C中的能量通过由储能电容C、储能电感L、M0S管Q2和M0S管Q3组成的等效Boost电路传递到功率M0S管Q4的栅极,在功率M0S管Q4关断过程中,功率M0S管Q4栅极上的能量通过由M0S管Q3、M0S管Q2、储能电感L和储能电容C组成的等效Buck电路返回到储能电容C中。 [0008] In the driving circuit within one switching cycle of the switching power supply of the power transistor Q4 M0S,] «03 & amp; only one switch, a power transistor Q4 M0S opening process, in the energy storage capacitor C from the storage by capacitor C, inductor L, equivalent Boost circuit M0S M0S transistor Q2 and transistor Q3, which is passed to the gate of the power M0S transistor Q4, transistor Q4 M0S power during shutdown, the energy of the power transistor Q4 gate M0S return to the storage capacitor C by an equivalent circuit composed M0S Buck tube Q3, M0S tube Q2, the energy storage inductor L and the capacitance C thereof.

[0009] 所述直流电压源V是一个输出0.7V的恒压源,其作用相当于一个电荷泵。 [0009] The DC voltage source outputting a constant voltage source V is 0.7V, which acts as a charge pump.

[0010] 所述M0S管QhMOS管Q2和M0S管Q3均为N沟道型M0SFET,型号采用IRF120,MOS管Q4为N沟道型M0SFET,型号采用SPW20N60S5,储能电容C为10yF,储能电感L为1此。 [0010] The transistor Q2 and M0S tube QhMOS M0S transistor Q3 are N-channel type M0SFET, models use IRF120, MOS transistor Q4 are N-channel type M0SFET, models use SPW20N60S5, the storage capacitor C is 10yF, inductor L 1 thereto.

[0011] 本发明具有如下优点: [0011] The present invention has the following advantages:

[0012] 1、在驱动电路使功率M0S管Q4关断时,传统驱动方案往往将M0S管Q4栅极电荷通过大地完全泄放掉,或者由栅源泄放电阻和M0S管Q4的栅源寄生电阻消耗掉,这样不仅增加了驱动电路的损耗,而且也降低了功率M0S管Q4的可靠性。 [0012] 1, the driving circuit of the power transistor Q4 is turned off when M0S, the conventional drive scheme M0S transistor Q4 tend to gate charge exhausting completely through the earth, or by a bleeder resistor and the gate-source gate-source parasitic M0S tube and Q4 resistance consumed, not only increase the loss of the drive circuit, but also reduces the reliability of the power transistor Q4 M0S. 本发明所采用的驱动方案,是将功率M0S管Q4栅极上面的电荷在M0S管Q4关断时,又回馈到驱动电路的储能电容中。 Drive scheme used in the present invention, the power is above the gate charge at the transistor Q4 M0S M0S transistor Q4 is turned off, the storage capacitor and back to the drive circuit. 用于驱动M0S管Q4下一周期的开通,大大降低了驱动电路的损耗。 M0S transistor Q4 for driving the opening of the next cycle, greatly reduce the loss of the drive circuit.

[0013] 2、在驱动电路使功率M0S管Q4开通时,与传统的驱动方案相比,本发明由于省去了栅极驱动电阻,这样就不存在栅极驱动电阻上面的损耗,降低了驱动电路的损耗,提高了系统的效率。 [0013] 2, the driving circuit of the power transistor Q4 M0S opening when compared with the conventional drive scheme, because the present invention eliminates the gate resistor, so there is no loss of the above gate driving resistance, the drive is reduced loss of the circuit, improving the efficiency of the system.

[0014] 3、本发明提出的驱动方案,当驱动电流流经电感需要续流时,采用同步整流的方法代替了传统意义的“续流二极管”,进一步降低驱动电路的损耗。 [0014] 3, the drive scheme proposed by the present invention, when the driving current flowing through the inductor needs wheeling synchronous rectification method instead of the traditional meaning of "freewheeling diode", to further reduce the loss of the drive circuit.

[0015] 4、本发明提出的驱动方案,是由基本的Buck、Boost电路拓扑变形而来,仅增加了两个起储能作用的无源器件储能电感L和储能电容C,结构及控制方法简单,容易实现。 [0015] 4. The proposed driving scheme of the present invention, is a basic Buck, Boost circuit topology from modification, an increase of only two passive components from the inductor L and store energy storage capacitor C, and Structure control method is simple and easy to implement.

附图说明 BRIEF DESCRIPTION

[0016]图1是本发明电路原理图; [0016] FIG. 1 is a circuit schematic diagram of the present invention;

[0017]图2是图1中关键节点示意图; [0017] FIG. 2 is a schematic diagram of key nodes in Figure 1;

[0018]图3是图1实施例原理图; _9]图4是图2中相关控制信号以及关键节点的波形图; [0018] FIG. 3 is a schematic diagram of the embodiment of FIG. 1; [9] FIG. 4 is a waveform diagram in FIG. 2 and the associated key control signal node;

[0020]图5是本发明与传统串接栅极驱动电阻方案在不同开关频率下的效率对比图; [0020] FIG. 5 is a series of the present invention and the conventional gate drive resistor program effectiveness comparison chart at different switching frequencies;

具体实施方式 Detailed ways

[0021]下面结合附图对发明的技术进行详细说明。 Technical drawings of the invention will be described in detail [0021] below in conjunction.

[0022] 如图1,是本发明提出的具体原理图。 [0022] FIG. 1 is a detailed schematic diagram of the present invention is presented. 直流电压源V是一个能够输出0.7V大小的恒压源,其作用相当于一个电荷泵。 V is a DC voltage source capable of outputting 0.7V constant voltage source size, which acts as a charge pump.

[0023] M0S管Qi为N沟道型M0SFET,栅极外接控制信号I,控制麗)8管&在合适的时刻开通和关断。 [0023] M0S tube Qi N-channel type M0SFET, external gate control signal I, the control Korea) 8 & amp; at the appropriate time on and off. 控制信号I由一个占空比可调的波形发生器所提供。 Control signal I is provided by a variable duty cycle waveform generator.

[0024]储能电容C在被驱动的M0S管Q4开通之前,存储来自直流电压源V中的能量。 [0024] The storage capacitor C before being driven M0S Q4 is opened, the stored energy from the DC voltage source V in.

[0025]储能电感L在被驱动的MOS管Q4开通之前储存来自储能电容C中的能量,为Boost升压电路的开启做准备。 [0025] The inductor L stores energy from the storage capacitor C before being driven MOS transistor Q4 opened, in preparation for the opening of Boost circuit.

[0026] M0S管Q2为N沟道型M0SFET,栅极外接控制信号II,控制.3管&在合适的时刻开通和关断。 [0026] M0S N-channel type transistor Q2 M0SFET, external gate control signal II, the control tube .3 & amp; at the appropriate time on and off. 控制信号II的来源和控制信号I类似,也是由一个占空比可调的波形发生器所提供。 The control signal source and control signal II I Similarly, a duty cycle is provided by the adjustable waveform generator. 在功率M0S管Q4开通过程,M0S管&的作用相当于基本Boo st电路中的开关管,通过M0S管Q2给储能电感L充电,将储能电容C中的能量转移到储能电感中,为Boost升压电路的开启做准备。 M0S power transistor Q4 turn-on process, M0S tube & amp; base acts like Boo st switch circuit through transistor Q2 M0S inductor L to charge the energy storage capacitor C is transferred to the inductor in preparation for the open of boost circuit.

[0027] M0S管Q3为N沟道型M0SFET,栅极外接控制信号III,控制M0S管Q3在合适的时刻开通和关断。 [0027] M0S N-channel type transistor Q3 M0SFET, external gate control signal III, the control transistor Q3 M0S at an appropriate timing on and off. 控制信号III同样由一个占空比可调的波形发生器所提供。 III same control signal is provided by a variable duty cycle waveform generator. 在功率M0S管q4开通过程,M0S管Q3的作用相当于基本Boost电路中的“续流二极管”,通过M0S管Q3为储能电感L续流,实现Boost变换器的功能。 Q4 tube M0S power turn-on process, the role of the transistor Q3 corresponds to the basic M0S Boost circuit "freewheeling diode", through transistor Q3 M0S inductor L is freewheeling, functional Boost converter. 在功率M0S管Q4关断过程,M0S管〇2和11103管Q3的作用刚好互换, 在关断过程,M0S管Q3的作用相当于基本Buck电路中的开关管,M0S管Q2的作用相当于基本Buck电路中的“续流二极管”,为储能电感L续流,从而实现Buck变换器的功能。 Just interchanged, M0S tube 〇2 effect transistor Q4 and turn-off power M0S 11103 Q3, during turn-off, action M0S transistor Q3 corresponds substantially Buck switch circuit, the transistor Q2 corresponds role M0S Buck basic circuits "freewheeling diode", is a freewheeling inductor L, to perform the functions of the Buck converter.

[0028]功率M0S管〇4为财勾道型功率M0SFET,代表开关变换器中需要被驱动的M0SFET。 [0028] Power for the money M0S tube 〇4 power M0SFET channel type, the representative needs to be driven M0SFET switching converter. [0029]如图2,是图1示原理图中的关键节点A、B、C,这三点处的信号波形就能反映出该电路是否能够正常工作。 [0029] FIG. 2, FIG. 1 is a schematic diagram of key nodes A, B, C, signal waveforms at three points can reflect whether the circuit to work properly.

[0030]如图3,是实施例电路原理图。 [0030] FIG. 3 is a schematic diagram of the circuit embodiment. 本发明在具体实施过程中元器件参数以及器件型号均如图3所示。 The present invention and a device model component parameters in a specific implementation are shown in Figure 3.

[0031 ]如图4,是本发明提出的驱动电路正常工作时的时序波形图,最终在图2所示的关键节点C处,得到高低电平交替变换的开关信号,达到驱动功率M0S管Q4的目的。 [0031] FIG. 4 is a timing waveform chart showing a driving circuit of the present invention proposed work, the final node key at C in FIG. 2, to obtain the switching signal alternating high and low and transistor Q4 to achieve the drive power M0S the goal of.

[0032]如图5,是采用传统串接栅极驱动电阻方案和采用本发明提出的驱动方案,在不同的开关频率下,驱动电路效率的对比图。 [0032] FIG. 5 is a series gate resistor conventional scheme and with the driving scheme proposed by the present invention, at different switching frequencies, the driving circuit efficiency comparison chart. 从图5中可以看到,随着开关频率的提高,驱动电路的效率都有所下降。 As it can be seen in FIG. 5, as the switching frequency increases, the efficiency of the driving circuit has declined. 但是采用本发明提出的驱动方案,在较高的开关频率下,效率均高于传统的栅极串接驱动电阻方案的效率。 However, the drive scheme employed by the present invention, at higher switching frequencies, efficiency is higher than the efficiency of conventional gate drive resistor connected in series scheme.

[0033] 直流电压源V串接M0S管&的漏极,1^[03管&的栅极外接控制信号I,!\103管01的源极分别与储能电容C、储能电感L的一端相连接,储能电容C的另一端接地,储能电感L的另一端串接M0S管Q3的源极,M0S管Q3的栅极外接控制信号III,M0S管Q2的漏极与变换器中功率M0S 管Q4的栅极相连,功率M0S管Q4的源极接地,储能电感和1!03管出的公共端与M0S管Q2的漏极相接,M0S管Q2的栅极外接控制信号II,M0S管Q2的源极接地。 [0033] The DC voltage source V series M0S tube & amp; drain, 1 ^ [03 & amp; external gate control signal the I, \ 103 source electrode 01 and the storage capacitor C, respectively, the energy storage inductor! L is connected to one end, the other end of L other end of the storage capacitor C, the inductor connected in series M0S Q3 is a source, a gate of the external control signal M0S III transistor Q3, the drain of transistor Q2 transform M0S M0S vessel connected to the gate of power transistor Q4, Q4 power source M0S tube is grounded, and the inductor 1! 03 in contact with the common terminal of the drain transistor Q2 M0S, M0S external control gate of transistor Q2 signal II, M0S source transistor Q2 is grounded.

[0034] 本发明在M0S管Q4开通时,电路可以等效成为基本的Boost电路,此时M0S管Q2相当于Boost电路中的“续流二极管”;在M0S管Q4关断时,电路可以等效成为基本的Buck的电路, 此时M0S管Q2相当于Buck电路中的“续流二极管”。 [0034] The present invention, when transistor Q4 M0S opened, the circuit may be substantially equivalent to the Boost circuit, this time corresponds to transistor Q2 M0S Boost circuit "freewheeling diode"; M0S when transistor Q4 is turned off, the circuit can wait Buck efficiency of the circuit as the basic, this time corresponds to transistor Q2 M0S Buck circuit "freewheeling diode." 而且,在M0S管Q4关断时,M0S管Q4栅极电荷,并没有通过外接栅源泄放电阻或者M0S管内部寄生栅源电阻消耗掉,而是通过等效的Buck电路回馈到储能电感,最后返回到储能电容中,降低M0S管的Q4的开关损耗,同时也降低了M0S管的栅极驱动电路损耗,有助于提高系统的效率及可靠性。 Further, when the transistor Q4 is turned off M0S, M0S gate charge transistor Q4, the gate and not through an external source or an internal resistance of the bleeder tube M0S gate-source parasitic resistance consumed, but rather fed back into the inductor circuit by an equivalent Buck , and finally returned to the storage capacitor, reducing the switching loss M0S tube and Q4, but also reduces the loss of the gate driving circuit M0S tube, help improve the efficiency and reliability of the system.

[0035]本发明工作过程如下: [0035] The operation of the present invention is as follows:

[0036] 如图4所示,系统上电瞬间,控制信号I给出,使控制信号I变为高电平,M0S管&实现开通,直流电压源开始给储能电容充电。 [0036] As shown in FIG 4, the moment of power system, the control signal I is given, the control signal I becomes high, M0S tube & amp; achieve opening, the DC voltage source begins to charge storage capacitor. 经过0〜七时间,控制信号I变为低电平,将M0S管Qi关断。 0~ seven elapsed time, the control signal I goes low, the tube M0S Qi off. 此时储能电容中获得能量。 In this case the energy storage capacitor is obtained.

[0037] 经过以〜^时间之后,控制信号II给出,使控制信号II变为高电平,M0S管&实现开通,开始有电流通过储能电感,储能电感开始储能,储能电容中能量开始传递到储能电感中。 [0037] In ~ ^ after the time elapsed, a control signal II is given, the control signal becomes high level II, tubes M0S & amp; achieve open, current begins to flow through the inductor, inductor begins to be recharged, storage capacitor energy begins to transfer energy storage inductance.

[0038] 经过t2〜t3时间之后,控制信号II变为低电平,M0S管Q2关断。 [0038] After t2~t3 time, the control signal becomes low level II, M0S transistor Q2 is turned off. 由于电感电流不能突变,就会在M0S管Q2的漏极产生一个上升的电压。 Since the inductor current can not change instantaneously, the voltage will produce a rise in the drain of transistor Q2 M0S. 然后经过t3〜t4死区时间,在U时刻,控制信号III给出,控制信号III变为高电平,M0S管Q3实现开通。 Then through t3~t4 dead time, at the time U, III gives the control signal, the control signal becomes high level III, M0S transistor Q3 to achieve opening. 此时电路等效成为一个基本的Boost电路,电感中的能量开始给M0S管Q4的栅源电容充电,M0S管Q4开始导通,经过t4〜t5时间,将控制信号III变为低电平,M0S管Q2关断,之后M0S管Q4的栅源电压稳定在14U0S管q4实现开通。 At this time, an equivalent circuit becomes a basic Boost circuit, energy in the inductor begins charging tube Q4 gate-source capacitance to M0S, M0S transistor Q4 starts conducting, t4~t5 elapsed time, the control signal becomes low level III, M0S transistor Q2 is turned off, the gate-source voltage of the tube after M0S Q4 is stabilized 14U0S implemented q4 tube opening. 此时,M0S管Qi、M0S管Q2、M0S管Q3均处于关断状态,而且由于M0S管%接入电路中的方式,是漏极连接被驱动的功率M0S管Q4的栅极,避免了在M0S管Q3关断器件,功率M0S管Q4 栅源电容上面的电荷通过M0S管Q3的体二极管进行泄放,这样就可以保证功率M0S管以在七5 〜t6期间可靠地导通。 In this case, the tube M0S Qi, Q2 M0S tube, M0S transistor Q3 are in an off state, and because the access% M0S tube circuit embodiment, the drain is connected to the gate of the driving power M0S Q4, avoiding the M0S transistor Q3 off device, the power capacitor above the gate source transistor Q4 M0S electric charges through the body diode M0S bleeder transistor Q3, so as to ensure a reliable power M0S tube turned during seven 5 ~t6.

[0039] 在t6时刻,给出控制信号III,使控制信号III变成高电平,M0S管Q3实现开通。 [0039] At t6, the control signal is given III, III of the control signal attains a high level, transistor Q3 M0S achieve opening. 此时由于M0S管Q2处于关断状态,则功率M0S管Q4的栅源电容上面的电荷就通过储能电感又回馈到储能电容中,电容上的电压在此时段会出现稍微的上升,此时电路等效成为一个基本的Buck电路。 M0S this time, since transistor Q2 is in the off state, the gate-source capacitance of the above M0S transistor Q4 to turn the power back into the charge storage capacitor through the inductor, the voltage across the capacitor in this period will be slightly increased, this when the equivalent circuit as a basic circuit Buck. 经过t6〜t7时间,控制信号III变为低电平,将M0S管Q3关断。 T6~t7 elapsed time, the control signal III to the low level, the transistor Q3 is turned off M0S. 此时,M0S管Q4的栅源电压已经稳定在〇. 7V左右,使M0S管Q4可靠地截止。 At this time, M0S Q4 gate-source voltage of the tube has stabilized in the square. About 7V, so M0S transistor Q4 is turned off reliably.

[0040] 经过t7〜t3死区时间,在t8时刻控制信号II给出,使得控制信号II变成高电平,M0S 管Q2实现开通,作用相当于基本Buck电路中的“续流二极管”,从而为储能电感续流。 [0040] After t7~t3 dead time, the control signal is given at time t8 II, II such that the control signal attains a high level, transistor Q2 M0S achieve the opening, acts as a basic circuit Buck "freewheeling diode", so as inductor freewheeling. 经过h 〜t9时间,控制信号II变成低电平,1^08管(}2关断,直至T时刻,电路一个周期的工作状态结束。接下来按照上述的时序,电路周期性地工作。在图2所示的〇点处就会产生高低交替的开关信号,使得功率M0S管Q4周期性地开通和关断,实现驱动开关变换器中功率M0S管Q4的目的。并且还能够实现在功率M0S管Q4关断的时候,将其栅源电容中的能量回馈到储能电容中,降低M0S管Q4的开关损耗,进一步提高整个开关变换器的效率。 H ~t9 elapsed time, the control signal becomes low level II, 1 ^ 08 (2} off, until the time T, the end of a working circuit state periods Next periodically operate according to the aforementioned timing circuit. it will produce alternating high and low signal at 0:00 switch shown in Figure 2, so that the power M0S transistor Q4 is periodically turned on and off, to achieve the purpose of driving the power switching converter M0S transistor Q4., and also enables power M0S when transistor Q4 is turned off, the gate-source capacitance of the energy which is fed back to the storage capacitor, the switching loss is reduced M0S transistor Q4, to further improve the efficiency of the entire switching converter.

Claims (3)

1.一种功率变换器中功率MOS管的栅极驱动电路,其特征在于:包括直流电压源v、M〇s 管Qi、储能电容C、储能电感L、M0S管Q2和M0S管Q3,直流电压源V的正极连接M0S管&的漏极, ^108管^的栅极连接外接控制信号1,1\103管&的源极连接储能电容C的一端和储能电感l的一端,储能电容C的另一端接地,储能电感L的另一端连接M0S管&的漏极和M0S管Q3的源极,M0S 管Q2的栅极连接外接控制信号II,M0S管q2的源极连接直流电压源V的负极并接地,M0S管q3 的栅极连接外接控制信号in,M0S管Q3的漏极作为驱动电路的输出,连接功率变换器中功率M0S管Q4的栅极;外接控制信号I、外接控制信号n和外接控制信号111都是由占空比可调的波形发生器所提供; 上述驱动电路在开关电源中功率M0S管Q4的一个开关周期内,1\103管&只开关一次,在功率M0S管Q4开通过程中,储能电容C中的能量通过 The gate drive circuit for a power converter with power MOS transistors, characterized by: a DC voltage source v, Qi M〇s pipe, the storage capacitor C, inductor L, M0S transistor Q2 and transistor Q3 M0S an anode connected to a DC voltage source V M0S tube & amp; drain, ^ 108 ^ external control signal connected to the gates 1,1 \ 103 & amp; source connected to one end of the storage capacitor C and the inductor l one end to the other end of the storage capacitor C, inductor L is connected to the other end of the pipe M0S & amp; M0S source and the drain of transistor Q3, a gate M0S transistor Q2 is connected to an external control signal II, tubes q2 M0S a source connected to the negative direct voltage source V and to ground, gate of the transistor q3 is connected to M0S external control signal in, the drain of transistor Q3 M0S as output driving circuit, a power converter connected to the power gate of Q4 is M0S; external control signal I, n external control signals and external control signals 111 are provided by a variable duty cycle waveform generator; the drive circuit in a switching cycle of the switching power supply transistor Q4 M0S, 1 \ 103 & amp; only one switch, a power transistor Q4 M0S opening process, the energy in the storage capacitor C by 储能电容C、储能电感L、M0S管Q2和MOS管Q3组成的等效Boost电路传递到功率M0S管Q4的栅极,在功率M0S管Q4关断过程中,功率M0S管Q4栅极上的能量通过由M0S管Q3、M0S管Q2、储能电感L和储能电容C组成的等效Buck电路返回到储能电容C中。 The storage capacitor C, Boost circuit equivalent inductor L, and the transistor Q2 M0S MOS transistor Q3, which is passed to the gate of the power M0S transistor Q4, transistor Q4 M0S power off process, the gate of the power transistor Q4 M0S the energy is returned to the storage capacitor C by an equivalent circuit composed M0S Buck tube Q3, M0S tube Q2, the energy storage inductor L and the capacitance C thereof.
2. 根据权利要求1所述的功率变换器中功率M0S管的栅极驱动电路,其特征在于:所述直流电压源V是一个输出0.7V的恒压源,其作用相当于一个电荷栗。 The gate drive circuit of the power converter 1 M0S power tube as claimed in claim, wherein: the DC voltage source V is an output of 0.7V constant voltage source, which acts as a charge Li.
3. 根据权利要求1或2所述的功率变换器中功率M0S管的栅极驱动电路,其特征在于:所述M0S管Qi、M0S管Q2和M0S管Q3均为N沟道型M0SFET,型号采用IRF120,M0S管Q4为N沟道型M0SFET,型号采用SPW20N60S5,储能电容C为10uF,储能电感L为luH。 The gate drive circuit of a power converter of claim 1 or 2 M0S power tube as claimed in claim, wherein: said tube M0S Qi, transistor Q2 and M0S M0S are N-channel type transistor Q3 M0SFET, model using IRF120, M0S N-channel type transistor Q4 M0SFET, models use SPW20N60S5, the storage capacitor C is 10uF, inductor L is luH.
CN201510703629.7A 2015-10-27 2015-10-27 A power converter gate drive circuit power mos tube CN105245091B (en)

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CN1561576A (en) * 2001-10-01 2005-01-05 皇家飞利浦电子股份有限公司 Gate driver apparatus having an energy recovering circuit
CN103580475A (en) * 2012-07-19 2014-02-12 英飞凌科技奥地利有限公司 Charge recovery in power converter driver stages
CN103715870A (en) * 2013-12-26 2014-04-09 华为技术有限公司 Voltage regulator and resonance gate driver thereof
KR101519850B1 (en) * 2014-07-09 2015-05-14 중앙대학교 산학협력단 Resonant gate driver for driving mosfet

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1561576A (en) * 2001-10-01 2005-01-05 皇家飞利浦电子股份有限公司 Gate driver apparatus having an energy recovering circuit
CN103580475A (en) * 2012-07-19 2014-02-12 英飞凌科技奥地利有限公司 Charge recovery in power converter driver stages
CN103715870A (en) * 2013-12-26 2014-04-09 华为技术有限公司 Voltage regulator and resonance gate driver thereof
KR101519850B1 (en) * 2014-07-09 2015-05-14 중앙대학교 산학협력단 Resonant gate driver for driving mosfet

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