CN105206575A - 多种金属栅的集成方法 - Google Patents

多种金属栅的集成方法 Download PDF

Info

Publication number
CN105206575A
CN105206575A CN201510657573.6A CN201510657573A CN105206575A CN 105206575 A CN105206575 A CN 105206575A CN 201510657573 A CN201510657573 A CN 201510657573A CN 105206575 A CN105206575 A CN 105206575A
Authority
CN
China
Prior art keywords
metal
grid
integrated approach
various metals
metal gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510657573.6A
Other languages
English (en)
Inventor
黎明
杨远程
陈珙
樊捷闻
张昊
黄如
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peking University
Original Assignee
Peking University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University filed Critical Peking University
Priority to CN201510657573.6A priority Critical patent/CN105206575A/zh
Publication of CN105206575A publication Critical patent/CN105206575A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开了一种多种金属栅的集成方法，属于超大规模集成电路制造技术领域。该方法基于后栅工艺“逐次剥离”，采用剥离工艺实现多种金属栅的集成方法，相比TakashiMatsukawa等的“淀积—退火合金”方法，本方法无附加热预算，提高了工艺的均匀性和可控性；且降低了刻蚀损伤，降低了工艺难度，扩大了材料的选择范围。

Description

多种金属栅的集成方法
技术领域
本发明属于超大规模集成电路制造技术领域，涉及一种通过逐次剥离实现多种金属栅集成的方法。
背景技术
随着半导体器件特征尺寸缩小，为更有效地抑制短沟效应、提高驱动能力，器件的栅介质等效电学厚度(EquivalentElectricalThickness，EOT)不断降低；但是，常规介质(如SiO2、SiON等)主要是通过减小介质的物理厚度来减小EOT，因此引起栅泄漏电流的增大。为了抑制栅泄漏电流，同时提高驱动能力(即在不明显减小介质物理厚度的情况下，减小介质的EOT)，需要采用高介电常数介质(High-kdielectric，HK介质)。由于HK介质的界面特性和热稳定性均不及传统SiO2，不能与多晶硅栅有效兼容，因而需要使用金属栅(MetalGate，MG)。正是因为HK-MG的引入，促使工业界开发后栅(Gate-Last)工艺以降低对HK介质和金属栅的热损伤；另一方面，全耗尽器件(如FinFET、FD-SOI、Nanowire等)的阈值调整依赖于多种金属功函数。因此，基于后栅工艺实现多种金属栅的集成成为一门富有挑战性的课题。
目前，见诸报道的多种金属栅的集成方案有如下几种：
传统的是逐次“淀积——刻蚀”的集成方法。该方法依赖于多次刻蚀工艺，易造成刻蚀损伤(尤其对于表面形貌复杂的非平面器件，如FinFET等)，且均匀性和可控性较差。
TakashiMatsukawa等[TakashiMatsukawaetal.,EDL,2008,29(6):618～620]报道了一种“淀积——退火合金”的集成方法。该方法中的多层金属合金退火过程增加了额外的热预算，降低了器件可靠性；此外，合金的均匀性与可控性也较差。
因此，业界急需一种均匀性和可控性都好的多种金属栅的集成方法。
发明内容
针对以上问题，本发明提供一种基于后栅工艺的“逐次剥离”实现多种金属栅的集成方法，以改善现有的公知技术。
本发明实现多种金属栅的集成方法的具体技术方案如图1所示，包括如下步骤：
1)与公开的后栅工艺类似，先制备源漏掺杂和假栅等前道工艺；
2)假栅去除后，淀积HK介质，再淀积一层薄金属作为缓冲层；
3)光刻露出器件1(此处将共同使用金属栅1的一类器件定义为器件1)，不局限于一个器件，不局限于一种尺寸(可以是小尺寸器件，如高性能的逻辑器件；也可是大尺寸器件，如I/O器件)，不局限于一种类型(可以是NFET，也可是PFET)；依次类推，定义器件2、器件3、器件n；
淀积金属1，通过机械剥离实现金属栅只在一种器件1的区间内存在；
4)光刻露出器件2；
淀积金属2，通过机械剥离实现金属栅2只在另一种器件2的区间内存在；
5)依次类推，可以扩展到n种器件情形；
6)清洗后填充金属M，作为n种器件金属栅的导电层；
7)通过对金属M进行化学机械抛光(CMP)，实现多种器件之间的导电层分离，达到器件隔离的效果。
进一步地，本方法适用于各种半导体衬底，包括体硅衬底，SOI衬底，体锗衬底，GOI衬底，化合物衬底等；
进一步地，本方法适用于需使用金属栅的各种类型的半导体器件，包括传统平面器件，FinFET器件，FDSOI器件，纳米线器件等；
进一步地，作为缓冲层的金属需要具有与HK介质间良好的界面特性、良好的热稳定性和化学稳定性，如TaN、TiN等，淀积方法优选保形性好的原子层淀积(ALD)；
进一步地，作为调节功函数的金属栅，金属栅1～金属栅n需具备不同大小的功函数，其中较小功函数的的n型金属可选择Al、Ti、AlTiN等；中等大小功函数的中禁带金属可选择TiN、TaN等；较大功函数的的p型金属栅可选择Pt、Ru、W、富氮的TiN等；
进一步地，金属1～金属n的淀积方式可以是物理气相淀积(PVD)，也可为化学气相淀积(CVD)。为更好地适应剥离工艺，优选非保形的PVD方式，如电子束蒸发等；
进一步地，作为导电层的填充金属M，需要具备低的电阻率，可选择W、Cu等。
本发明的优点和积极效果如下：
1)相比传统的逐次“淀积——刻蚀”方法，本方法大幅减少了刻蚀的次数，降低了刻蚀损伤，提高了工艺的均匀性和可控性；
2)剥离工艺能实现不易刻蚀的材料(如Pt、W等)的图形化，降低了工艺难度，扩大了材料的选择范围；
3)相比TakashiMatsukawa等的“淀积——退火合金”方法，本方法无附加热预算，提高了工艺的均匀性和可控性。
附图说明
图1是本发明提出的逐次剥离法实现多种金属栅集成的工艺流程示意图。
图2-10为各关节工艺的剖面图。
其中：
图2按标准平面器件流程行进至源漏杂质激活；
图3淀积隔离层，CMP露出假栅顶部；
图4依次淀积HK栅介质和缓冲金属层；
图5光刻器件1的栅图形，非保形淀积金属1；
图6剥离实现金属1的图形化，即实现金属1只在器件1的区间内存在；
图7相同方法实现金属2、金属3的图形化；
图8清洗后，填充导电金属M；
图9通过对金属M进行化学机械抛光(CMP)，实现器件之间的导电层分离，达到器件隔离的效果；
图10为图2-图9的图例说明。
具体实施方式
下面结合附图和具体实例对本发明进行详细说明。
实施例1：
根据下列步骤可以实现具有3种阈值(Vt1、Vt2、Vt3；其具体值根据不同技术代的要求及不同类型器件(如高性能逻辑器件、低功耗逻辑器件、I/O器件等)的性能进行设定的体硅平面器件：
1)在(100)体硅衬底上按标准体硅平面工艺加工，直至源/漏杂质激活，如图2所示；
2)PECVDSiO2作为隔离层；
3)CMPSiO2直至露出假栅顶部；
4)各向同性刻蚀去除假栅，如图3所示；
5)ALD1.5nmHfO2作绝缘栅介质；
6)ALD5nmTaN作缓冲层，如图4所示；
7)光刻器件1(如具有阈值Vt1)的栅线条(栅线条处的光刻胶显影时被去除)；
8)非保形淀积金属1(如TaN)10nm，如图5所示；
9)通过剥离，实现金属栅1的图形化，如图6所示；
10)按相同方法，依次实现金属栅2(用于形成具有阈值Vt2的器件2)(如Al)、金属栅3(用于形成具有阈值Vt3的器件3)(如Pt)的图形化，如图7所示；
11)清洗后，PVD填充金属M(如Cu)作为导电金属，如图8所示；
12)对金属M进行化学机械抛光(CMP)，实现器件之间的导电层分离，达到器件隔离的效果，如图9所示；
13)后续按标准体硅平面后端工艺完成器件集成。
实施例2：
在实施例1的基础上，作如下调整，可以实现3种阈值的体硅FinFET器件：
1)实施例1步骤1中，在(100)体硅衬底按标准体硅FinFET工艺加工，直至源/漏杂质激活；
2)实施例1步骤5中，HK介质的种类和厚度可根据实际技术节点要求进行优化调整；
3)实施例1步骤8、10中，金属1、金属2、金属3的种类和厚度可根据实际技术节点要求进行优化调整；
4)实施例1步骤11中，金属M的种类和厚度可根据实际技术节点要求进行优化调整；
5)实施例1步骤13中，后续按标准体硅FinFET后端工艺完成器件集成。
本发明实施例并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (7)

1.一种多种金属栅的集成方法，包括以下步骤：
1)在衬底上按标准体硅平面工艺加工，制备源/漏和假栅，直至源/漏杂质激活；
2)去除假栅，淀积HK介质，再淀积一层薄金属作为缓冲层；
3)光刻露出一种器件，淀积金属，通过机械剥离实现金属栅只在该器件的区间内；
4)重复步骤3)，扩展到n种器件，金属栅1～金属栅n具备不同大小的功函数；
5)清洗后填充金属M，作为n种器件金属栅的导电层；
6)通过对金属M进行化学机械抛光，实现多种器件之间的导电层分离。
2.如权利要求1所述的多种金属栅的集成方法，其特征在于，所述衬底为体硅、SOI、体锗、GOI或化合物衬底。
3.如权利要求1所述的多种金属栅的集成方法，其特征在于，所述器件为传统平面器件、FinFET器件、FDSOI器件或纳米线器件。
4.如权利要求1所述的多种金属栅的集成方法，其特征在于，较小功函数的金属栅选择Al、Ti或AlTiN；中等大小功函数的金属栅选择TiN或TaN；较大功函数的金属栅选择Pt、Ru、W或富氮的TiN。
5.如权利要求1所述的多种金属栅的集成方法，其特征在于，作为缓冲层的金属采用TaN或TiN，淀积方法为原子层淀积。
6.如权利要求1所述的多种金属栅的集成方法，其特征在于，金属栅的淀积方式是物理气相淀积、化学气相淀积或电子束蒸发。
7.如权利要求1所述的多种金属栅的集成方法，其特征在于，作为导电层的填充金属M采用W或Cu。
CN201510657573.6A 2015-10-13 2015-10-13 多种金属栅的集成方法 Pending CN105206575A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510657573.6A CN105206575A (zh) 2015-10-13 2015-10-13 多种金属栅的集成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510657573.6A CN105206575A (zh) 2015-10-13 2015-10-13 多种金属栅的集成方法

Publications (1)

Publication Number Publication Date
CN105206575A true CN105206575A (zh) 2015-12-30

Family

ID=54954158

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510657573.6A Pending CN105206575A (zh) 2015-10-13 2015-10-13 多种金属栅的集成方法

Country Status (1)

Country Link
CN (1) CN105206575A (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6563178B2 (en) * 2000-03-29 2003-05-13 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the device
US6686282B1 (en) * 2003-03-31 2004-02-03 Motorola, Inc. Plated metal transistor gate and method of formation
CN102142367A (zh) * 2010-01-29 2011-08-03 台湾积体电路制造股份有限公司 集成电路的制造方法
CN103077947A (zh) * 2011-10-26 2013-05-01 中国科学院微电子研究所 具有双金属栅的cmos器件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6563178B2 (en) * 2000-03-29 2003-05-13 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the device
US6686282B1 (en) * 2003-03-31 2004-02-03 Motorola, Inc. Plated metal transistor gate and method of formation
CN102142367A (zh) * 2010-01-29 2011-08-03 台湾积体电路制造股份有限公司 集成电路的制造方法
CN103077947A (zh) * 2011-10-26 2013-05-01 中国科学院微电子研究所 具有双金属栅的cmos器件及其制造方法

Similar Documents

Publication Publication Date Title
US11056400B2 (en) Semiconductor device and method
US11342458B2 (en) Semiconductor structure and fabricating method thereof
US10957545B2 (en) Method for manufacturing semiconductor device
US9660075B2 (en) Integrated circuits with dual silicide contacts and methods for fabricating same
US10192969B2 (en) Transistor gate metal with laterally graduated work function
CN106158747B (zh) 半导体结构及其形成方法
US8664054B2 (en) Method for forming semiconductor structure
US20200312849A1 (en) Gate recess uniformity in vertical field effect transistor
JP2020526018A (ja) 半導体デバイスを製造するための方法および半導体デバイス
CN107689395B (zh) 半导体器件和方法
CN109860275A (zh) 半导体器件及其制造方法
US20230282725A1 (en) Semiconductor Devices and Methods of Forming the Same
US9859364B1 (en) Semiconductor device and manufacturing method thereof
US20190148519A1 (en) Semiconductor structure and method for forming the same
CN114975275A (zh) 半导体器件和方法
CN105206575A (zh) 多种金属栅的集成方法
US10128186B2 (en) Simultaneous formation of liner and metal conductor
US9721788B1 (en) Simultaneous formation of liner and metal conductor
US11217480B2 (en) Semiconductor structure with a laminated layer
CN220963349U (zh) 半导体装置
TWI820428B (zh) 電晶體閘極結構及其形成方法
US11257816B2 (en) Method for manufacturing semiconductor device including dummy gate electrodes
US20230343699A1 (en) Field effect transistor with source/drain via and method
US20210090944A1 (en) Semiconductor Structure with Staggered Selective Growth
KR20230034172A (ko) 다수의 트랜지스터 소스들에 대한 자가 정렬된 넓은 후면 파워 레일 접촉부들

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20151230