CN105197880B - A kind of bonding method with cavity chip - Google Patents
A kind of bonding method with cavity chip Download PDFInfo
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- CN105197880B CN105197880B CN201410286773.0A CN201410286773A CN105197880B CN 105197880 B CN105197880 B CN 105197880B CN 201410286773 A CN201410286773 A CN 201410286773A CN 105197880 B CN105197880 B CN 105197880B
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Abstract
The product manufactured the invention discloses a kind of bonding method with cavity chip and according to this method.The problem that raffinate causes bonding quality difference is this method solve, to realize that the bonding of high quality cavity provides good basis.The method according to the invention includes：A) chip to be bonded to two carries out pre-wash with formed with the hydrophilic group beneficial to bonding；B) by two wafer aligneds to be bonded；C) chip after alignment is put into bonding room, room will be bonded and vacuumize and heat to remove the liquid of wafer surface residual.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to bonding method with cavity chip manufactures according to this method
Product.
Background technology
Bonding (bonding) refer to by various chemically and physically effects connect two or more substrates or chip (such as
Chip glass or silicon wafer) process, mainly including gluing bonding, anode linkage, eutectic bonding, melting bonding, glass paste
Bonding, metal are diffusion interlinked etc..With developing rapidly for the 3D manufacturing technologies such as silicon hole (TSV), MEMS, para-linkage technology and key
The requirement of conjunction quality is also further detailed and strictly gets up.
Bonding chip (wafer bonding) is very important technology ring in the manufacture of MEMS (MEMS) device
Section.Vacuum bonding (vacuum bonding) is a kind of important branch in bonding techniques.With the pressure quickly grown in recent years
Exemplified by the devices such as sensor, oscillator, the characteristics of they are common is to be required for forming a vacuum cavity after bonding, and chamber
Internal vacuum is to ensureing that device performance index has highly important effect.
With the rapid development of micromachining technology, there are a kind of new bonding techniques --- Si-Si direct bonding skill
Art, it refers to the material tight such as silicon chip and silicon chip, oxide layer is joined together to form into one by effect chemically and physically
Overall method.Surface Machining and body processing can be organically combined together by it, and important ground is occupied in micromachined
Position.It is often used in combination with other means, can both form micro-structural, forms support and protection to micro-structural, can realize again micro-
Being electrically connected between mechanical structure or between micro mechanical structure and circuit.
For example, during the cavity devices Si-Si bonding based on melting bonding principle, first, pre-wash mistake is carried out
Journey.The purpose is to the hydrophilic group beneficial to bonding is formed in plasma-treated silicon wafer surface.Pre-wash last
Step is usually using centrifugal force (Rotary drying or drying) caused by chuck high speed rotation, by the remaining deionized water of wafer surface
Dry.
Fig. 1 shows the cross-sectional view of the cavity body structure formed by Si-Si bonding process.It will be seen from figure 1 that it is being bonded
Two wafers 101 and 104 between exist large area cavity 102 and with certain depth marking groove (scribe lane)
103.Therefore, in the pre-wash stage, it can not completely remove and be remained in large area cavity and deep trench using only Rotary drying
Deionized water.After the completion of this not only influences bonding, the vacuum and bonding quality of cavity devices, also because empty intracavity liquid is residual
Stay, hidden danger is left safely to device.
At present, for the bonding technology of cavity devices, typically using traditional melting bonding technology method, not yet have
Targetedly cavity devices bonding special process.
Equally, residual liquid minimizing technology relies primarily on Rotary drying to realize.For the cavity that depth-to-width ratio is high, area is big
Device, because the raffinate linear velocity in the different radii upper plenum of chip is different, it can not rely on and extend rotational time or raising
The means such as rotary rpm solve.For example, in the central area of rotation chip, the linear velocity of residual liquid is relatively slow, therefore
Central area cavity residual liquid is relatively more, and when carrying out melting bonding to the chip, the residual liquid in the region can produce
Raw large stretch of space, causes bonding to fail.
In addition, the limitation of subject wafer bonding technology condition, the methods of typically can not also being dried using isopropanol (IPA).
Fig. 2 shows traditional Si-Si bonding process flow chart.
First, in step 201, pre-wash, wherein the two chips are carried out to two wafer surfaces to be bonded
In it is at least one on formed with structures such as cavity, grooves.On the bonding surface of pre-wash stage chip introduce go from
Sub- water, so as to formed with the hydrophilic group beneficial to bonding.Then, using centrifugal force caused by the high speed rotation of wafer chuck, by crystalline substance
The residual level on piece surface dries.
In step 202, by two wafer aligneds to be bonded.
In step 203, two wafer surfaces of alignment are coincided together.It is bonded using the hydrogen bond of wafer surface.
In step 204, two chips through bonding are checked.
In step 205, high annealing is carried out to two chips through bonding to form the stronger siloxanes key (Si- of bond energy
O-Si)。
Tested using traditional silicon silicon cavity bonding technology, found after being analyzed experimental result：In tradition
Under the conditions of Si-Si bonding process, change bonding force, bonding time and surface treatment condition, the improvement of para-linkage quality is very
It is limited.Residual liquid in the wafer produces large stretch of space.
Therefore, removing the liquid of pre-wash stage residual becomes further important.
The content of the invention
It is an object of the invention to provide a kind of method with cavity bonding chip, this method effectively removes and remains in chip device
Residual liquid in part structure, vacuum and bonding quality after cavity devices bonding are improved, while decrease cavity device
The potential safety hazard of part.
According to one embodiment of present invention, there is provided a kind of bonding method of chip, including：
A) chip to be bonded to two carries out pre-wash with formed with the hydrophilic group beneficial to bonding；
B) by two wafer aligneds to be bonded；
C) chip after alignment is put into bonding room, room will be bonded and vacuumize and heat to remove the liquid of wafer surface residual
Body.
According to one embodiment of present invention, preceding method is additionally included in before step a), to wafer surface to be bonded
Carry out activation process.
According to one embodiment of present invention, it is clear in advance by the way that deionized water is introduced into bonding surface progress in step a)
Wash.
According to one embodiment of present invention, step c) one or more of comprises the following steps step：
C1) bonding room is vacuumized and kept for certain time；
C2) it is filled with to form gas to bonding room；
C3) bonding room is heated in specified temp and kept for certain time；
C4) bonding room is vacuumized and kept for certain time again.
According to one embodiment of present invention, step c) is additionally included in step c4) it is filled with to be formed to bonding room again afterwards
Gas, then bonding room is vacuumized and kept for certain time.
According to one embodiment of present invention, the mixed gas that gas can be nitrogen and hydrogen is formed, is filled with the shape
The indoor air pressure of the bonding is at least 800 millibars after into gas.
According to one embodiment of present invention, specified temp is between 22 DEG C to 80 DEG C.
According to one embodiment of present invention, specified temp is 60 DEG C.
According to one embodiment of present invention, preceding method is also annealed including the chip after para-linkage.
According to one embodiment of present invention, at least one wafer surface to be bonded has cavity structure.
According to another embodiment of the invention, there is provided a kind of semiconductor devices, including the key manufactured by preceding method
Close structure.
Compared with prior art, advantages of the present invention includes：
The method according to the invention is directed to cavity devices bonding performance, proposes to utilize vacuum in conventional melt bonding technology
Drying principles, solves the problem that raffinate causes bonding quality difference, to realize that the bonding of high quality cavity provides good basis.Together
When, this method is small to existing process reschedualing without newly added equipment, has the advantages that cost is low, risk is small, implementation is strong.
Brief description of the drawings
For the above and other advantages and features of each embodiment that the present invention is furture elucidated, refer to the attached drawing is presented
The more specifically description of various embodiments of the present invention.It is appreciated that these accompanying drawings only describe the exemplary embodiments of the present invention, therefore
It is restriction on its scope to be not to be regarded as.In the accompanying drawings, in order to cheer and bright, layer and the thickness in region are exaggerated.It is identical or
Corresponding part will be represented with same or similar mark.
Fig. 1 shows the cross-sectional view of the cavity body structure formed by Wafer Bonding Process.
Fig. 2 shows traditional Wafer Bonding Process flow chart.
Fig. 3 A-3G show the schematic diagram of the bonding chip according to one embodiment of the present of invention.
Fig. 4 shows the flow chart of Wafer Bonding Process according to an embodiment of the invention.
Fig. 5 shows the three-phase diagram of water.
Embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case of neither one or multiple specific details or with it is other replacement and/or addition method, material or component
Implement each embodiment together.In other situations, it is not shown or known structure, material or operation is not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to embodiments of the invention is just provided.However, the present invention can be implemented in the case of no specific detail.This
Outside, it should be understood that each embodiment shown in accompanying drawing is illustrative expression and is not drawn necessarily to scale.
Fig. 3 A-3G show the schematic diagram of the bonding chip according to one embodiment of the present of invention.
First, two wafer surfaces being bonded are carried out with activation process, it is at least one in the two chips
Surface is formed with structures such as cavity, grooves.
In the activation process stage of bonding surface, as shown in Figure 3A, the surface of silicon wafer is bombarded using nitrogen gas plasma,
Because autoxidation acts on, there is Si-O keys on the surface of silicon wafer.As shown in Figure 3 B, due to plasma bombardment, silicon face
Part Si-O keys in natural oxidizing layer interrupt, and form dead key, as shown in Figure 3 C.
Then, the pre-wash stage is carried out, deionized water is introduced in plasma-treated wafer surface, and make it
Combined with Si- dead keys, formed with the hydrophilic group beneficial to bonding, as shown in Figure 3 D.Deionized water can be applied using dropping liquid-spin coating mode
It is distributed on the surface of silicon wafer.Centrifugal force caused by generally being rotated at a high speed using wafer chuck in the prior art, surface is residual
Remaining moisture dries.But chamber can not be removed completely for the cavity containing large area or the chip of deeper groove, this method
Residual moisture in body or groove, so as to cause bonding to fail.In order to overcome this problem, in an embodiment of the present invention, lead to
Cross and vacuumize-toast-vacuum step in bonding stage increase, remained in remove the pre-wash stage in wafer device structure
Hydrone.Bonding process is described in detail below with reference to Fig. 4.Enter to be about to two using the hydrogen bond of wafer surface in this process
Bonding chip together, as shown in FIGURE 3 E.
Annealing stage, as illustrated in Figure 3 F, using pyroreaction, the stronger siloxanes key (Si-O-Si) of bond energy is formed, is such as schemed
Shown in 3G.
Fig. 4 shows the flow chart of Wafer Bonding Process according to an embodiment of the invention.
First, in step 401, activation process is carried out to two wafer surfaces to be bonded.In one embodiment,
Surface active can be carried out by N2 plasma bombardments.
In step 402, plasma-treated chip carries out pre-wash.In one embodiment, can be by that will go
Ionized water, which introduces bonding surface, to be come formed with the hydrophilic group beneficial to bonding.
In step 403, by two wafer aligneds to be bonded.In one embodiment, chip to be bonded can be put into crystalline substance
Piece is directed at the chuck of machine, and wafer aligned is completed using the machine that is aligned, and wafer chuck then is put into bonding room.
In step 404, bonding room is vacuumized and kept for certain time.In one embodiment, bonding room can be taken out very
Sky is kept for 5 minutes to 1 millibar.
Optionally, in step 405, can be filled with to form gas to bonding room.In one embodiment, the formation gas being filled with
It is hydrogen and nitrogen, and is filled with to form after gas the air pressure for being bonded room and be at least 800 millibars.
In step 406, bonding room is kept 5 minutes at a certain temperature.In one embodiment, the specified temp is 22
DEG C between 80 DEG C.For example, the specified temp can be 60 DEG C.
In step 407, bonding room is vacuumized and kept for certain time again.In one embodiment, room will can be bonded
0.01 millibar is evacuated to, and is kept for 5 minutes.
Optionally, in step 408, can be filled with to form gas to bonding room again.In one embodiment, the formation being filled with
Gas is hydrogen and nitrogen, and is filled with to form after gas the air pressure for being bonded room and be at least 800 millibars.
In step 409, bonding room is vacuumized and kept for certain time again.
In one embodiment, in order to further reduce the concentration of the indoor vapor of bonding, step 408 can be repeated several times
With 409.
In step 410, two chips through bonding are checked.In one embodiment, can be shown by scanning electron
Micro mirror is observed, and whether has large stretch of space between chip.Can also check chip whether flexural deformation.
In step 411, high annealing is carried out to two chips through bonding to form the stronger siloxanes key (Si- of bond energy
O-Si).In one embodiment, the annealing temperature of chip is about 300 DEG C.
Using above-mentioned bonding method, by vacuumizing-toasting-vacuum step in bonding stage increase, eliminate in advance
The raffinate that wash phase is remained in wafer device structure, vacuum and bonding quality after cavity devices bonding are improved, together
When decrease the potential safety hazards of cavity devices.
It is can be seen that from the three-phase diagram of the water shown in Fig. 5 in drying process, the vaporization of aqueous water has two kinds of evaporation and boiling
Mode.Vaporization rate of the water in boiling is more faster than the vaporization rate in evaporation, and moisture evaporation becomes steam can be with office
What carried out at a temperature of.Moisture boiling becomes steam, can only carry out at a certain temperature.But when pressure is reduced, water
Boiling point also reduces.Such as under 19.6kPa air pressure, the boiling point of water can drop to 60 DEG C.
Therefore, according to the present invention bonding method make full use of water under low pressure boiling point reduce the characteristics of, and bonding room
Under interior formed vacuum state, by heat transfer types such as heat transfer, heat radiations, the enough heats of sustainable supply moisture, promote brilliant
The boiling of piece remained on surface liquid, accelerate vaporization rate.Meanwhile vacuumize and quickly extract the steam of vaporization out, and in chip week
Enclose to form negative pressure state, make to form larger moist gradient between chip and surrounding medium, accelerate vaporization rate, reach quick
Dry purpose.
In step 405 and 408, the purpose to form gas is filled with to bonding room during bonding and is on the one hand to make key
Close indoor holding and be specifically bonded atmosphere, the formation gas being on the other hand filled with, which can reduce, is bonded indoor vapor and other gases
The concentration of impurity, so as to be advantageous to accelerate to dry and provide bonding yield rate.
The foregoing describe some embodiments of the present invention.However, the present invention can be embodied as other concrete forms without carrying on the back
From its spirit or essential characteristics.Described embodiment should all be to be considered merely as illustrative and not restrictive in all respects.
Therefore, the scope of the present invention by appended claims rather than described above limits.Fall into the equivalents of claims
All changes in implication and scope are covered by the scope of claims.
Claims (8)
1. a kind of bonding method of chip, including：
A) chip to be bonded to two carries out pre-wash with formed with the hydrophilic group beneficial to bonding；
B) by two wafer aligneds to be bonded；
C) chip after alignment is put into bonding room, room will be bonded and vacuumize and heat to remove the liquid of wafer surface residual；
D) chip after para-linkage is annealed；
Wherein, the step c) comprises the following steps：
C1) bonding room is vacuumized and kept for certain time；
C2) it is filled with to form gas to bonding room；
C3) bonding room is heated in specified temp and kept for certain time；
C4) bonding room is vacuumized and kept for certain time again,
Wherein, the formation gas being filled with is the mixed gas of nitrogen and hydrogen, to form specific bonding atmosphere.
2. the method as described in claim 1, being additionally included in before step a), wafer surface to be bonded is carried out at activation
Reason.
3. the method as described in claim 1, it is characterised in that carried out in step a) by the way that deionized water is introduced into bonding surface
Pre-wash.
4. the method as described in claim 1, it is characterised in that the step c) is additionally included in step c4) afterwards again to key
Close room to be filled with to form gas, then bonding room is vacuumized and kept for certain time.
5. the method as described in claim 1, it is characterised in that be filled with the indoor air pressure of the bonding after the formation gas extremely
It is 800 millibars less.
6. the method as described in claim 1, it is characterised in that the specified temp is between 22 DEG C to 80 DEG C.
7. the method as described in claim 1, it is characterised in that the specified temp is 60 DEG C.
8. the method as described in claim 1, it is characterised in that at least one wafer surface to be bonded has cavity structure.
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| CN201410286773.0A CN105197880B (en) | 2014-06-24 | 2014-06-24 | A kind of bonding method with cavity chip |
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| CN109671614B (en) | 2017-08-10 | 2020-08-21 | 长江存储科技有限责任公司 | Wafer bonding method |
| CN108439814B (en) * | 2018-04-25 | 2021-04-20 | 哈尔滨工业大学 | Plasma activation direct bonding method for surface pretreatment by using water vapor |
| CN109844915A (en) * | 2019-01-02 | 2019-06-04 | 长江存储科技有限责任公司 | Plasma-activated processing for wafer bonding |
| CN114777427B (en) * | 2022-05-10 | 2023-11-17 | 星恒电源股份有限公司 | Drying method for square laminated lithium ion battery cell |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102020235A (en) * | 2010-11-11 | 2011-04-20 | 北京自动化控制设备研究所 | Low-moisture content packaging method for thin outline (TO) packaging structure and packaging assembly thereof |
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| CN1028191C (en) * | 1992-11-10 | 1995-04-12 | 东南大学 | Silicon chip directive bonding method |
| WO2003097552A1 (en) * | 2002-04-30 | 2003-11-27 | Agency For Science Technology And Research | A method of wafer/substrate bonding |
| US7601271B2 (en) * | 2005-11-28 | 2009-10-13 | S.O.I.Tec Silicon On Insulator Technologies | Process and equipment for bonding by molecular adhesion |
| EP2091071B1 (en) * | 2008-02-15 | 2012-12-12 | Soitec | Process for bonding two substrates |
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| CN102020235A (en) * | 2010-11-11 | 2011-04-20 | 北京自动化控制设备研究所 | Low-moisture content packaging method for thin outline (TO) packaging structure and packaging assembly thereof |
Non-Patent Citations (1)
| Title |
|---|
| "Si/Si直接键合界面性质的研究""Si/Si直接键合界面性质的研究";陈松岩等;《固体电子学研究与进展》;20040831;第24卷(第3期);第390-395页，正文2.1部分 * |
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