CN103871953B - A kind of shallow groove filling method - Google Patents
A kind of shallow groove filling method Download PDFInfo
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- CN103871953B CN103871953B CN201410106819.6A CN201410106819A CN103871953B CN 103871953 B CN103871953 B CN 103871953B CN 201410106819 A CN201410106819 A CN 201410106819A CN 103871953 B CN103871953 B CN 103871953B
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- Prior art keywords
- shallow trench
- shallow
- filling method
- silicon dioxide
- shallow groove
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
Abstract
The invention discloses a kind of channel filling method, its method is: provide a semiconductor structure being formed with shallow trench；Use high density plasma CVD technique to fill silica membrane in described shallow trench, and make the top of described silica membrane be in the top distance below of described semiconductor structure；The surface exposed in described groove is carried out thermal oxidation technology, with the certain thickness silicon dioxide of continued growth；Carry out annealing process；Using plasma chemical vapor deposition method continues to prepare silicon dioxide, to fill the remainder in shallow trench.So can be thermally oxidized by the surface single crystal silicon of plasma damage thus repair the damage at shallow trench top, and the top of shallow trench is only the region of device work, the reparation therefore damaged can be greatly improved device reliability.
Description
Technical field
The present invention relates to 40 nanometers and following shallow trench technical field, refer more particularly to one
Shallow groove filling method.
Background technology
Along with being pushed further into of Moore's Law, the integrated level of the integrated circuit that we are required is more
Come the highest, so the isolation structure of each components and parts must be according to identical ratio between integrated circuit
Reducing, wherein along with the generation of beak effect, so-called beak effect refers to one
Semiconductor substrate layer forms rostriform shallow trench through over etching.
At present, the degree of depth of the shallow trench below 40 nanometers about 3000 Ethylmercurichlorendimide, width is only 400
To about 800 Ethylmercurichlorendimides, its ratio great disparity is excessive, the liquid source of widely used predominantly AMAT
Low-pressure chemical vapor deposition (HARP) and the high density plasma CVD of NVLS
(HDP-CVD) two kinds of technique, but the HARP technique of this AMAT want to carry out to groove without
The filling in space, it is necessary to combine wet method annealing, the silicon inside groove can be consumed, cause active
The size in district diminishes, even if NVLS and HDP-CVD carries out the filling of groove and need not wet method and move back
Fire, but owing to the density of plasma is higher, and along with dry etching, high-octane
Silicon in shallow trench can be bombarded the damage causing silicon by plasma, if these damage fruits are not repaiied
Defect will be become again, the reliability of device is caused bad impact, even influences whether good
Rate.
Chinese patent (CN1979797A) discloses a kind of sti trench groove fill method, including
Substrate is placed in reative cell, substrate is formed groove；Utilize in the reaction chamber and comprise sputtering
The chemical vapor deposition method of technique fills silicon oxide in the trench, the reaction gas used in it
Body includes oxygen and the silane that chemical vapor deposition method uses, and the hydrogen that sputtering technology uses
Gas and helium；Continue in reative cell, be passed through oxygen, described oxygen carried out plasma treatment,
High density oxygen gas plasma is utilized to remove the silicon particle of residual in silicon.
Disclosed in above-mentioned patent, a kind of sti trench groove is filled and can enough be removed in silica-filled film
The silicon particle of residual, thus improves the quality of filling film, but operates more complicated and filling out
The silicon sustained damage is not repaired during filling, the reliability to device can be caused
Produce harmful effect.
Summary of the invention
In view of the above problems, the present invention provides a kind of shallow groove filling method.Come in this way
Replace existing technology, can repair by the surface single crystal silicon of highdensity plasma damage, greatly
The big reliability that improve device.
The present invention solves the technical scheme that the problems referred to above are used:
A kind of shallow groove filling method, it is characterised in that described method includes:
Step S1, offer one are formed with the semiconductor structure of shallow trench；
Step S2, employing high density plasma CVD technique are at described shallow trench
Middle filling silica membrane, and make the top of described silica membrane be in described quasiconductor
The top distance below of structure；
Step S3, in described groove expose surface carry out thermal oxidation technology, with continues give birth to
Long certain thickness silicon dioxide；
Step S4, carry out annealing process；
Step S5, using plasma chemical vapor deposition method continue to prepare silicon dioxide,
To fill the remainder in shallow trench.
Above-mentioned a kind of shallow groove filling method, it is characterised in that described semiconductor structure includes
One substrate and the etching barrier layer being positioned on described substrate, and by successively to described etch stopper
Layer and described substrate perform etching, and form described shallow trench.
Above-mentioned a kind of shallow groove filling method, it is characterised in that to described etching barrier layer and
After described substrate performs etching, also include cleaning, to form described shallow trench.
Above-mentioned a kind of shallow groove filling method, it is characterised in that described silica membrane
Top is in below described semiconductor structure top at least 300 Ethylmercurichlorendimides.
Above-mentioned a kind of shallow groove filling method, it is characterised in that in step S3, described two
The thickness of silicon oxide is that 30 Ethylmercurichlorendimides are to 100 Ethylmercurichlorendimides.
Above-mentioned a kind of shallow groove filling method, it is characterised in that use same process equipment to enter
High density in plasma activated chemical vapour deposition technique in row step S5 and step S2 etc. from
Daughter chemical vapor deposition method.
Technique scheme has the advantage that or beneficial effect:
A kind of shallow groove filling method, through filling silica membrane, then uses thermal oxide
Consuming the monocrystal silicon come out, thus repair the damage at shallow trench top, top is device work
The region made, therefore the method is greatly improved the reliability of device.
Accompanying drawing explanation
With reference to appended accompanying drawing, more fully to describe embodiments of the invention.But, appended
Accompanying drawing is merely to illustrate and illustrates, is not intended that limitation of the scope of the invention.
Fig. 1 is the structural representation of the shallow trench formed after photoengraving in the inventive method；
Fig. 2 is the shallow trench being partially filled with that the inventive method medium high density plasma completes
Structural representation；
Fig. 3 is the structural representation of the shallow trench formed after thermal oxide in the inventive method；
Fig. 4 is the structural representation of the shallow trench after final step has deposited in the inventive method
Figure.
Detailed description of the invention
The present invention provides a kind of shallow groove filling method, can be applicable to technology node be 45/40nm,
32/28nm, less than or equal in the technique of 22nm；Can be applicable in techniques below platform: Logic,
Memory、RF、HV。
As Figure 1-4, a kind of shallow groove filling method, wherein, described method includes:
Step S1, offer one are formed with the semiconductor structure of shallow trench；
Step S2, employing high density plasma CVD technique are at described shallow trench
Middle filling silica membrane, and make the top of described silica membrane be in described quasiconductor
The top distance below of structure；
Step S3, in described groove expose surface carry out thermal oxidation technology, with continues give birth to
Long certain thickness silicon dioxide；
Step S4, carry out annealing process；
Step S5, using plasma chemical vapor deposition method continue to prepare silicon dioxide,
To fill the remainder in shallow trench.
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as this
The restriction of invention.
In the present embodiment, first provide the Semiconductor substrate 1 of silicon materials, described half
The upper deposition-etch barrier layer 2 of conductor substrate 1 layer, utilizes photo-etching processes to be sequentially etched described quarter
Erosion barrier layer 2 and Semiconductor substrate 1, to described etching barrier layer 2 and described Semiconductor substrate
After 1 performs etching, also include cleaning, to form described shallow trench 3.
It is subsequently filled silica membrane 4, with highly dense in the most etched shallow trench 3 completed
The mode of degree plasma activated chemical vapour deposition fills silica membrane 4, wherein combines deposition
With two key steps of etching, deposition carries out the filling of silicon dioxide to shallow trench 3, and etching will
" the highlighting " at shallow trench top eliminates, and the deposition for next round that eliminates of " highlighting " provides
The filling of broad air inlet, beneficially next round, the deposition so approximately passing through 4-8 wheel adds
Etching just can obtain void-free filling.When silica membrane 4 deposits to distance shallow trench
During 3 distance from tops about 300-1000 Ethylmercurichlorendimide, stop filling.
Shallow trench 3 top is not filled by part again and carries out thermal oxide, be at high temperature passed through oxygen pair
The surface exposed in groove carries out thermal oxide, can grow the silicon dioxide layer 5 of 30-100 Ethylmercurichlorendimide,
Then make annealing treatment.
After annealing, using plasma chemical gaseous phase has deposited filling out shallow trench 3
Fill, and be completely covered on the upper surface of Semiconductor substrate 1.
In sum, use high-density plasma when filling, and have dry etch step,
Monocrystal silicon in shallow trench can be bombarded by high-octane plasma, causes damage, but draws
Enter thermal oxidation mode, then carry out plasma activated chemical vapour deposition and complete shallow trench is filled out
Fill, owing to thermal oxide can consume the monocrystal silicon come out, therefore, by the table of plasma damage
Face monocrystal silicon can be thermally oxidized thus repair the damage at shallow trench top, and the top of shallow trench is
Being the region of device work, therefore, the reparation of damage can be greatly improved device reliability.
For a person skilled in the art, after reading described above, various changes and modifications
Will be apparent to undoubtedly.Therefore, appending claims should be regarded as and contains the true of the present invention
Sincere figure and whole variations and modifications of scope.In Claims scope any and all etc.
The scope of valency and content, be all considered as still belonging to the intent and scope of the invention.
Claims (6)
1. a shallow groove filling method, it is characterised in that described method includes:
Step S1, offer one are formed with the semiconductor structure of shallow trench；
Step S2, employing high density plasma CVD technique are at described shallow trench
Middle filling silica membrane, and make the top of described silica membrane be in described quasiconductor
The top distance below of structure；
Wherein, step S2 is to combine deposition and two steps of etching, and shallow trench is carried out by deposition
The filling of silicon dioxide, etches and " the highlighting " at shallow trench top is eliminated, disappearing of " highlighting "
Except the deposition for next round provides the filling of broad air inlet, beneficially next round；
Step S3, in described groove expose surface carry out thermal oxidation technology, with continues give birth to
Long certain thickness silicon dioxide；
Step S4, carry out annealing process；
Step S5, using plasma chemical vapor deposition method continue to prepare silicon dioxide,
To fill the remainder in shallow trench.
2. a kind of shallow groove filling method as claimed in claim 1, it is characterised in that institute
State semiconductor structure and include a substrate and the etching barrier layer being positioned on described substrate, and by depending on
Secondary described etching barrier layer and described substrate are performed etching, form described shallow trench.
3. a kind of shallow groove filling method as claimed in claim 2, it is characterised in that right
After described etching barrier layer and described substrate perform etching, also include cleaning, to be formed
Described shallow trench.
4. a kind of shallow groove filling method as claimed in claim 1, it is characterised in that institute
The top stating silica membrane is at least 300 Ethylmercurichlorendimides below described semiconductor structure top
Place.
5. a kind of shallow groove filling method as claimed in claim 1, it is characterised in that step
In rapid S3, the thickness of described silicon dioxide is that 30 Ethylmercurichlorendimides are to 100 Ethylmercurichlorendimides.
6. a kind of shallow groove filling method as claimed in claim 1, it is characterised in that adopt
The plasma activated chemical vapour deposition technique in step S5 and step is carried out with same process equipment
High density plasma CVD technique in S2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410106819.6A CN103871953B (en) | 2014-03-20 | 2014-03-20 | A kind of shallow groove filling method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410106819.6A CN103871953B (en) | 2014-03-20 | 2014-03-20 | A kind of shallow groove filling method |
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| Publication Number | Publication Date |
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| CN103871953A CN103871953A (en) | 2014-06-18 |
| CN103871953B true CN103871953B (en) | 2017-01-04 |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113725147B (en) * | 2021-09-02 | 2023-10-10 | 长鑫存储技术有限公司 | Semiconductor structure manufacturing method and semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1442895A (en) * | 2002-03-06 | 2003-09-17 | 矽统科技股份有限公司 | Mathod of forming shallow slot isolating ragion |
| CN1979797A (en) * | 2005-12-05 | 2007-06-13 | 中芯国际集成电路制造(上海)有限公司 | STI channel filling method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100346842B1 (en) * | 2000-12-01 | 2002-08-03 | 삼성전자 주식회사 | Semiconductor device having shallow trench isolation structure and method for manufacturing the same |
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2014
- 2014-03-20 CN CN201410106819.6A patent/CN103871953B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1442895A (en) * | 2002-03-06 | 2003-09-17 | 矽统科技股份有限公司 | Mathod of forming shallow slot isolating ragion |
| CN1979797A (en) * | 2005-12-05 | 2007-06-13 | 中芯国际集成电路制造(上海)有限公司 | STI channel filling method |
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| Publication number | Publication date |
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| CN103871953A (en) | 2014-06-18 |
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