CN104916535B - A kind of method of induced with laser thermally grown oxide silicon - Google Patents
A kind of method of induced with laser thermally grown oxide silicon Download PDFInfo
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- CN104916535B CN104916535B CN201410093052.8A CN201410093052A CN104916535B CN 104916535 B CN104916535 B CN 104916535B CN 201410093052 A CN201410093052 A CN 201410093052A CN 104916535 B CN104916535 B CN 104916535B
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Abstract
The present invention provides a kind of method of induced with laser thermally grown oxide silicon, and methods described includes:The step of silica is prepared using laser irradiation amorphous silicon.Methods described is applied to wafer behind sensitive technologies processing procedure.The wafer behind sensitive technologies processing procedure includes:Device wafers and support wafer are provided;Plasma deposition silicon oxide layer and amorphous si-layer are sequentially formed on the device wafers surface;Chemical-mechanical planarization step is carried out, to remove part amorphous silicon layer;Perform laser irradiation step;Perform thermal bonding step.Induced with laser mode of oxidizing thermally grown silicon oxide layer is used on BSI device wafers bonding faces according to the manufacturing process of the present invention, can effectively avoid the generation of device wafers fire damage defect, the compactness height of oxide is generated, bond strength can be improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of method of induced with laser thermally grown oxide silicon.
Background technology
Thermal bonding (Fusion Bonding) technology is widely used in complementary metal-oxide CIS (CMOS
Image sensor, CIS) and MEMS (Micro-Electro-Mechanical Systems, MEMS) 3D encapsulation
In processing procedure, its general principle is that the interconnection of two wafers is realized by Si-O keys.Due to the compactness ratio of hot oxide growth silica
The compactness of plasma enhancing tetraethyl orthosilicate (PE-TEOS) layer is higher, Si-O keys it is more, therefore bond strength is more
Greatly, it is more suitable for the medium of bonding.
For wafer behind sensitive technologies (Backside Illumination, BSI), support wafer is naked silicon systems,
Medium uses hot oxide growth silica, and its bond strength is good;And device wafers due to be use CMOS-PST processing procedures, therefore
The temperature that can at most bear is 400 DEG C, thus device wafers commonly using PE-TEOS as be bonded medium, bond strength compared with
Difference.
Fig. 1 shows the processing step of prior art BSI thermal bondings, is specially:In a step 101, there is provided device wafers
With support wafer, alignment mark is formed in device wafers.The bonding face of the support wafer is already formed with thermal oxide growth
Silicon oxide layer.Alignment mark is formed in device wafers, thinks and wafer (wafer rear) is supported in subsequent wafer bonding technology
It is aligned with device wafers (wafer frontside).In a step 102, PE-TEOS layers are deposited on device wafers surface.In step
In 103, chemically mechanical polishing planarisation step is performed, to remove part PE-TEOS layers.At step 104, plasma is carried out
Activation step, to improve bond strength.In step 105, device wafers are carried out with deionized water infiltration cleaning, is carried out after cleaning
It is spin-dried for.In step 106, thermal bonding technique is carried out, by the device wafers and the support wafer interconnection.As shown in Figure 2 A
For device wafers and support wafer bonding schematic diagram, the surface of device wafers 200, which deposits, as seen from the figure PE-TEOS layers 201,
Support wafer 202 bonding face deposition has thermally grown silicon oxide layer 203, and device wafers (front) are mutually tied with support wafer (back side)
Close, realized and interconnected by Si-O keys.It is the enlarged diagram of bonded interface as shown in Figure 2 B.So what is faced at present is how to carry
The quality of high device wafers bonding face deposition oxide, the problem of further to improve bond strength.
Therefore, it is badly in need of a kind of new manufacture method, to overcome deficiency of the prior art.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to solve problems of the prior art, the present invention proposes a kind of side of induced with laser thermally grown oxide silicon
Method, comprise the following steps:The step of silica is prepared using laser irradiation amorphous silicon.
Further, methods described is applied to wafer behind sensitive technologies processing procedure.
Further, the wafer behind sensitive technologies processing procedure includes:Device wafers and support wafer are provided;In the device
Plasma deposition silicon oxide layer and amorphous si-layer are sequentially formed on crystal column surface;Chemical-mechanical planarization step is carried out, to go
Except part amorphous silicon layer;Perform laser irradiation step;Perform thermal bonding step.
Further, the atmosphere of the laser irradiation is air or oxygen atmosphere, and wave-length coverage is 200~350nm, and energy is close
Degree is more than 2J/cm2。
Further, the plasma deposition silicon oxide layer thickness is
Further, after performing the chemical-mechanical planarization step, the amorphous si-layer thickness is
Further, the thermal bonding technological parameter is:The bonding pressure of application is 1~10N, and bonding time is 10~60s.
Further, also include performing plasma activation and wet-cleaning and rotation successively before the thermal bonding technique is performed
Dry step.
Further, the plasma activating step uses nitrogen as gas source, and power is 100~600W, and soak time is
10~60s.
Further, the wet clean step using deionized water clean, the spinning step rotating speed be 1000~
3500rpm, time are 1~5min.
Further, also include forming alignment in the device wafers before the plasma deposition silicon oxide layer is formed
The step of mark.
It is to sum up shown, induced with laser oxidation side is used on BSI device wafers bonding faces according to the manufacturing process of the present invention
Formula thermally grown silicon oxide layer, the generation of device wafers fire damage defect can be effectively avoided, generate the compactness height of oxide, can carry
High bond strength.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing:
Fig. 1 is the flow chart for the step of prior art BSI thermal bonding techniques are implemented successively;
Fig. 2A is prior art BSI thermal bonding step schematic diagrams;
Fig. 2 B are the close-up schematic view of bonded interface;
Fig. 3 A-3C are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present
Schematic cross sectional view;
Fig. 4 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Manufacturing process of the invention by using induced with laser mode of oxidizing thermally grown oxide silicon on BSI device wafers bonding faces
Layer.Obviously, execution of the invention is not limited to the specific details that the technical staff of semiconductor applications is familiar with.The present invention compared with
Good embodiment is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
It should be appreciated that when using term "comprising" and/or " comprising " in this manual, it is indicated described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
[exemplary embodiment]
The present invention is described in more detail below in conjunction with diagrammatic cross-section, wherein denoting the preferred reality of the present invention
Apply example, it should be appreciated that those skilled in the art can modify invention described herein, and still realize having for the present invention
Sharp effect.
First, there is provided device wafers and support wafer, alignment mark is formed in device wafers.
The device wafers are made up of Semiconductor substrate and device, and the material of Semiconductor substrate is monocrystalline silicon, can also
It is other substrates such as silicon or stress silicon on insulator.The device is by several Metal-oxide-semicondutor field-effects
Other devices such as transistor (MOSFETs) and electric capacity, resistance interconnect the integrated circuit or other to be formed by alloy
Common semiconductor devices in integrated circuit fields, such as bipolar device or power device etc..The support wafer is silicon wafer
Circle, plays a supportive role.
Alignment mark is formed in device wafers, with ensure in subsequent wafer bonding technology support wafer (wafer rear) and
Device wafers (wafer frontside) carry out accurate alignment.The formation technology of alignment mark is prior art, be will not be described here.
Then, as shown in Figure 3A, plasma deposition silicon oxide layer 301 and nothing are sequentially formed on the surface of device wafers 300
Amorphous silicon layer 302.
The material of plasma deposition silicon oxide layer 301 is to be prepared by plasma enhanced chemical vapor deposition processes
Silicon oxide layer (HDP) prepared by TEOS (PE-TEOS) or high-density plasma enhanced chemical vapor deposition processes, preferably
For PE-TEOS.Because the plasma enhanced deposition technique for depositing PE-TEOS/HDP silicon oxide layers is commonly used in the prior art
Technique, it will not be repeated here.The thickness of the plasma deposition silicon oxide layer 301 isPreferably
The formation process of the amorphous si-layer 302 can use any prior art well known to those skilled in the art,
Compare preferably chemical vapour deposition technique, such as low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical gas
Phase depositing operation.
Then, as shown in Figure 3 B, chemically mechanical polishing planarization (CMP) step is performed, to remove part amorphous silicon layer.
The chemically mechanical polishing planarisation step uses prior art, will not be repeated here.After chemically mechanical polishing planarization, remain
Remaining part divides the thickness of amorphous si-layer 302 to be
Then, as shown in Figure 3 C, laser irradiation step is performed, amorphous si-layer after planarization is oxidized to silicon oxide layer
303。
The induced with laser step of thermal oxidation, it is that amorphous si-layer is positioned in air or oxygen atmosphere, using sharp
Light irradiation heats amorphous si-layer, and amorphous si-layer absorbs oxygen during fusing, is oxidized to silica, is regenerating afterwards
Long zone freezing, while the top of pair PE-TEOS layers contacted with amorphous si-layer is made annealing treatment, therefore PE- can be made
The top of TEOS layers is more densified.The laser wavelength range is 200~350nm, and energy density is more than 2J/cm2。
Then, plasma activating step is carried out, to improve bond strength.
Device wafers surface is activated with plasma, bond strength can be greatly improved, produce few cavity
Or space, obtain a preferable bonding effect.As an example, using N2As source gas to generation silicon oxide layer surface
Carry out plasma-activated, power is 100~600W, and soak time is 10~60s.
Then, device wafers are carried out with deionized water infiltration cleaning, is spin-dried for after cleaning.Be bonded two wafers it
Before, the wafer for being intended to bonding carries out wet clean process, makes particle, impurity, chemical pollutant of wafer surface attachment etc.
Deng can as far as possible remove, to obtain preferably pure bonding interface, meet rigors of the bonding conditions to surface.The cleaning
Step carries out infiltration cleaning using deionized water (DI water) to device wafers, is then spin-dried for.As an example, institute
Spinning step is stated, rotating speed is 1000~3500rpm, and the time is 1~5min.
Then, thermal bonding technique is carried out, by device wafers and support wafer interconnection.
The support wafer is before thermal bonding technique is carried out, on surface formed with thermal oxide silicon oxide layer.And in hot oxygen
Before oxide/silica layer is formed, formed with alignment mark on support wafer, to ensure device wafers and support during thermal bonding
The alignment precision of wafer.And plasma activating step and wet-cleaning are carried out successively to thermal oxide silicon oxide layer and have been spin-dried for
Step.Above step is prior art, and therefore not to repeat here.
Thermal bonding technique is performed, by the device wafers and the support wafer interconnection.As an example, the heat
In bonding process, the bonding pressure of application is 1~10N, and bonding time is 10~60s.
Reference picture 4, the flow chart for the step of method according to an exemplary embodiment of the present invention is implemented successively is illustrated therein is,
For schematically illustrating the flow of whole manufacturing process.
In step 401, there is provided device wafers and support wafer, alignment mark is formed in device wafers.
In step 402, plasma deposition silicon oxide layer and amorphous si-layer are sequentially formed on device wafers surface.
In step 403, chemically mechanical polishing planarisation step is performed.
In step 404, laser irradiation step is performed.
In step 405, plasma activating step is carried out.
In a step 406, device wafers are carried out with deionized water infiltration cleaning, is spin-dried for after cleaning.
In step 407, thermal bonding technique is carried out.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of method of induced with laser thermally grown oxide silicon suitable for wafer behind sensitive technologies processing procedure, including:
Device wafers and support wafer are provided;
Plasma deposition silicon oxide layer and amorphous si-layer are sequentially formed on the device wafers surface;
Chemical-mechanical planarization step is carried out, to remove part amorphous silicon layer;
The step of amorphous silicon prepares silica is irradiated using laser, wherein, the nothing is heated using laser irradiation
The top of pair plasma deposition silicon oxide layer contacted with the amorphous si-layer is annealed while amorphous silicon layer,
So that the top of the plasma deposition silicon oxide layer is more densified;
Perform thermal bonding step.
2. the method as described in claim 1, it is characterised in that the atmosphere of laser irradiation is air or oxygen atmosphere, ripple
Long scope is 200~350nm, and energy density is more than 2J/cm2。
3. the method as described in claim 1, it is characterised in that the plasma deposition silicon oxide layer thickness is
4. the method as described in claim 1, it is characterised in that after performing the chemical-mechanical planarization step, the nothing is determined
Shape silicon layer thickness is
5. the method as described in claim 1, it is characterised in that the thermal bonding technological parameter is:The bonding pressure of application is 1
~10N, bonding time are 10~60s.
6. the method as described in claim 1, it is characterised in that also include performing successively before the thermal bonding technique is performed
Plasma activation and wet-cleaning and the step of be spin-dried for.
7. method as claimed in claim 6, it is characterised in that the plasma activating step uses nitrogen as gas source, work(
Rate is 100~600W, and soak time is 10~60s.
8. method as claimed in claim 6, it is characterised in that the wet clean step is cleaned using deionized water, described
Spinning step rotating speed is 1000~3500rpm, and the time is 1~5min.
9. the method as described in claim 1, it is characterised in that also include before the plasma deposition silicon oxide layer is formed
In the device wafers formed alignment mark the step of.
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CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子(上海)有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
CN108461512A (en) * | 2018-02-02 | 2018-08-28 | 豪威科技(上海)有限公司 | wafer bonding structure and wafer bonding method |
CN110314896A (en) * | 2019-03-21 | 2019-10-11 | 清华大学 | A kind of semiconductor substrate materials polishing method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101764052A (en) * | 2008-12-22 | 2010-06-30 | 硅绝缘体技术有限公司 | Method for bonding two substrates |
CN103050480A (en) * | 2012-08-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Technical method for imaging rear side of silicon wafer |
CN103065945A (en) * | 2013-01-14 | 2013-04-24 | 陆伟 | Image sensor wafer bonding method |
CN103557827A (en) * | 2013-10-21 | 2014-02-05 | 南通大学 | P-type silicon solar cell PN junction depth measuring method based on laser oxidation style |
-
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- 2014-03-13 CN CN201410093052.8A patent/CN104916535B/en active Active
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101764052A (en) * | 2008-12-22 | 2010-06-30 | 硅绝缘体技术有限公司 | Method for bonding two substrates |
CN103050480A (en) * | 2012-08-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Technical method for imaging rear side of silicon wafer |
CN103065945A (en) * | 2013-01-14 | 2013-04-24 | 陆伟 | Image sensor wafer bonding method |
CN103557827A (en) * | 2013-10-21 | 2014-02-05 | 南通大学 | P-type silicon solar cell PN junction depth measuring method based on laser oxidation style |
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