CN105183430B

CN105183430B - A kind of timer IP kernel being connected with 8-bit microprocessor application system and its realize the time-controlled method of timer

Info

Publication number: CN105183430B
Application number: CN201510376687.3A
Authority: CN
Inventors: 余玲; 蔡启仲; 谢友慧; 戴永涛
Original assignee: Guangxi University of Science and Technology; Lushan College of Guangxi University of Science and Technology
Current assignee: Guangxi University of Science and Technology; Lushan College of Guangxi University of Science and Technology
Priority date: 2015-06-30
Filing date: 2015-06-30
Publication date: 2018-01-19
Anticipated expiration: 2035-06-30
Also published as: CN105183430A

Abstract

A kind of timer IP kernel being connected with 8-bit microprocessor application system, including data input output decompose storage control module, the frequency divider of pulse 12, Timing Processing control module, timer overflow indicator control module and input gate selection control module with command word；The present invention applies FPGA design timer IP kernel Hard link control circuit, timer IP kernel has 14 16 bit timing devices, wherein 12 can make up 6 32 bit timing devices, a command word sets mode of operation, timing base clock division multiple selects, another command word control working condition；The present invention is not take up 8-bit microprocessor program execution time in addition to 8-bit microprocessor carries out function and state setting, timing parameters transmission to timer, reads the operation of timing currency；Each 16/32 bit timing utensil has automatic reloading timing parameters function, improves timing accuracy；It disclosure satisfy that large number of timer timing and the demand of timing control system.

Description

A kind of timer IP kernel being connected with 8-bit microprocessor application system and its realization are fixed When the time-controlled method of device

Technical field

The present invention relates to a kind of timer IP kernel being connected with 8-bit microprocessor application system and its realize timer timing The method of control, more particularly to a kind of the characteristics of being based on FPGA parallel processings, the energy formed using FPGA design hardware circuitry Enough timer IP kernels being connected with 8-bit microprocessor application system and its for realizing the time-controlled method of timer.

Background technology

In extensive Time sequence control or other 8-bit microprocessor application systems needed using numerous timers, Substantial amounts of timer will be used, extension timer number there are three kinds of implementations：In first way application microprocessor The timing of one timer is programmed using timer interrupt mode as fiducial time, sets timing times number variable, this is regularly Times number variable is also the marking variable for extending timer, and programmed method mainly has 2 kinds, and the 1st kind of method is to perform a secondary standard to determine When device interrupt a service function timing times number variable and add 1, and compared with the benchmark timing multiple value of setting, if timing times number variable The benchmark timing multiple value of setting is reached, to timing times number variable clear 0, has then performed what the extension timer timing arrived Program；Or the marking variable of an extension timer is specially set, when timing times number variable has reached the benchmark timing times of setting During numerical value, to timing times number variable clear 0, the marking variable of 1 timer is put, the mark of the timer is judged in the program of principal function Know whether variable is " 1 ", if it is, the marking variable of clear 0 timer, performs once the extension timer timing and arrive Processing function；The second way is that microprocessor is connected with timer extended chip, and timer chip mainly has at present 82C54,3 16 bit timing devices can be extended；

Following weak point be present in two kinds of implementations of the above：

1. the Interruption method of application benchmark timer, CPU are responded and are exited benchmark timer interrupt service program and account for With CPU run times；The timing base time is smaller, such as 1ms, and the timer that timer system needs extend is more, will take CPU run times are longer, and the execution speed to other program modules produces serious influence, and timing accuracy is not high；

2. the second way extends out Special timer chip using microprocessor, required timer is more, extends out special Timer chip is more, and the circuit scale of 8-bit microprocessor application system is bigger；

The third mode is to be realized using non-programmable hardware timing, each of which timer with independent hardware circuit； Timing function is realized in this way, and required timer is more, and circuit scale is bigger, and maintenance workload is big.

The content of the invention

It is an object of the invention to fully apply FPGA parallel processing function, there is provided a kind of micro- based on FPGA and 8 Processor application system connection timer IP kernel and its for realizing the time-controlled method of timer, in the timer IP kernel There are 14 16 bit timing devices in portion, can also be set to 6 32 bit timing devices, each 16 bit timing using 12 16 bit timing devices Device or 32 bit timing devices output spill over, can program the work for setting gate-control signal control timer, the work of timer Pattern, selects the frequency dividing multiple of four kinds of timer counters, and the timer IP kernel has timing accuracy height, only needed by initialization volume Two orders of journey set the working operating mode of each timer, and timing process is not take up the execution of 8-bit microprocessor program Time, it can realize to the quantity up to timing of 14 16 bit timing devices or 2 16 bit timing devices and 6 32 bit timing devices with determining When the advantages that controlling, to overcome the shortcomings of that existing timing mode is realized present in technology.

In order to solve the above technical problems, the present invention adopts the technical scheme that：It is a kind of to connect with 8-bit microprocessor application system The timer IP kernel connect, it is characterised in that：The timer IP kernel includes data input output and decomposes storage control mould with command word Block, the frequency divider of pulse 12, Timing Processing control module, timer overflow indicator control module, input gate selection control module；

The data input output is decomposed at storage control module and 8-bit microprocessor application system, timing with command word Reason control module, timer overflow indicator control module and input gate selection control module and connected；

The frequency divider of pulse 12 is also connected with 8-bit microprocessor application system and Timing Processing control module；

The Timing Processing control module also with 8-bit microprocessor application system, timer overflow indicator control module and Input gate selection control module connection；

It is low level bar that the data input output decomposes storage control module in the chip selection signal of input with command word The timer given under part if write signal is effective according to 8-bit microprocessor application system or the address of timer command word, The mode of operation frequency dividing multiple coded command word of timer operation is obtained, STATUS control commands word, 16 bit timing devices or 32 are fixed When device timing parameters, and according to timing parameters, timer numbering, mode of operation divide times number encoder and state control give respectively To store and export, also output is write mode of operation frequency dividing multiple coded command word signal, write state control command word signal and write Timer parameter signal；If read signal effectively transmits the real-time timing value of timer to 8-bit microprocessor application system；

The frequency divider of pulse 12 is divided to the clock pulses of 8-bit microprocessor application system, and it is exported as fixed When processing and control module timer timing control operation reference clock pulse；

The Timing Processing control module is in the presence of mode of operation frequency dividing multiple coded command word signal is write, according to fixed When device numbering store the timer mode of operation, reference clock divide multiple encoded radio；Believe in write state control command word In the presence of number, the state control signal for storing the timer is numbered according to timer；In the effect of write timing device parameter signal Under, the timing parameters for storing the timer are numbered according to timer；It is defeated outside the Timing Processing control module timer IP kernel The clock pulses CLK II that enters controls the operation of Timing Processing control module, during the benchmark exported according to the frequency divider of pulse 12 Clocked pulse period completes a Timing Processing of all timers, includes the state control process of each timer, mode of operation Judgement processing, according to each 16/32 bit timing device set reference clock multiple value to each 16/32 bit timing device Real-time timing parameter value carries out plus 1 operation, and when producing spilling, timing parameters are reloaded automatically to real-time timing parameter value, and defeated Go out overflow indicator signal；It is low level in the chip selection signal that data input output decomposes storage control module input with command word Under the conditions of, if read signal is effective, the address of the timer given according to 8-bit microprocessor application system, it is fixed directly to read this When device real-time timing parameter value through data input output with command word decompose storage control module be transferred to 8-bit microprocessor should With the data/address bus of system, the real-time timing parameters of 16 bit timing devices need timesharing to be read twice, the reality of 32 bit timing devices When timing parameters need timesharing to be read for four times；Under the reset signal effect of 8-bit microprocessor application system output, stop The fixed cycle operator of all timers；

The timer overflow indicator control module exports the high level of 16/32 bit timing devices effectively spill over； When the spill over of 16 bit timing devices of Timing Processing control module output is transformed to high level by low level, the timer is stored Overflow indicator is high level；If the timer overflow indicator is high level, clear overflow indicator is converted to low level by high level, It is low level to store the timer overflow indicator；In the presence of mode of operation frequency dividing multiple coded command word signal is write, timing Device overflow indicator control module stores the information of 32 bit timing device mode of operations according to register number, blocks the 32 bit timing device The flooding information of low 16 remains low level；

The input gate selects control module in the case where writing mode of operation frequency dividing multiple coded command word signal function, according to Timer numbering stores the mode of operation of the timer, is required according to gate control function determined by the runs pattern and defeated The gate level entered, the gate-control signal of control input gate selection control module output.

Its further technical scheme is：The data input output decomposes storage control module with command word includes 8 pairs To data strobe triple gate group, read-write control module, timing parameter register, timer numbered register, mode of operation Divide multiple code registers, mode control register；

8 bi-directional data strobe triple gates group controls mould with 8-bit microprocessor application system, read-write respectively Block, timing parameter register, timer numbered register, mode of operation frequency dividing multiple code registers, mode control register Connected with Timing Processing control module；

The read-write control module is also numbered with 8-bit microprocessor application system, timing parameter register, timer Register, mode of operation frequency dividing multiple code registers, mode control register, Timing Processing control module, timer overflow Mark control module gates selection control module with input and connected；

The timing parameter register is also connected with Timing Processing control module；

The timer numbered register also overflows with 8-bit microprocessor application system, Timing Processing control module, timer Go out to indicate that control module gates selection control module with input and connected；

The mode of operation frequency dividing multiple code registers also control mould with 8-bit microprocessor application system, Timing Processing Block, timer overflow indicator control module and input gate selection control module and connected；

The mode control register also overflows with 8-bit microprocessor application system, Timing Processing control module and timer Go out to indicate that control module connects；

The data input output decomposes the read-write control module of storage control module in chip selection signal with command word Under the conditions of low level, if write signal is effective, 8 bi-directional data strobe triple gate group write signals are sent, gate 8 micro- places Manage the data input of device application system data/address bus；Write timing device numbering signal is produced, and judges the address value of input, if The address value of timer parameter, the address value is write into timer numbered register, write timing device parameter signal is produced, by data The data write-in timing parameter register of bus；If timer order word address, by the 2nd ~ the 5th digit of data/address bus According to write-in timer numbered register, order word address is 0EH or 0FH, and it is 0 to set the 3rd bit timing device number value S3, is otherwise set It is set to 1；If command word least-significant byte address, then command word is mode of operation frequency dividing multiple coded command word, and Working mould is write in generation Formula divides multiple coded command word signal, by the 0th of data/address bus, the 1st, the 6th and the 7th write-in mode of operation frequency dividing Multiple code registers；If command word most-significant byte address, then command word is STATUS control commands word, produces write state control Command word signal, by the 0th of data/address bus, the 1st and the 7th write state control register；If read signal is effective, hair Go out 8 bi-directional data strobe triple gate group read signals, output data inside the timer IP kernel of Timing Processing control module is total Data/address bus of the data transfer of line to 8-bit microprocessor application system.

Its further technical scheme is：The Timing Processing control module includes timer timing control operation module, Address strobe control I, 8 Bit Time Parameters dual-ported memories, address strobe control II, 8 bit timing real-time parameter dual-ports are deposited Reservoir, address strobe control III, 4 mode of operations divide times number encoder dual-ported memory, address strobe control IV, 3 shapes State controls dual-ported memory；

The timer timing control operation module respectively with the frequency divider of pulse 12, timer overflow indicator control module, Timer overflow indicator control module, address strobe control I, 8 Bit Time Parameters dual-ported memories, address strobe control II, 8 Bit timing real-time parameter dual-ported memory, address strobe control III, 4 mode of operation frequency dividing times number encoder dual-port storage Device, address strobe control the Timing Processing control of IV, 3 state control dual-ported memory and timer device IP kernel outside input Operation clock pulses CLK II is connected；

The address strobe control I also decomposes storage control module with command word with data input output and 8 bit timings are joined Number dual-ported memory connection；

The 8 Bit Time Parameters dual-ported memory also with data input output with command word decompose storage control module and 8 bit timing real-time parameter dual-ported memories connect；

The address strobe control II is also decomposed with command word and deposited with 8-bit microprocessor application system, data input output Storage control module connects with 8 bit timing real-time parameter dual-ported memories；

The 8 bit timing real-time parameter dual-ported memory also decomposes storage control mould with data input output and command word Block connects；

The address strobe control III also decomposes storage control module and 4 Working moulds with data input output with command word Formula frequency dividing times number encoder dual-ported memory connection；

4 mode of operations frequency dividing times number encoder dual-ported memory also exports to decompose with command word with data input to be deposited Store up control module connection；

The address strobe control IV also decomposes storage control module and 3 state controls with data input output with command word Dual-ported memory connection processed；

3 states control dual-ported memory also decomposes storage control module, 8 with data input output with command word The reset signal connection of bit microprocessor application system；If the reset signal of input is effective reset signal, 3 shapes are resetted State controls dual-ported memory, stops the fixed cycle operator of all timers.

Further technical scheme is for it：The timer overflow indicator control module includes NOT gate, M0 mode of operations position Register group, overflow quenching pulse controller, NAND gate I, d type flip flop I, with door I, NAND gate II, d type flip flop II, NAND gate III, d type flip flop III, with door II, NAND gate IV, d type flip flop IV, NAND gate V, d type flip flop V, with door III, NAND gate VI, D is touched Send out device VI, NAND gate VII, d type flip flop VII, NAND gate VIII, d type flip flop VIII, with door IV, NAND gate Ⅸ, d type flip flop Ⅸ, NAND gate Ⅹ, d type flip flop Ⅹ, with door V, NAND gate Ⅺ, d type flip flop Ⅺ, NAND gate Ⅻ, d type flip flop Ⅻ, with door VI, NAND gate Ⅹ III, D Trigger Ⅹ III, NAND gate Ⅹ IV, d type flip flop Ⅹ IV；

The state control that the input of the NOT gate decomposes storage control module with data input output with command word is deposited The M0 output ends connection of device, output end are connected with an input of M0 mode of operation bit register groups；

The other three input of the M0 mode of operation bit register groups reset signal with 8-bit microprocessor application system respectively The mode of operation of writing for the read-write control module that output end, data input output decompose storage control module with command word divides Multiple coded command word signal output part connects with the timer numbering output end of timer numbered register, output end respectively with Door I, it is connected with door II, with door III, with door IV, with door V, with an input of door VI；

Three inputs for overflowing quenching pulse controller decompose storage control with data input output and command word respectively Write state control command word signal output part, the clear overflow indicator of mode control register of the read-write control module of module Output end connects with the timer numbering output end of timer numbered register, output end difference NAND gate I, NAND gate II, with NOT gate III, NAND gate IV, NAND gate V, NAND gate VI, NAND gate VII, NAND gate VIII, NAND gate Ⅸ, NAND gate Ⅹ, NAND gate Ⅺth, the input connection of NAND gate Ⅻ, NAND gate Ⅹ III, NAND gate Ⅹ IV；Output end also with d type flip flop I, d type flip flop IIth, d type flip flop III, d type flip flop IV, d type flip flop V, d type flip flop VI, d type flip flop VII, d type flip flop VIII, d type flip flop Ⅸ, D are touched Hair device Ⅹ, d type flip flop Ⅺ, d type flip flop Ⅻ, d type flip flop Ⅹ III connect with the data input pin of d type flip flop Ⅹ IV；

Another input of NAND gate I is connected with the overflow indicator output end of Timing Processing control module, output end and D The clock signal input terminal connection of trigger I；

The data output end of d type flip flop I and it is connected with another input of door I；

Connect with the output end of door I as the overflow indicator output signal of 16 bit timing devices 0 with 8-bit microprocessor application system Connect；

Another input of NAND gate II is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop II；

The data output end of d type flip flop II is defeated as the overflow indicator output signal of the bit timing device 0 of 16 bit timing device 1/32 Go out end to be connected with 8-bit microprocessor application system；

Another input of NAND gate III is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop III；

The data output end of d type flip flop III and it is connected with another input of door II；

With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door II as 16 bit timing devices 2 Connection；

Another input of NAND gate IV is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop IV；

The data output end of d type flip flop IV is defeated as the overflow indicator output signal of the bit timing device 1 of 16 bit timing device 3/32 Go out end to be connected with 8-bit microprocessor application system；

Another input of NAND gate V is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop V；

The data output end of d type flip flop V and it is connected with another input of door III；

With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door III as 16 bit timing devices 4 Connection；

Another input of NAND gate VI is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop VI；

The data output end of d type flip flop VI is defeated as the overflow indicator output signal of the bit timing device 2 of 16 bit timing device 5/32 Go out end to be connected with 8-bit microprocessor application system；

Another input of NAND gate VII is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop VII；

Overflow indicator output signal output end and 8 micro- places of the data output end of d type flip flop VII as 16 bit timing devices 6 Manage the connection of device application system；

Another input of NAND gate VIII is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop VIII；

The data output end of d type flip flop VIII and it is connected with another input of door IV；

With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door IV as 16 bit timing devices 7 Connection；

Another input of NAND gate Ⅸ is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop Ⅸ；

The data output end of d type flip flop Ⅸ is defeated as the overflow indicator output signal of the bit timing device 3 of 16 bit timing device 8/32 Go out end to be connected with 8-bit microprocessor application system；

Another input of NAND gate Ⅹ is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop Ⅹ；

The data output end of d type flip flop Ⅹ and it is connected with another input of door V；

With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door V as 16 bit timing devices 9 Connection；

Another input of NAND gate Ⅺ is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop Ⅺ；

The data output end of d type flip flop Ⅺ is defeated as the overflow indicator output signal of the bit timing device 4 of 16 bit timing device 10/32 Go out end to be connected with 8-bit microprocessor application system；

Another input of NAND gate Ⅻ is connected with the overflow indicator output end of Timing Processing control module, output end with The clock signal input terminal connection of d type flip flop Ⅻ；

The data output end of d type flip flop Ⅻ and it is connected with an input of door VI；

With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door VI as 16 bit timing devices 11 Connection；

Another input of NAND gate Ⅹ III is connected with the overflow indicator output end of Timing Processing control module, output end It is connected with the clock signal input terminal of d type flip flop Ⅹ III；

Overflow indicator output signal of the data output end of d type flip flop Ⅹ III as the bit timing device 5 of 16 bit timing device 12/32 Output end is connected with 8-bit microprocessor application system；

Another input of NAND gate Ⅹ IV is connected with the overflow indicator output end of Timing Processing control module, output end It is connected with the clock signal input terminal of d type flip flop Ⅹ IV；

The data output end of d type flip flop Ⅹ IV is micro- as the overflow indicator output signal output end of 16 bit timing device 13 and 8 Processor application system connects.

Related another technical scheme is：A kind of timer IP kernel being connected with 8-bit microprocessor application system is used for real The method of existing timer timing control operation, it is to be connected with the above-mentioned one kind of the present invention with 8-bit microprocessor application system Timer IP kernel realize the method for timer timing control operation；

It is concretely comprised the following steps：

s101：Clear reference clock pulse frequency dividing multiple u storage of array units, counter number value j；

s102：Reference clock pulse trailing edge trigger performs 1 time；

s103：Judge whether timer number value j is equal to or more than 1EH, if j value is equal to or more than 1EH, enter Step s104, otherwise into s105；

s104：Timer number value j=00H, return to step s102 are set；

s105：Judge whether timer number value j is equal to 0EH or 0FH, if j value is equal to 0EH or 0FH, enter Enter step s106, otherwise into step s107；

s106：Timer number value j=10H is set, into step s107；

s107：Judgement opens/stopped whether signal is equal to 0, if open/stopping signal=0, the timer stops timing working, enters Step s108, otherwise into step s111；

s108：Judge whether clear timing currency is equal to 0, if clear timing currency=0, into step s109, otherwise Into step s110；

s109：The value of the timer timing memory cell is removed, into step s110；

s110：Timer number value j adds 2, return to step s103；

s111：The reference clock pulse frequency dividing multiple of the timer adds 1：U (j)=u (j)+1, into step s112；

s112：Judge the runs pattern, if mode of operation M1M0=10,16 bit timing devices are gated, into step s113；If mode of operation M1M0=00,16 bit timing devices of no gate, into step s118；If mode of operation M1M0=01, The 32 bit timing devices without gate, into step s114；If mode of operation M1M0=11,32 bit timing devices of gate are selected, are entered Enter step s115；

s113：Whether the gate-control signal for judging the 16 bit timing device is 0, the return to step if gate-control signal is equal to 0 S110, otherwise into step s118；

s114：Judge whether low 2 of 32 bit timing device numbering j be equal to 00, if equal to 00 enters step s126, Otherwise return to step s110；

s115：Judge whether low 2 of 32 bit timing device numbering j be equal to 00, if equal to 00 enters step s116, Otherwise return to step s110；

s116：Whether the gate-control signal for judging the 32 bit timing device is 0, enters step if gate-control signal is equal to 0 S117, otherwise into step s126；

s117：Timer numbering j adds 4：J=j+4, return to step s103；

s118：Judge the coding of the frequency dividing multiple of the 16 bit timing device, if frequency dividing multiple is encoded to F2F1=00, enter Enter step s122；If frequency dividing multiple is encoded to F2F1=01, into step s119；If frequency dividing multiple is encoded to F2F1=10, then into step s120；If frequency dividing multiple is encoded to F2F1=11, into step s121；

s119：Judge whether the reference clock pulse frequency dividing multiple u (j) of 16 bit timing device value is equal to 10, if u (j)=10, then into step s122, otherwise return to step s110；

s120：Judge whether the reference clock pulse frequency dividing multiple u (j) of 16 bit timing device value is equal to 100, if u (j)=100, then into step s122, otherwise return to step s110；

s121：Judge whether the reference clock pulse frequency dividing multiple u (j) of 16 bit timing device value is equal to 1000, if u (j)=1000, then into step s122, otherwise return to step s110；

s122：The reference clock pulse frequency dividing multiple u (j) of 16 bit timing device value is set to be equal to 0, into step s123；

s123：Read 16 bit timing currencys of the 16 bit timing device and add 1, be as a result stored in the 16 bit timing device 16 Timing currency memory cell, into step s124；

s124：Judge whether the timing value of the 16 bit timing device produces spilling, enter step s125 if spilling is produced, Otherwise return to step s110；

s125：Reload 16 Bit Time Parameters of the 16 bit timing device, return to step s110；

s126：Judge the coding of the frequency dividing multiple of the 32 bit timing device, if frequency dividing multiple is encoded to F2F1=00, enter Enter step s130；If frequency dividing multiple is encoded to F2F1=01, into step s127；If frequency dividing multiple is encoded to F2F1=10, then into step s128；If frequency dividing multiple is encoded to F2F1=10, into step s129；

s127:Judge whether the reference clock pulse frequency dividing multiple u (j) of 32 bit timing device value is equal to 10, if u (j)=10, then into step s130, otherwise return to step s117；

s128:Judge whether the reference clock pulse frequency dividing multiple u (j) of 32 bit timing device value is equal to 100, if u (j)=100, then into step s130, otherwise return to step s117；

s129:Judge whether the reference clock pulse frequency dividing multiple u (j) of 32 bit timing device value is equal to 1000, if U (j)=1000, then into step s130, otherwise return to step s117；

s130:The reference clock pulse frequency dividing multiple u (j) of 32 bit timing device value is set to be equal to 0, into step s131；

s131：Read 32 bit timing currencys of the 32 bit timing device and add 1, be as a result stored in the 32 of the 32 bit timing device Bit timing currency memory cell, into step s132；

s132:Judge whether the timing value of the 32 bit timing device produces spilling, enter step if spilling is produced S133, otherwise return to step s117；

s133：Reload 32 Bit Time Parameters of the 32 bit timing device, return to step s117.

Due to use above structure, a kind of timer IP kernel being connected with 8-bit microprocessor application system of the present invention and It realizes that the method for timer timing control operation has the advantages that：

1. it is connected with 8-bit microprocessor application system, programming Control facility

The timer IP kernel of the present invention directly can be connected with 8-bit microprocessor application system, in timer IP kernel When each timer carries out function setting, 8-bit microprocessor only needs to can determine that this to 1 command word of timer IP kernel transmission The mode of operation of timer, timing base clock pulses frequency dividing multiple；Send the timing that another command word starts the timer Work, and whether the clear timer overflow indicator and whether clear timing currency；For a 16 bit timing devices, timesharing passes Defeated most-significant byte and least-significant byte timing parameters；For a 32 bit timing devices, it is necessary to transmit 32 Bit Time Parameters in four times；8 micro- places Reason device can also directly read the real-time timing value of the timer, programming Control timer facility according to the address of timer.

2. improving timing accuracy, it is adapted to large number of timer timing and time-controlled system requirements

There are 14 16 bit timing devices inside the timer IP kernel of the present invention, need setting command word can according to timing application So that 2 16 bit timing devices are formed into 32 bit timing devices, it is at best able to set 6 32 bit timing devices of composition, additionally it is possible to set selection The frequency dividing multiple of four kinds of timing base clock pulses；When timing is to generation timing spill over, timer IP of the invention The enough automatic reloading timing parameters of nuclear energy；Due to point of the timing base clock pulses of command word setting timer can be passed through Frequency multiple, 32 bit timing devices are formed, the function of automatic reloading timing parameters, timing accuracy is improved, disclosure satisfy that number again Measure numerous timer timings and time-controlled system requirements.

3.FPGA parallel processings timing, timer IP kernel are cost-effective

The present invention is except 8-bit microprocessor carries out function setting to timer, timing parameters transmit, timer timing arrives The clear timing overflow indicator of software, timing currency is read, and needed outside the operation of clear timing currency, 8 will be not take up The program execution time of microprocessor；The timer IP kernel formed using FPGA design hardware circuitry can be reconstructed as 7 16 bit timing devices, 2 16 bit timing devices can be formed 32 bit timing devices, be at best able to set 3 32 bit timing devices of composition；This A kind of timer IP kernel being connected with 8-bit microprocessor application system of invention and its side for realizing timer timing control operation No matter a timer clock fiducial time is how many to method, can select the frequency dividing multiple of four kinds of timing base clock pulses, from Dynamic timing parameters of reloading, the time for taking the program execution of 8-bit microprocessor are greatly reduced, and use it for developing quantity crowd More timer timings and time-controlled system, can obtain very high cost performance.

With reference to the accompanying drawings and examples to a kind of timer IP being connected with 8-bit microprocessor application system of the present invention Core and its realize that the technical characteristic of method of timer timing control operation is further described.

Brief description of the drawings

Fig. 1：A kind of circuit structure block diagram of timer IP kernel being connected with 8-bit microprocessor application system of the present invention；

Fig. 2：A kind of timer IP kernel A being connected with 8-bit microprocessor application system of the embodiment of the present invention one encapsulation Figure；

Fig. 3：A kind of data of timer IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention one are defeated Enter the circuit block diagram that storage control module is decomposed in output with command word；

Fig. 4：A kind of " the timing of timer IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention one The circuit block diagram of processing and control module "；

Fig. 5：A kind of " the timing of timer IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention one The circuit block diagram of device overflow indicator control module "；

Fig. 6：A kind of timer IP kernel B being connected with 8-bit microprocessor application system of the embodiment of the present invention two encapsulation Figure；

Fig. 7：A kind of timer IP kernel B being connected with 8-bit microprocessor application system of the embodiment of the present invention two " timing The circuit block diagram of device overflow indicator control module "；

Fig. 8：A kind of timer IP kernel A's being connected with 8-bit microprocessor application system of embodiments of the present invention one determines When device timing control operation program flow diagram；

Fig. 9：A kind of timer IP kernel B being connected with 8-bit microprocessor application system of the embodiment of the present invention two timing Device timing control operation program flow diagram.

In figure：

I -8-bit microprocessor application system, the output of II-data input and command word decomposition storage control module, III - The frequency divider of pulse 12, IV-Timing Processing control module, V V b of a/-timer overflow indicator control module, VI-input gate Control selection control module；

1-8 bi-directional data strobe triple gate groups, 2-read-write control module, 3-timing parameter register, 4- Timer numbered register, 5-mode of operation frequency dividing multiple code registers, 6-mode control register；

7-NOT gate, 8-M0 mode of operation bit register groups, 9-spilling quenching pulse controller, 10-NAND gate I, 11-d type flip flop I, 12-with door I, 13-NAND gate II, 14-d type flip flop II, 15-NAND gate III, 16-d type flip flop III, 17-with door II, 18-NAND gate IV, 19-d type flip flop IV, 20-NAND gate V, 21-d type flip flop V, 22-with door III, 23-NAND gate VI, 24-d type flip flop VI, 25-NAND gate VII, 26-d type flip flop VII, 27-NAND gate VIII, 28-D triggerings Device VIII, 29-with door IV, 30-NAND gate Ⅸ, 31-d type flip flop Ⅸ, 32-NAND gate Ⅹ, 33-d type flip flop Ⅹ, 34-with Door V, 35-NAND gate Ⅺ, 36-d type flip flop Ⅺ, 37-NAND gate Ⅻ, 38-d type flip flop Ⅻ, 39-with door VI, 40-with NOT gate Ⅹ III, 41-d type flip flop Ⅹ III, 42-NAND gate Ⅹ IV；

43-d type flip flop Ⅹ IV, 44-timer timing control operation module, 45-address strobe control I, 46-8 Timing parameters dual-ported memory, 47-address strobe control II, 48-8 bit timing real-time parameter dual-ported memories, 49- Address strobe control III, 50-4 mode of operations divide times number encoder dual-ported memory, and 51-address strobe controls IV, 52-3 states control dual-ported memory.

Abbreviation explanation in text：

FPGA-Field Programmable Gate Array, field programmable gate array；

RD-Read signals, read signal；

CS-Chip Select signals, chip selection signal；

WR-Write, write signal；

RST-Reset, reset signal；

AB-Address Bus, address bus；

DB-Data Bus, data/address bus；

CLK-Clock pulse, clock pulses；

The overflow indicator output signal that TF- timings arrive；

GATE- gates input signal；

M0-16/32 bit timings device encodes, and M0 is " 0 ", 16 bit timing devices；M0 is " 1 ", 32 bit timing devices；

M1- gate modes encode, and M1 is " 0 ", no gate input signal control timer；M1 is " 1 ", gate input letter Number control timer；

Input data bus inside DB_1- timers IP kernel；

Output data bus inside DB_2- timers IP kernel；

RD_1-8 positions bi-directional data strobe triple gate group read signal；

The real-time timing value read signals of RD_2-；

WR_1-8 positions bi-directional data strobe triple gate group write signal；

WR_2- writes mode of operation frequency dividing multiple coded command word signal；

WR_3- write state control command word signals；

WR_4- write timing device parameter signals；

WR_5- write timing device numbering signals；

I-reference clock pulses of CLK；

II-Timing Processings of CLK control operation clock pulses；

S0, S1, S2- the 0th, the 1st, the 2nd bit timing device number value；

The bit timing device number values of S3- the 3rd；

The gate input signal of GATE0 ~ 13-16 bit timings device 0 ~ 13, wherein GATE1, GATE3, GATE5, GATE8, GATE10, GATE12 correspond to the gate input signal of 32 bit timing devices 0 ~ 5 respectively；

The overflow indicator output signal that the timing of TF0 ~ 13-16 bit timings device 0 ~ 13 arrives, wherein TF1, TF3, TF5, TF8, TF10, TF12 correspond to the overflow indicator output signal that the timing of 32 bit timing devices 0 ~ 5 arrives respectively；

D type flip flop-Data flip-flop；

D-Data input, d type flip flop data input pin；

Q-Data output, d type flip flop data output end；

CP-Clock Pulse input, clock signal input terminal.

Embodiment

A kind of timer IP kernel being connected with 8-bit microprocessor application system：

As shown in figure 1, the timer IP kernel includes data input output decomposes storage control module II, pulse with command word 12 frequency dividers III, Timing Processing control module IV, timer overflow indicator control module V, input gate selection control module Ⅵ；

It is low level that the data input output decomposes storage control module II in the chip selection signal of input with command word Under the conditions of, if write signal is effective, the timer or the ground of timer command word that are given according to 8-bit microprocessor application system I Location, obtain the mode of operation frequency dividing multiple coded command word of timer operation, STATUS control commands word, 16 bit timing devices or 32 The timing parameters of timer, and divide times number encoder and state control difference according to timing parameters, timer numbering, mode of operation Stored and exported, also output write mode of operation frequency dividing multiple coded command word signal, write state control command word signal and Write timing device parameter signal；If read signal effectively transmits the real-time timing value of timer to 8-bit microprocessor application system I；

The frequency divider III of pulse 12 is used to divide the clock pulses of 8-bit microprocessor application system I, and it is exported Reference clock pulse as the timer timing control operation of Timing Processing control module IV；

The Timing Processing control module IV write mode of operation frequency dividing multiple coded command word signal in the presence of, according to Timer numbering stores the mode of operation of the timer, and reference clock divides the encoded radio of multiple；In write state control command word In the presence of signal, the state control signal for storing the timer is numbered according to timer；In the work of write timing device parameter signal Under, the timing parameters for storing the timer are numbered according to timer；Outside the timer IP kernel of Timing Processing control module IV The clock pulses CLK II of portion's input controls the operation of Timing Processing control module, according to one of the output of the frequency divider III of pulse 12 The reference clock pulse cycle completes a Timing Processing of all timers, includes the state control process of each timer, work The judgement processing of operation mode, it is fixed to each 16/32 according to the reference clock multiple value that each 16/32 bit timing device is set When device real-time timing parameter value carry out plus 1 operation, produce spilling when, real-time timing parameter value is reloaded automatically timing join Number, and export overflow indicator signal；The chip selection signal of the input of storage control module II is decomposed with command word in data input output Under the conditions of low level, if read signal is effective, the address of the timer given according to 8-bit microprocessor application system I, directly Connect read the timer real-time timing parameter value through data input output with command word decompose storage control module II be transferred to 8 The data/address bus of bit microprocessor application system I, the real-time timing parameters of 16 bit timing devices need timesharing to be read twice, and 32 The real-time timing parameters of bit timing device need timesharing to be read for four times；In the reset letter that 8-bit microprocessor application system I exports Under number effect, stop the fixed cycle operators of all timers；

The high level that the timer overflow indicator control module V is used to export 16/32 bit timing devices effectively overflows Signal；When the spill over for the 16 bit timing devices that Timing Processing control module IV exports is transformed to high level by low level, storage The timer overflow indicator is high level；If the timer overflow indicator is high level, clear overflow indicator is changed by high level For low level, it is low level to store the timer overflow indicator；Writing the work of mode of operation frequency dividing multiple coded command word signal Under, timer overflow indicator control module V stores the information of 32 bit timing device mode of operations, block according to register number The flooding information of low 16 of the 32 bit timing device remains low level；

The input gate selection control module VI is pressed in the case where writing mode of operation frequency dividing multiple coded command word signal function According to timer number store the timer mode of operation, according to determined by the runs pattern gate control function requirement and The gate level of input, the gate-control signal that control input gate selection control module VI exports；

The data input output decomposes storage control module II and 8-bit microprocessor application system I, timing with command word Processing and control module IV, timer overflow indicator control module V and input gate selection control module VI connect；

The frequency divider III of pulse 12 is also connected with 8-bit microprocessor application system I and Timing Processing control module IV；

The Timing Processing control module IV also with 8-bit microprocessor application system I, timer overflow indicator control module V connects with input gate selection control module VI.

In order to be adapted to large number of timer timing with time-controlled system requirements, the need applied according to different timings Will, the encapsulation of setting command word forms the timer IP kernel of different digits, therefore, there is following several embodiments：Such as can So that 2 16 bit timing devices are formed into 32 bit timing devices, it is at best able to set 6 32 bit timing devices of composition, additionally it is possible to set selection Frequency dividing multiple of four kinds of timing base clock pulses etc.；It is described below below.

Embodiment one：

A kind of timer IP kernel being connected with 8-bit microprocessor application system that 6 32 bit timing devices of composition can be set A,（Hereinafter referred to as：Timer IP kernel A）：

Export and order as described above, the timer IP kernel A that should be connected with 8-bit microprocessor application system includes data input Word is made to decompose storage control module II, the frequency divider III of pulse 12, Timing Processing control module IV, timer overflow indicator control mould Block V, input gate selection control module VI（Referring to Fig. 1）, timer IP kernel A has 48 pins, and it encapsulates figure referring to Fig. 2；

As shown in figure 3, the data input output decomposes storage control module II with command word includes 8 bi-directional datas choosings Logical triple gate group 1, read-write control module 2, timing parameter register 3, timer numbered register 4, mode of operation frequency dividing Multiple code registers 5, mode control register 6；

8 bi-directional data strobe triple gates group 1 controls mould with 8-bit microprocessor application system I, read-write respectively Block 2, timing parameter register 3, timer numbered register 4, mode of operation frequency dividing multiple code registers 5, state control is posted Storage 6 and Timing Processing control module IV connect；

The read-write control module 2 also with 8-bit microprocessor application system I, timing parameter register 3, timer Numbered register 4, mode of operation frequency dividing multiple code registers 5, mode control register 6, Timing Processing control module IV, determines When device overflow indicator control module V and input gate selection control module VI connect；

The timing parameter register 3 is also connected with Timing Processing control module IV；

The timer numbered register 4 also with 8-bit microprocessor application system I, Timing Processing control module IV, timing Device overflow indicator control module V and input gate selection control module VI connect；

The mode of operation frequency dividing multiple code registers 5 also control with 8-bit microprocessor application system I, Timing Processing Module IV, timer overflow indicator control module V and input gate selection control module VI connect；

The mode control register 6 also with 8-bit microprocessor application system I, Timing Processing control module IV and timing Device overflow indicator control module V connects.

As shown in figure 4, the Timing Processing control module IV includes timer timing control operation module 44, address strobe I 45,8 Bit Time Parameters dual-ported memories 46 are controlled, address strobe controls the storage of II 47,8 bit timing real-time parameter dual-ports Device 48, address strobe control III 49,4 mode of operation frequency dividing times number encoder dual-ported memories 50, and address strobe controls IV 51, 3 states control dual-ported memory 52；

The timer timing control operation module 44 controls mould with the frequency divider III of pulse 12, timer overflow indicator respectively Block V, timer overflow indicator control module V, address strobe control I 45,8 Bit Time Parameters dual-ported memories 46, address II 47,8 bit timing real-time parameter dual-ported memories 48 of gating control, address strobe control III 49,4 mode of operation frequency dividings times Number encoder dual-ported memory 50, address strobe control IV 51 and 3 state control dual-ported memories 52 and timer device IP The Timing Processing control operation clock pulses CLK II of core outside input is connected；

The address strobe control I 45 also decomposes storage control module II with command word with data input output and 8 fixed When parameter dual-ported memory 46 connect；

The 8 Bit Time Parameters dual-ported memory 46 also decomposes storage control module with data input output with command word II and 8 bit timing real-time parameter dual-ported memory 48 connect；

The address strobe control II 47 is also decomposed with 8-bit microprocessor application system I, data input output with command word The bit timing real-time parameter dual-ported memory 48 of storage control module II and 8 connects；

The 8 bit timing real-time parameter dual-ported memory 48 also decomposes storage control with data input output and command word Module II connects；

The address strobe control III 49 also decomposes storage control module II and 4 works with data input output with command word An operation mode frequency dividing times number encoder dual-ported memory 50 connects；

4 mode of operations frequency dividing times number encoder dual-ported memory 50 also decomposes with data input output with command word Storage control module II connects；

The address strobe control IV 51 also decomposes storage control module II and 3 shapes with data input output with command word State control dual-ported memory 52 connects；

3 states control dual-ported memory 52 also decomposes storage control module with data input output with command word IIth, the reset signal connection of 8-bit microprocessor application system I；If the reset signal of input is effective reset signal, reset 3 states control dual-ported memory 52, stop the fixed cycle operator of all timers.

As shown in figure 5, the timer overflow indicator control module V includes NOT gate 7, M0 mode of operation bit register groups 8, overflow quenching pulse controller 9, NAND gate I 10, d type flip flop I 11, and door I 12, NAND gate II 13, d type flip flop II 14, with NOT gate III 15, d type flip flop III 16, and door II 17, NAND gate IV 18, d type flip flop IV 19, NAND gate V 20, d type flip flop V 21, With door III 22, NAND gate VI 23, d type flip flop VI 24, NAND gate VII 25, d type flip flop VII 26, NAND gate VIII 27, d type flip flop VIII 28, with door IV 29, NAND gate Ⅸ 30, d type flip flop Ⅸ 31, NAND gate Ⅹ 32, d type flip flop Ⅹ 33, with door V 34, NAND gate Ⅺ 35, d type flip flop Ⅺ 36, NAND gate Ⅻ 37, d type flip flop Ⅻ 38, and door VI 39, NAND gate Ⅹ III 40, d type flip flop Ⅹ III 41, with NOT gate Ⅹ IV 42, d type flip flop Ⅹ IV 43；

The input of the NOT gate 7 is exported with data input and posted with the state control of command word decomposition storage control module II The M0 output ends connection of storage 6, output end are connected with an input of M0 mode of operation bit registers group 8；

The other three input of M0 mode of operation bit registers group 8 is believed with the reset of 8-bit microprocessor application system I respectively What number output end, data input output and command word decomposed the read-write control module 2 of storage control module II writes Working mould Formula frequency dividing multiple coded command word signal output part connects with the timer numbering output end of timer numbered register 4, exports End is connected with door I 12, with door II 17, with door III 22, with door IV 29, with door V 34, with an input of door VI 39 respectively；

Three inputs for overflowing quenching pulse controller 9 decompose storage control with data input output and command word respectively The write state control command word signal output part of the read-write control module 2 of module II, the clear spilling of mode control register 6 Mark output end connects with the timer numbering output end of timer numbered register 4, output end difference NAND gate I 10, with it is non- Door II 13, NAND gate III 15, NAND gate IV 18, NAND gate V 20, NAND gate VI 23, NAND gate VII 25, NAND gate VIII 27, with it is non- Door Ⅸ 30, NAND gate Ⅹ 32, NAND gate Ⅺ 35, NAND gate Ⅻ 37, NAND gate Ⅹ III 40, an input of NAND gate Ⅹ IV 42 Connection；Output end is also touched with d type flip flop I 11, d type flip flop II 14, d type flip flop III 16, d type flip flop IV 19, d type flip flop V 21, D Send out device VI 24, d type flip flop VII 26, d type flip flop VIII 28, d type flip flop Ⅸ 31, d type flip flop Ⅹ 33, d type flip flop Ⅺ 36, d type flip flop Ⅻ 38, d type flip flop Ⅹ III 41 connects with the data input pin of d type flip flop Ⅹ IV 43；

Another input of NAND gate I 10 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop I 11；

The data output end of d type flip flop I 11 and it is connected with another input of door I 12；

With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door I 12 as 16 bit timing devices 0 I connection；

Another input of NAND gate II 13 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop II 14；

Overflow indicator output signal of the data output end of d type flip flop II 14 as the bit timing device 0 of 16 bit timing device 1/32 Output end is connected with 8-bit microprocessor application system I；

Another input of NAND gate III 15 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop III 16；

The data output end of d type flip flop III 16 and it is connected with another input of door II 17；

Applied with the output end of door II 17 as the overflow indicator output signal of 16 bit timing devices 2 with 8-bit microprocessor and be The connection of system I；

Another input of NAND gate IV 18 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop IV 19；

Overflow indicator output signal of the data output end of d type flip flop IV 19 as the bit timing device 1 of 16 bit timing device 3/32 Output end is connected with 8-bit microprocessor application system I；

Another input of NAND gate V 20 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop V 21；

The data output end of d type flip flop V 21 and it is connected with another input of door III 22；

Applied with the output end of door III 22 as the overflow indicator output signal of 16 bit timing devices 4 with 8-bit microprocessor and be The connection of system I；

Another input of NAND gate VI 23 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop VI 24；

Overflow indicator output signal of the data output end of d type flip flop VI 24 as the bit timing device 2 of 16 bit timing device 5/32 Output end is connected with 8-bit microprocessor application system I；

Another input of NAND gate VII 25 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop VII 26；

The data output end of d type flip flop VII 26 is micro- as the overflow indicator output signal output end of 16 bit timing devices 6 and 8 Processor application system I connects；

Another input of NAND gate VIII 27 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop VIII 28；

The data output end of d type flip flop VIII 28 and it is connected with another input of door IV 29；

Applied with the output end of door IV 29 as the overflow indicator output signal of 16 bit timing devices 7 with 8-bit microprocessor and be The connection of system I；

Another input of NAND gate Ⅸ 30 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop Ⅸ 31；

Overflow indicator output signal of the data output end of d type flip flop Ⅸ 31 as the bit timing device 3 of 16 bit timing device 8/32 Output end is connected with 8-bit microprocessor application system I；

Another input of NAND gate Ⅹ 32 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop Ⅹ 33；

The data output end of d type flip flop Ⅹ 33 and it is connected with another input of door V 34；

Applied with the output end of door V 34 as the overflow indicator output signal of 16 bit timing devices 9 with 8-bit microprocessor and be The connection of system I；

Another input of NAND gate Ⅺ 35 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop Ⅺ 36；

Overflow indicator output signal of the data output end of d type flip flop Ⅺ 36 as the bit timing device 4 of 16 bit timing device 10/32 Output end is connected with 8-bit microprocessor application system I；

Another input of NAND gate Ⅻ 37 is connected with the overflow indicator output end of Timing Processing control module IV, output End is connected with the clock signal input terminal of d type flip flop Ⅻ 38；

The data output end of d type flip flop Ⅻ 38 and it is connected with an input of door VI 39；

Applied with the output end of door VI 39 as the overflow indicator output signal of 16 bit timing devices 11 with 8-bit microprocessor and be The connection of system I；

Another input of NAND gate Ⅹ III 40 is connected with the overflow indicator output end of Timing Processing control module IV, defeated Go out end to be connected with the clock signal input terminal of d type flip flop Ⅹ III 41；

The data output end of d type flip flop Ⅹ III 41 exports letter as the overflow indicator of the bit timing device 5 of 16 bit timing device 12/32 Number output end is connected with 8-bit microprocessor application system I；

Another input of NAND gate Ⅹ IV 42 is connected with the overflow indicator output end of Timing Processing control module IV, defeated Go out end to be connected with the clock signal input terminal of d type flip flop Ⅹ IV 43；

The data output end of d type flip flop Ⅹ IV 43 is as the overflow indicator output signal output end of 16 bit timing device 13 and 8 Microprocessor application system I connects.

Timer IP kernel A timer is with command address coding schedule referring to subordinate list one《With 8-bit microprocessor application system The timer IP kernel A of connection timer and command address coding schedule》；Mode of operation divides multiple coded command word referring to subordinate list Two《Timer IP kernel A mode of operation frequency dividing multiple coded command word list》；STATUS control commands word is referring to subordinate list three《It is fixed When device IP kernel A STATUS control commands word list》.

The timer IP kernel A being connected with 8-bit microprocessor application system is used to realize timer timing control operation The program flow diagram of method is referring to Fig. 8；

It is concretely comprised the following steps：

s102：Reference clock pulse trailing edge trigger performs 1 time；

s104：Timer number value j=00H, return to step s102 are set；

s106：Timer number value j=10H is set, into step s107；

s109：The value of the timer timing memory cell is removed, into step s110；

s110：Timer number value j adds 2, return to step s103；

s117：Timer numbering j adds 4：J=j+4, return to step s103；

Embodiment two：

A kind of timer IP kernel being connected with 8-bit microprocessor application system that 3 32 bit timing devices of composition can be set B,（Hereinafter referred to as：Timer IP kernel B）：

Timer IP kernel B has 34 pins, and it encapsulates figure referring to Fig. 6；

Timer IP kernel B basic structure is with embodiment one with the difference of embodiment one：The timer IP kernel B has 7 16 bit timing devices, wherein 6 can make up 3 32 bit timing devices；The timer overflow indicator control module V Overflow indicator output signal TF0 ~ 13 are transformed to overflow indicator output signal TF0 ~ 7, the input gate selection control module VI Gate input signal GATE0 ~ 13 be transformed to gate input signal GATE0 ~ 7, referring to Fig. 1；The data input output and life The 4th bit timing device number value S3 and timer numbering for making the read-write control module 2 of word decomposition storage control module II are posted The connecting line of storage 4 is deleted；The b of timer overflow indicator control module V circuit block diagram is referring to Fig. 7.

Timer IP kernel B timer is with command address coding schedule referring to subordinate list four《Timer IP kernel B timer and life Make geocoding table》；Mode of operation divides multiple coded command word referring to subordinate list five《Timer IP kernel B mode of operation frequency dividing Multiple coded command word list》；STATUS control commands word is referring to subordinate list six《Timer IP kernel B STATUS control commands word one Look at table》.

The program flow diagram that timer IP kernel B is used to realize timer timing control operation is referring to Fig. 9；With timer IP Core A timer timing control operation program flow diagram difference is：Timer IP kernel A s105 and s106 operation step Suddenly deleted, step s103 is transformed to：Judge whether timer number value j is equal to or more than 1EH, if j value be equal to or More than 1EH, then into step s104, otherwise into s107.

Embodiment three：

A kind of timer IP kernel being connected with 8-bit microprocessor application system, the frequency divider III of pulse 12 in Fig. 1 determine The timing base clock of timer IP kernel, the frequency divider III of pulse 12 is transformed to 50 frequency dividers III, adapt to 8-bit microprocessor when Clock frequency is more than 12MHz situation.

Example IV：

A kind of timer IP kernel being connected with 8-bit microprocessor application system, the frequency divider III of pulse 12 in Fig. 1 determine The timing base clock of timer IP kernel, the frequency divider III of pulse 12 is transformed to 100 frequency dividers III, adapts to 8-bit microprocessor Clock frequency is greatly more than 12MHz situation.

Subordinate list one：

《The timer for the timer IP kernel A being connected with 8-bit microprocessor application system and command address coding schedule》

Subordinate list two：《Timer IP kernel A mode of operation frequency dividing multiple coded command word list》

Subordinate list three：《Timer IP kernel A STATUS control commands word list》

Subordinate list four：《Timer IP kernel B timer and command address coding schedule》

Subordinate list five：《Timer IP kernel B mode of operation frequency dividing multiple coded command word list》

Subordinate list six：《Timer IP kernel B STATUS control commands word list》

Claims

A kind of 1. timer IP kernel being connected with 8-bit microprocessor application system, it is characterised in that：The timer IP kernel includes number Storage control module is decomposed according to input and output and command word（Ⅱ）, the frequency divider of pulse 12（Ⅲ）, Timing Processing control module（Ⅳ）, Timer overflow indicator control module（Ⅴ）, input gate selection control module（Ⅵ）；

The data input output decomposes storage control module with command word（Ⅱ）With 8-bit microprocessor application system（Ⅰ）, timing Processing and control module（Ⅳ）, timer overflow indicator control module（Ⅴ）Selection control module is gated with input（Ⅵ）Connection；

The frequency divider of pulse 12（Ⅲ）Also with 8-bit microprocessor application system（Ⅰ）With Timing Processing control module（Ⅳ）Connection；

The Timing Processing control module（Ⅳ）Also with 8-bit microprocessor application system（Ⅰ）, timer overflow indicator control module （Ⅴ）Selection control module is gated with input（Ⅵ）Connection；

The data input output decomposes storage control module with command word（Ⅱ）It is low level bar in the chip selection signal of input Under part, if write signal is effective, according to 8-bit microprocessor application system（Ⅰ）Given timer or the ground of timer command word Location, obtains timer command word, the timing parameters of 16 bit timing devices or 32 bit timing devices, and by 16 bit timing devices or 32 bit timings The timing parameters of device, timer command word is numbered according to command word everybody definition according to timer, mode of operation divides multiple Coding and state control are stored and exported respectively, and also output writes mode of operation frequency dividing multiple coded command word signal, writes shape State control command word signal and write timing device parameter signal；Under the conditions of the chip selection signal of input is low level, if reading letter Number effectively, to 8-bit microprocessor application system（Ⅰ）Transmit the real-time timing value of timer；

The frequency divider of pulse 12（Ⅲ）To 8-bit microprocessor application system（Ⅰ）Clock pulses divided, its export conduct Timing Processing control module（Ⅳ）Timer timing control operation reference clock pulse；

The Timing Processing control module（Ⅳ）In the presence of mode of operation frequency dividing multiple coded command word signal is write, according to fixed When device numbering store the timer mode of operation, reference clock divide multiple encoded radio；Believe in write state control command word In the presence of number, the state control signal for storing the timer is numbered according to timer；In the effect of write timing device parameter signal Under, the timing parameters for storing the timer are numbered according to timer；The Timing Processing control module（Ⅳ）Outside timer IP kernel The clock pulses CLK II of portion's input controls the operation of Timing Processing control module, according to the frequency divider of pulse 12（Ⅲ）The one of output Individual reference clock pulse completes a Timing Processing of all timers, includes the state control process of each timer, work The judgement processing of pattern, the reference clock multiple value set according to each 16/32 bit timing device is to each 16/32 bit timing The real-time timing parameter value of device carries out plus 1 operation, and when producing spilling, timing parameters are reloaded automatically to real-time timing parameter value, And export overflow indicator；In data input output storage control module is decomposed with command word（Ⅱ）The chip selection signal of input is low electricity Under conditions of flat, if read signal is effective, according to 8-bit microprocessor application system（Ⅰ）The address of given timer, directly read The real-time timing value for going out the timer decomposes storage control module through data input output with command word（Ⅱ）It is transferred to 8 micro- places Manage device application system（Ⅰ）Data/address bus, the real-time timing parameters of 16 bit timing devices need timesharing to be read twice, and 32 are fixed When device real-time timing parameters need timesharing to be read for four times；In 8-bit microprocessor application system（Ⅰ）The reset signal of output Under effect, stop the fixed cycle operator of all timers；

The timer overflow indicator control module（Ⅴ）Export the high level effectively spill over of 16/32 bit timing devices； Timing Processing control module（Ⅳ）When the spill over of 16 bit timing devices of output is transformed to high level by low level, 8 micro- places Manage device application system（Ⅰ）It is high level to store the timer overflow indicator；It is clear to overflow if the timer overflow indicator is high level Go out mark and low level is converted to by high level, it is low level to store the timer overflow indicator；Writing mode of operation frequency dividing multiple In the presence of coded command word signal, timer overflow indicator control module（Ⅴ）32 bit timing devices are stored according to register number The information of mode of operation, the spill over for blocking low 16 of the 32 bit timing device remain low level；

The input gate selection control module（Ⅵ）In the case where writing mode of operation frequency dividing multiple coded command word signal function, according to Timer numbering stores the mode of operation of the timer, is required according to gate control function determined by the runs pattern and defeated The gate level entered, control input gate selection control module（Ⅵ）The gate-control signal of output.
A kind of 2. timer IP kernel being connected with 8-bit microprocessor application system as claimed in claim 1, it is characterised in that： The data input output decomposes storage control module with command word（Ⅱ）Including 8 bi-directional data strobe triple gate groups（1）, read Write signal control module（2）, timing parameter register（3）, timer numbered register（4）, mode of operation frequency dividing times number encoder Register（5）, mode control register（6）；

8 bi-directional data strobes triple gate group（1）Respectively with 8-bit microprocessor application system（Ⅰ）, read-write control mould Block（2）, timing parameter register（3）, timer numbered register（4）, mode of operation frequency dividing multiple code registers（5）, shape State control register（6）With Timing Processing control module（Ⅳ）Connection；

The read-write control module（2）Also with 8-bit microprocessor application system（Ⅰ）, timing parameter register（3）, timing Device numbered register（4）, mode of operation frequency dividing multiple code registers（5）, mode control register（6）, Timing Processing control Module（Ⅳ）, timer overflow indicator control module（Ⅴ）Selection control module is gated with input（Ⅵ）Connection；

The timing parameter register（3）Also with Timing Processing control module（Ⅳ）Connection；

The timer numbered register（4）Also with 8-bit microprocessor application system（Ⅰ）, Timing Processing control module（Ⅳ）, it is fixed When device overflow indicator control module（Ⅴ）Selection control module is gated with input（Ⅵ）Connection；

The mode of operation divides multiple code registers（5）Also with 8-bit microprocessor application system（Ⅰ）, Timing Processing control Module（Ⅳ）, timer overflow indicator control module（Ⅴ）Selection control module is gated with input（Ⅵ）Connection；

The mode control register（6）Also with 8-bit microprocessor application system（Ⅰ）, Timing Processing control module（Ⅳ）With it is fixed When device overflow indicator control module（Ⅴ）Connection；

The data input output decomposes storage control module with command word（Ⅱ）Read-write control module（2）Select and believe in piece Number under the conditions of low level, if write signal is effective, to send 8 bi-directional data strobe triple gate groups（1）Write signal, gating 8 Bit microprocessor application system（Ⅰ）The data input of data/address bus, write timing device numbering signal is produced, and judge the address of input Value, if the address value of timer parameter, the address value is write into timer numbered register（4）, produce write timing device ginseng Number signal, the data of data/address bus are write into timing parameter register（3）；If timer order word address, total by data The 2nd of line ~ the 5th data write-in timer numbered register（4）, order word address is 0EH or 0FH, sets the 3rd bit timing Device number value S3 is 0, is otherwise provided as 1；If command word least-significant byte address, then command word is that mode of operation frequency dividing multiple is compiled Code command word, generation write mode of operation frequency dividing multiple coded command word signal, by the 0th of data/address bus, the 1st, the 6th and 7th write-in mode of operation frequency dividing multiple code registers（5）；If command word most-significant byte address, then command word is state control Command word processed, write state control command word signal is produced, the 0th of data/address bus, the 1st and the 7th write state is controlled Register（6）；If read signal is effective, 8 bi-directional data strobe triple gate groups are sent（1）Read signal, Timing Processing is controlled Module（Ⅳ）Timer IP kernel inside output data bus data transfer to 8-bit microprocessor application system（Ⅰ）Data Bus.
A kind of 3. timer IP kernel being connected with 8-bit microprocessor application system as claimed in claim 2, it is characterised in that： The Timing Processing control module（Ⅳ）Including timer timing control operation module（44）, address strobe control I（45）, 8 Timing parameters dual-ported memory（46）, address strobe control II（47）, 8 bit timing real-time parameter dual-ported memories（48）, Address strobe control III（49）, 4 mode of operations frequency dividing times number encoder dual-ported memories（50）, address strobe control IV （51）, 3 states control dual-ported memories（52）；

The timer timing control operation module（44）Respectively with the frequency divider of pulse 12（Ⅲ）, timer overflow indicator control mould Block（Ⅴ）, timer overflow indicator control module（Ⅴ）, address strobe control I（45）, 8 Bit Time Parameters dual-ported memories （46）, address strobe control II（47）, 8 bit timing real-time parameter dual-ported memories（48）, address strobe control III（49）、4 Position mode of operation frequency dividing times number encoder dual-ported memory（50）, address strobe control IV（51）, 3 state control dual-ports deposit Reservoir（52）Connected with the Timing Processing control operation clock pulses CLK II of timer device IP kernel outside input；

The address strobe control I（45）Also storage control module is decomposed with data input output with command word（Ⅱ）It is fixed with 8 When parameter dual-ported memory（46）Connection；

The 8 Bit Time Parameters dual-ported memory（46）Also storage control module is decomposed with data input output with command word （Ⅱ）With 8 bit timing real-time parameter dual-ported memories（48）Connection；

The address strobe control II（47）Also with 8-bit microprocessor application system（Ⅰ）, data input output with command word decompose Storage control module（Ⅱ）With 8 bit timing real-time parameter dual-ported memories（48）Connection；

The 8 bit timing real-time parameter dual-ported memory（48）Also storage control mould is decomposed with data input output and command word Block（Ⅱ）Connection；

The address strobe control III（49）Also storage control module is decomposed with data input output with command word（Ⅱ）With 4 works Operation mode divides times number encoder dual-ported memory（50）Connection；

4 mode of operations divide times number encoder dual-ported memory（50）Also export to decompose with command word with data input and deposit Store up control module（Ⅱ）Connection；

The address strobe control IV（51）Also storage control module is decomposed with data input output with command word（Ⅱ）With 3 shapes State controls dual-ported memory（52）Connection；

3 states control dual-ported memory（52）Also storage control module is decomposed with data input output with command word （Ⅱ）, 8-bit microprocessor application system（Ⅰ）Reset signal connection；If the reset signal of input is effective reset signal, Reset 3 state control dual-ported memories（52）, stop the fixed cycle operators of all timers.
A kind of 4. timer IP kernel being connected with 8-bit microprocessor application system as claimed in claim 3, it is characterised in that： The timer overflow indicator control module（Ⅴ）Including NOT gate（7）, M0 mode of operation bit register groups（8）, overflow and reset arteries and veins Rush controller（9）, NAND gate I（10）, d type flip flop I（11）, with door I（12）, NAND gate II（13）, d type flip flop II（14）, with NOT gate III（15）, d type flip flop III（16）, with door II（17）, NAND gate IV（18）, d type flip flop IV（19）, NAND gate V（20）, D Trigger V（21）, with door III（22）, NAND gate VI（23）, d type flip flop VI（24）, NAND gate VII（25）, d type flip flop VII （26）, NAND gate VIII（27）, d type flip flop VIII（28）, with door IV（29）, NAND gate Ⅸ（30）, d type flip flop Ⅸ（31）, NAND gate Ⅹ（32）, d type flip flop Ⅹ（33）, with door V（34）, NAND gate Ⅺ（35）, d type flip flop Ⅺ（36）, NAND gate Ⅻ（37）, D triggerings Device Ⅻ（38）, with door VI（39）, NAND gate Ⅹ III（40）, d type flip flop Ⅹ III（41）, NAND gate Ⅹ IV（42）, d type flip flop Ⅹ IV （43）；

The NOT gate（7）The output of input and data input decompose storage control module with command word（Ⅱ）State control post Storage（6）The connection of M0 output ends, output end and M0 mode of operation bit register groups（8）An input connection；

M0 mode of operation bit register groups（8）The other three input respectively with 8-bit microprocessor application system（Ⅰ）Reset letter Number output end, data input output decompose storage control module with command word（Ⅱ）Read-write control module（2）Write work Operation mode divides multiple coded command word signal output part and timer numbered register（4）Timer numbering output end connect Connect, output end respectively with door I（12）And door II（17）And door III（22）And door IV（29）And door V（34）And door VI（39） An input connection；

Overflow quenching pulse controller（9）Three inputs respectively with data input output with command word decompose storage control mould Block（Ⅱ）Read-write control module（2）Write state control command word signal output part, mode control register（6）It is clear Overflow indicator output end and timer numbered register（4）Timer numbering output end connection, output end difference NAND gate I （10）, NAND gate II（13）, NAND gate III（15）, NAND gate IV（18）, NAND gate V（20）, NAND gate VI（23）, NAND gate Ⅶ（25）, NAND gate VIII（27）, NAND gate Ⅸ（30）, NAND gate Ⅹ（32）, NAND gate Ⅺ（35）, NAND gate Ⅻ（37）, with it is non- Door Ⅹ III（40）, NAND gate Ⅹ IV（42）An input connection；Output end also with d type flip flop I（11）, d type flip flop II （14）, d type flip flop III（16）, d type flip flop IV（19）, d type flip flop V（21）, d type flip flop VI（24）, d type flip flop VII（26）、D Trigger VIII（28）, d type flip flop Ⅸ（31）, d type flip flop Ⅹ（33）, d type flip flop Ⅺ（36）, d type flip flop Ⅻ（38）, d type flip flop ⅩⅢ（41）With d type flip flop Ⅹ IV（43）Data input pin connection；

NAND gate I（10）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop I（11）Clock signal input terminal connection；

D type flip flop I（11）Data output end and with door I（12）Another input connection；

With door I（12）Overflow indicator output signal output end and 8-bit microprocessor application of the output end as 16 bit timing devices 0 System（Ⅰ）Connection；

NAND gate II（13）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop II（14）Clock signal input terminal connection；

D type flip flop II（14）Data output end it is defeated as the overflow indicator output signal of the bit timing device 0 of 16 bit timing device 1/32 Go out end and 8-bit microprocessor application system（Ⅰ）Connection；

NAND gate III（15）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop III（16）Clock signal input terminal connection；

D type flip flop III（16）Data output end and with door II（17）Another input connection；

With door II（17）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 bit timing devices 2 （Ⅰ）Connection；

NAND gate IV（18）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop IV（19）Clock signal input terminal connection；

D type flip flop IV（19）Data output end it is defeated as the overflow indicator output signal of the bit timing device 1 of 16 bit timing device 3/32 Go out end and 8-bit microprocessor application system（Ⅰ）Connection；

NAND gate V（20）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop V（21）Clock signal input terminal connection；

D type flip flop V（21）Data output end and with door III（22）Another input connection；

With door III（22）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 bit timing devices 4 （Ⅰ）Connection；

NAND gate VI（23）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop VI（24）Clock signal input terminal connection；

D type flip flop VI（24）Data output end it is defeated as the overflow indicator output signal of the bit timing device 2 of 16 bit timing device 5/32 Go out end and 8-bit microprocessor application system（Ⅰ）Connection；

NAND gate VII（25）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop VII（26）Clock signal input terminal connection；

D type flip flop VII（26）Overflow indicator output signal output end and 8 micro- places of the data output end as 16 bit timing devices 6 Manage device application system（Ⅰ）Connection；

NAND gate VIII（27）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop VIII（28）Clock signal input terminal connection；

D type flip flop VIII（28）Data output end and with door IV（29）Another input connection；

With door IV（29）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 bit timing devices 7 （Ⅰ）Connection；

NAND gate Ⅸ（30）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop Ⅸ（31）Clock signal input terminal connection；

D type flip flop Ⅸ（31）Data output end it is defeated as the overflow indicator output signal of the bit timing device 3 of 16 bit timing device 8/32 Go out end and 8-bit microprocessor application system（Ⅰ）Connection；

NAND gate Ⅹ（32）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop Ⅹ（33）Clock signal input terminal connection；

D type flip flop Ⅹ（33）Data output end and with door V（34）Another input connection；

With door V（34）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 bit timing devices 9 （Ⅰ）Connection；

NAND gate Ⅺ（35）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop Ⅺ（36）Clock signal input terminal connection；

D type flip flop Ⅺ（36）Data output end it is defeated as the overflow indicator output signal of the bit timing device 4 of 16 bit timing device 10/32 Go out end and 8-bit microprocessor application system（Ⅰ）Connection；

NAND gate Ⅻ（37）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, output End and d type flip flop Ⅻ（38）Clock signal input terminal connection；

D type flip flop Ⅻ（38）Data output end and with door VI（39）An input connection；

With door VI（39）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 bit timing devices 11 （Ⅰ）Connection；

NAND gate Ⅹ III（40）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, it is defeated Go out end and d type flip flop Ⅹ III（41）Clock signal input terminal connection；

D type flip flop Ⅹ III（41）Overflow indicator output signal of the data output end as the bit timing device 5 of 16 bit timing device 12/32 Output end and 8-bit microprocessor application system（Ⅰ）Connection；

NAND gate Ⅹ IV（42）Another input and Timing Processing control module（Ⅳ）Overflow indicator output end connection, it is defeated Go out end and d type flip flop Ⅹ IV（43）Clock signal input terminal connection；

D type flip flop Ⅹ IV（43）Data output end it is micro- as the overflow indicator output signal output end of 16 bit timing device 13 and 8 Processor application system（Ⅰ）Connection.
5. a kind of timer IP kernel being connected with 8-bit microprocessor application system is used for the side for realizing timer timing control operation Method, it is characterised in that：It is with a kind of timer IP being connected with 8-bit microprocessor application system described in claim 4 Core realizes the method for timer timing control operation；

It is concretely comprised the following steps：

s101：Clear reference clock pulse frequency dividing multiple u storage of array units, timer number value j；

s102：Reference clock pulse trailing edge trigger performs 1 time；

s103：Judge whether timer number value j is equal to or more than 1EH, if j value is equal to or more than 1EH, into step S104, otherwise into s105；

s104：Timer number value j=00H, return to step s102 are set；

s105：Judge whether timer number value j is equal to 0EH or 0FH, if j value is equal to 0EH or 0FH, enter step Rapid s106, otherwise into step s107；

s106：Timer number value j=10H is set, into step s107；

s107：Judgement opens/stopped whether signal is equal to 0, if open/stopping signal=0, the timer stops timing working, into step S108, otherwise into step s111；

s108：Judge whether clear timing currency is equal to 0, if clear timing currency=0, into step s109, otherwise enters Step s110；

s109：The value of the timer timing memory cell is removed, into step s110；

s110：Timer number value j adds 2, return to step s103；

s111：The reference clock pulse frequency dividing multiple of the timer adds 1：U (j)=u (j)+1, into step s112；

s112：Judge the runs pattern, if mode of operation M1M0=10,16 bit timing devices are gated, into step s113；If mode of operation M1M0=00,16 bit timing devices of no gate, into step s118；If mode of operation M1M0=01, The 32 bit timing devices without gate, into step s114；If mode of operation M1M0=11,32 bit timing devices of gate are selected, are entered Enter step s115；

s113：Whether the gate-control signal for judging the 16 bit timing device is 0, and return to step s110, no if gate-control signal is equal to 0 Then enter step s118；

s114：Judge whether low 2 of 32 bit timing device numbering j be equal to 00, if equal to 00 enters step s126, otherwise Return to step s110；

s115：Judge whether low 2 of 32 bit timing device numbering j be equal to 00, if equal to 00 enters step s116, otherwise Return to step s110；

s116：Whether the gate-control signal for judging the 32 bit timing device is 0, no into step s117 if gate-control signal is equal to 0 Then enter step s126；

s117：Timer numbering j adds 4：J=j+4, return to step s103；

s118：The coding of the frequency dividing multiple of the 16 bit timing device is judged, if frequency dividing multiple is encoded to F2F1=00, into step Rapid s122；If frequency dividing multiple is encoded to F2F1=01, into step s119；If frequency dividing multiple be encoded to F2F1= 10, then into step s120；If frequency dividing multiple is encoded to F2F1=11, into step s121；

s119：Judge whether the reference clock pulse frequency dividing multiple u (j) of 16 bit timing device value is equal to 10, if u (j)= 10, then into step s122, otherwise return to step s110；

s120：Judge whether the reference clock pulse frequency dividing multiple u (j) of 16 bit timing device value is equal to 100, if u (j)= 100, then into step s122, otherwise return to step s110；

s121：Judge whether the reference clock pulse frequency dividing multiple u (j) of 16 bit timing device value is equal to 1000, if u (j)= 1000, then into step s122, otherwise return to step s110；

s122：The reference clock pulse frequency dividing multiple u (j) of 16 bit timing device value is set to be equal to 0, into step s123；

s123：Read 16 bit timing currencys of the 16 bit timing device and add 1, be as a result stored in the bit timing of 16 bit timing device 16 Currency memory cell, into step s124；

s124：Judge whether the timing value of the 16 bit timing device produces spilling, enter step s125 if spilling is produced, otherwise Return to step s110；

s125：Reload 16 Bit Time Parameters of the 16 bit timing device, return to step s110；

s126：The coding of the frequency dividing multiple of the 32 bit timing device is judged, if frequency dividing multiple is encoded to F2F1=00, into step Rapid s130；If frequency dividing multiple is encoded to F2F1=01, into step s127；If frequency dividing multiple be encoded to F2F1= 10, then into step s128；If frequency dividing multiple is encoded to F2F1=10, into step s129；

s127:Judge whether the reference clock pulse frequency dividing multiple u (j) of 32 bit timing device value is equal to 10, if u (j)= 10, then into step s130, otherwise return to step s117；

s128:Judge whether the reference clock pulse frequency dividing multiple u (j) of 32 bit timing device value is equal to 100, if u (j)= 100, then into step s130, otherwise return to step s117；

s129:Judge whether the reference clock pulse frequency dividing multiple u (j) of 32 bit timing device value is equal to 1000, if u (j) =1000, then into step s130, otherwise return to step s117；

s130:The reference clock pulse frequency dividing multiple u (j) of 32 bit timing device value is set to be equal to 0, into step s131；

s131：Read 32 bit timing currencys of the 32 bit timing device and add 1, be as a result stored in 32 of the 32 bit timing device it is fixed When currency memory cell, into step s132；

s132:Judge whether the timing value of the 32 bit timing device produces spilling, it is no into step s133 if spilling is produced Then return to step s117；

s133：Reload 32 Bit Time Parameters of the 32 bit timing device, return to step s117.