CN204790973U

CN204790973U - Counter IP kernel of being connected with 8 microprocessor application system

Info

Publication number: CN204790973U
Application number: CN201520463374.7U
Authority: CN
Inventors: 柯宝中; 侯丽; 蔡启仲; 潘绍明
Original assignee: Guangxi University of Science and Technology
Current assignee: Guangxi University of Science and Technology
Priority date: 2015-06-30
Filing date: 2015-06-30
Publication date: 2015-11-18
Anticipated expiration: 2025-06-30

Abstract

The utility model provides a counter IP kernel of being connected with 8 microprocessor application system, includes that data input output and command word decompose storage control module, and control module is handled to 12 frequency dividers of pulse, count, and counter overflow indicator control module selects control module with the input gate, the utility model discloses use the hard connection control circuit of FPGA design counter IP kernel, the counter IP kernel has 14 16 digit counters, wherein can constitute 6 32 digit counters for 12, and a command word sets up mode, the parameter setting of filtering reference clock pulse multiple, another command word control operating condition, the utility model discloses except that 8 microprocessor carried out function and state setting, count parameter transmission, read to count the operation of current value the counter, every 16/32 digit counter still had the automatic count parameter function of reloading, does not occupy 8 microprocessor procedure execution time, the demand that can satisfy the numerous rolling counters forwards of quantity and count control system.

Description

A kind of counter IP kernel be connected with 8-bit microprocessor application system

Technical field

The utility model relates to a kind of counter IP kernel be connected with 8-bit microprocessor application system, particularly relate to a kind of feature based on FPGA parallel processing, application FPGA designs the counter IP kernel that can be connected with 8-bit microprocessor application system of Hard link circuit composition.

Background technology

Need to apply in the 8-bit microprocessor application system of numerous counter at extensive tally control or other, a large amount of counters will be used, extension counter number has three kinds of implementations: first kind of way is that the count value of the counter applied in microprocessor is as reference count value, counting interrupt mode is adopted to programme, times number variable of reference count value is set, this count value times number variable is also the marking variable of extension counter, programmed method mainly contains 2 kinds, 1st kind of method performs a start-stop counter break in service function count value times number variable to add 1, and compare with the multiple value of the reference count value arranged, if count value times number variable has reached the multiple value of the reference count value of setting, to count value times number variable clear 0, then the program that this extension counter count value is overflowed is performed, or the marking variable of an extension counter is set specially, when count value times number variable has reached the multiple value of reference count value of setting, to count value times number variable clear 0, put the marking variable of 1 counter, whether the marking variable judging this counter in the program of principal function is " 1 ", if so, then the marking variable of clear 0 this counter, performs once the process function that this extension counter count value is overflowed, the second way is that microprocessor is connected with counter extension chip, and current counter chip mainly contains 82C54, can expand 3 16 digit counters,

There is following weak point in above two kinds of implementations:

1. apply the counting interrupt method of reference counter, CPU responds and exits reference counter interrupt service routine and takies CPU working time; Reference count value is less, and counter system needs the counter of expansion more, will take CPU longer for working time, and produce serious influence to the execution speed of other program module;

2. the second way adopts microprocessor to extend out private counter chip, and required counter is more, extends out private counter chip more, and the circuit scale of 8-bit microprocessor application system is larger;

The third mode adopts non-programmable hardware counting, the independently hardware circuit realization of its each counter; Adopt and realize tally function in this way, required counter is more, and circuit scale is larger, and maintenance workload is large.

Summary of the invention

The purpose of this utility model is the parallel processing function fully applying FPGA, a kind of counter IP kernel be connected with 8-bit microprocessor application system based on FPGA is provided, there are 14 16 digit counters counter IP kernel inside, 12 16 digit counters can be applied and be set to 6 32 digit counters, each 16 digit counters or 32 digit counters can export counting spill over, can programme and the work of gate-control signal control counter is set, the mode of operation of counter, select four kinds of filtering parameters counting input pulse, this counter IP kernel only needs the working operating mode of two each counters of command set through initialization programming, when each counter overflows, can automatic reloading count parameter, counting process does not take the time that 8-bit microprocessor program performs, the advantage such as counting and tally control quantity being reached to 14 16 digit counters or 6 32 digit counters can be realized, to overcome the deficiency existing for existing counting mode actualizing technology.

For solving the problems of the technologies described above, the technical scheme that the utility model is taked is: a kind of counter IP kernel be connected with 8-bit microprocessor application system, it is characterized in that: this counter IP kernel comprises data input and output and command word decomposes storage control module, pulse 12 frequency divider, counting processing and control module, counter overflow mark control module, input gate selects control module;

Described data input and output and command word decompose storage control module with 8-bit microprocessor application system, count processing and control module, counter overflow mark control module and input gate and select control module to be connected;

Described pulse 12 frequency divider is also with 8-bit microprocessor application system with count processing and control module and be connected;

Described counting processing and control module is also with 8-bit microprocessor application system, counter overflow mark control module with input gate and select control module to be connected;

Described data input and output and command word decompose storage control module under the chip selection signal inputted is low level condition, if write signal is effective, the address of the counter given according to 8-bit microprocessor application system or counter command word, obtain the mode of operation frequency division multiple coded command word that counter runs, STATUS control commands word, the count parameter of 16 digit counters or 32 digit counters, and according to count parameter, counter is numbered, mode of operation frequency division times number encoder and state control stored respectively and export, also export and write mode of operation frequency division multiple coded command word signal, write STATUS control commands word signal and write counter parameter signal, if read signal is effectively to 8-bit microprocessor application system transmission counter real-time counting value,

Described pulse 12 frequency divider carries out frequency division to the time clock of 8-bit microprocessor application system, and it exports the filtering reference clock pulse of the rolling counters forward control operation as counting processing and control module;

Described counting processing and control module, under the effect writing mode of operation frequency division multiple coded command word signal, stores the mode of operation of this counter, the encoded radio of filtering reference clock frequency division multiple according to counter numbering, under the effect writing STATUS control commands word signal, store the state control signal of this counter according to counter numbering, under the effect writing counter parameter signal, store the count parameter of this counter according to counter numbering, described counting processing and control module is under the counting processing controls of counter IP kernel outside input runs the effect of time clock CLK II, control the operation of counting processing and control module, the filtering reference clock pulse cycle exported according to pulse 12 frequency divider completes all single treatments having started counter, comprise the state control treatment of each counter, the judgement process of mode of operation, when the number of filtering reference clock reaches the filtering reference clock multiple value set by 16/32 digit counters, the counting input signal of this counter is read in from counter IP kernel outside, carry out a filtering process, if judge it is once count pulse effectively, then 1 operation is added to the real-time counting parameter value of this counter, when producing spilling, to the automatic heavy cartridges count parameter of real-time counting parameter value, and export overflow indicator signal, under in data input and output and command word, to decompose chip selection signal that storage control module inputs be low level condition, if read signal is effective, according to the address of the given counter of 8-bit microprocessor application system, the real-time counting parameter value of direct this counter of reading decomposes through data input and output and command word the data bus that storage control module is transferred to 8-bit microprocessor application system, the real-time counting parameter of 16 digit counters needs timesharing to be read for twice, and the real-time counting parameter of 32 digit counters needs timesharing to be read for four times, under the reset signal effect that 8-bit microprocessor application system exports, stop the counting operation of all counters,

The high level that described counter overflow mark control module exports 16/32 digit counters is effective spill over; When the spill over of 16 digit counters that counting processing and control module exports is transformed to high level by low level, stores this counter overflow and be masked as high level; If this counter overflow is masked as high level, clear overflow indicator is converted to low level by high level, stores this counter overflow and is masked as low level; Under the effect writing mode of operation frequency division multiple coded command word signal, counter overflow mark control module stores the information of 32 digit counter mode of operations according to register number, and the flooding information blocking low 16 of this 32 digit counter remains low level;

Described input gate selects control module writing under mode of operation frequency division multiple coded command word signal function, the mode of operation of this counter is stored according to counter numbering, according to the gate level that the determined gate control function of this counter works pattern requires and inputs, the gate-control signal that control inputs gate selects control module to export.

Its further technical scheme is: described data input and output and command word are decomposed storage control module and comprised 8 bi-directional data strobe triple gate groups, read-write control module, count parameter register, counter numbered register, mode of operation filtering code register, mode control register;

Described 8 bi-directional data strobe triple gate groups respectively with 8-bit microprocessor application system, read-write control module, count parameter register, counter numbered register, mode of operation filtering code register, mode control register is connected with counting processing and control module;

Described read-write control module also with 8-bit microprocessor application system, count parameter register, counter numbered register, mode of operation filtering code register, mode control register, counting processing and control module, counter overflow mark control module select control module to be connected with input gate;

Described count parameter register is also connected with counting processing and control module;

Described counter numbered register also with 8-bit microprocessor application system, count processing and control module, counter overflow mark control module and input gate and select control module to be connected;

Described mode of operation filtering code register also with 8-bit microprocessor application system, count processing and control module, counter overflow mark control module and input gate and select control module to be connected;

Described mode control register also with 8-bit microprocessor application system, count processing and control module sum counter overflow indicator control module and be connected;

Described data input and output and command word decompose the read-write control module of storage control module under chip selection signal is low level condition, if write signal is effective, send 8 bi-directional data strobe triple gate group write signals, the data input of gating 8-bit microprocessor application system data bus; Counter numbering signal is write in generation, and judge the address value that 8-bit microprocessor application system address bus inputs, if the address value of counter parameter, by this address value write counter numbered register, counter parameter signal is write in generation, by 8 bit data write count parameter registers of data bus; If counter command word address, by the 2nd of data bus the ~ the 5th bit data write counter numbered register, command word address is 0EH or 0FH, and arranging the 3rd digit counter number value S3 is 0, otherwise is set to 1; If command word least-significant byte address, then command word is mode of operation frequency division multiple coded command word, mode of operation frequency division multiple coded command word signal is write in generation, by the 0th of data bus the, the 1st, the 6th and the 7th write mode of operation frequency division multiple code registers; If command word most-significant byte address, then command word is STATUS control commands word, produces and writes STATUS control commands word signal, by the 0th of data bus the, the 1st and the 7th write state control register; If read signal is effective, send 8 bi-directional data strobe triple gate group read signals, the data of inner for the counter IP kernel of counting processing and control module output data bus are transferred to the data bus of 8-bit microprocessor application system.

Its further technical scheme be: described counting processing and control module comprises rolling counters forward control operation module, address strobe controls I, 8 count parameter dual-ported memories, address strobe controls II, 8 counting real-time parameter dual-ported memories, and address strobe controls III, 4 mode of operation frequency division times number encoder dual-ported memories, address strobe controls IV, 3 states and controls dual-ported memory, 4 counting filtering parameter shift memories;

Described rolling counters forward control operation module respectively with pulse 12 frequency divider, counter overflow mark control module, input gate selects control module, address strobe controls I, 8 count parameter dual-ported memories, address strobe controls II, 8 counting real-time parameter dual-ported memories, address strobe controls III, 4 mode of operation frequency division times number encoder dual-ported memories, address strobe controls IV, 3 states control dual-ported memory, 4 counting filtering parameter shift memories, the counting input signal of counter IP kernel outside input runs time clock CLK II with counting processing controls and is connected,

Described address strobe control I also decomposes storage control module with data input and output and command word and 8 count parameter dual-ported memories are connected;

Described 8 count parameter dual-ported memories also decompose storage control module and 8 and count real-time parameter dual-ported memory and be connected with data input and output and command word;

Described address strobe controls II and also decomposes storage control module and 8 with 8-bit microprocessor application system, data input and output and command word and count real-time parameter dual-ported memory and be connected;

Described 8 counting real-time parameter dual-ported memories also decompose storage control module with data input and output and command word and are connected;

Described address strobe control III also decomposes storage control module with data input and output and command word and 4 mode of operation frequency division times number encoder dual-ported memories are connected;

Described 4 mode of operation frequency divisions times number encoder dual-ported memory also decomposes storage control module with data input and output and command word and is connected;

Described address strobe controls IV and also decomposes storage control module and 3 states with data input and output and command word and control dual-ported memory and be connected;

Described 3 states control dual-ported memory also decomposes storage control module with data input and output and command word, the reset signal of 8-bit microprocessor application system is connected; If the reset signal of input is effective reset signal, 3 states that reset control dual-ported memory, stop the counting of all counters.

Its more further technical scheme be: described counter overflow mark control module comprises not gate, M0 mode of operation bit register group, overflow quenching pulse controller, Sheffer stroke gate I, d type flip flop I, with door I, Sheffer stroke gate II, d type flip flop II, Sheffer stroke gate III, d type flip flop III, with door II, Sheffer stroke gate IV, d type flip flop IV, Sheffer stroke gate V, d type flip flop V, with door III, Sheffer stroke gate VI, d type flip flop VI, Sheffer stroke gate VII, d type flip flop VII, Sheffer stroke gate VIII, d type flip flop VIII, with door IV, Sheffer stroke gate Ⅸ, d type flip flop Ⅸ, Sheffer stroke gate Ⅹ, d type flip flop Ⅹ, with door V, Sheffer stroke gate Ⅺ, d type flip flop Ⅺ, Sheffer stroke gate Ⅻ, d type flip flop Ⅻ, with door VI, Sheffer stroke gate Ⅹ III, d type flip flop Ⅹ III, Sheffer stroke gate Ⅹ IV, d type flip flop Ⅹ IV,

The M0 output terminal that input end and data input and output and the command word of described not gate decompose the mode control register of storage control module is connected, and output terminal is connected with an input end of M0 mode of operation bit register group;

The counter numbering output terminal writing mode of operation filtering code command word signal output part sum counter numbered register that another three input ends of M0 mode of operation bit register group decompose the read-write control module of storage control module with the reset signal output terminal of 8-bit microprocessor application system, data input and output with command word is respectively connected, and output terminal is respectively with door I, with door II, with door III, with door IV, with door V, be connected with an input end of door VI;

What three input ends overflowing quenching pulse controller decomposed the read-write control module of storage control module respectively with data input and output and command word writes STATUS control commands word signal output part, the counter numbering output terminal of the clear overflow indicator output terminal sum counter numbered register of mode control register connects, output terminal is Sheffer stroke gate I respectively, Sheffer stroke gate II, Sheffer stroke gate III, Sheffer stroke gate IV, Sheffer stroke gate V, Sheffer stroke gate VI, Sheffer stroke gate VII, Sheffer stroke gate VIII, Sheffer stroke gate Ⅸ, Sheffer stroke gate Ⅹ, Sheffer stroke gate Ⅺ, Sheffer stroke gate Ⅻ, Sheffer stroke gate Ⅹ III, an input end of Sheffer stroke gate Ⅹ IV connects, output terminal is also connected with the data input pin of d type flip flop I, d type flip flop II, d type flip flop III, d type flip flop IV, d type flip flop V, d type flip flop VI, d type flip flop VII, d type flip flop VIII, d type flip flop Ⅸ, d type flip flop Ⅹ, d type flip flop Ⅺ, d type flip flop Ⅻ, d type flip flop Ⅹ III and d type flip flop Ⅹ IV,

Another input end of Sheffer stroke gate I is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop I;

The data output end of d type flip flop I and being connected with another input end of door I;

To output signal as the overflow indicator of 16 digit counters 0 with the output terminal of door I and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate II is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop II;

The data output end of d type flip flop II is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 digit counter 1/32 digit counters 0;

Another input end of Sheffer stroke gate III is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop III;

The data output end of d type flip flop III and being connected with another input end of door II;

To output signal as the overflow indicator of 16 digit counters 2 with the output terminal of door II and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate IV is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop IV;

The data output end of d type flip flop IV is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 digit counter 3/32 digit counters 1;

Another input end of Sheffer stroke gate V is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop V;

The data output end of d type flip flop V and being connected with another input end of door III;

To output signal as the overflow indicator of 16 digit counters 4 with the output terminal of door III and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate VI is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop VI;

The data output end of d type flip flop VI is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 digit counter 5/32 digit counters 2;

Another input end of Sheffer stroke gate VII is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop VII;

The data output end of d type flip flop VII is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 digit counters 6;

Another input end of Sheffer stroke gate VIII is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop VIII;

The data output end of d type flip flop VIII and being connected with another input end of door IV;

To output signal as the overflow indicator of 16 digit counters 7 with the output terminal of door IV and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate Ⅸ is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅸ;

The data output end of d type flip flop Ⅸ is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 digit counter 8/32 digit counters 3;

Another input end of Sheffer stroke gate Ⅹ is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ;

The data output end of d type flip flop Ⅹ and being connected with another input end of door V;

To output signal as the overflow indicator of 16 digit counters 9 with the output terminal of door V and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate Ⅺ is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅺ;

The data output end of d type flip flop Ⅺ is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 digit counter 10/32 digit counters 4;

Another input end of Sheffer stroke gate Ⅻ is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅻ;

The data output end of d type flip flop Ⅻ and being connected with an input end of door VI;

To output signal as the overflow indicator of 16 digit counters 11 with the output terminal of door VI and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate Ⅹ III is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ III;

The data output end of d type flip flop Ⅹ III is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 digit counter 12/32 digit counters 5;

Another input end of Sheffer stroke gate Ⅹ IV is connected with the overflow indicator output terminal of counting processing and control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ IV;

The data output end of d type flip flop Ⅹ IV is connected with 8-bit microprocessor application system as 16 digit counter 13 overflow indicator output signal output terminals.

Owing to adopting above structure, the counter IP kernel that a kind of and 8-bit microprocessor application system of the utility model is connected has following beneficial effect:

1. be connected with 8-bit microprocessor application system, programming Control is convenient

Counter IP kernel of the present utility model can directly be connected with 8-bit microprocessor application system, when function setting is carried out to each counter in counter IP kernel, 8-bit microprocessor only needs to send to counter IP kernel the mode of operation that 1 command word can determine this counter, the filtering parameter of counting filtering reference clock pulse; Send the Counts that another command word starts this counter, and whether this counter clear overflow indicator and whether count currency clearly; For 16 digit counters, time sharing transmissions most-significant byte and least-significant byte count parameter; For 32 digit counters, point four transmission, 32 count parameter; 8-bit microprocessor directly can also read the real-time counting value of this counter according to the address of counter, programming Control counter is convenient.

2. be applicable to the system requirements of One's name is legion rolling counters forward and tally control

There are 14 16 digit counters counter IP kernel inside of the present utility model, 2 16 digit counters can be formed 32 digit counters by the setting command word that needs according to counting application, composition 6 32 digit counters can be set, the filtering parameter of selection four kinds counting filtering reference clock pulse can also be set; When counting produces counting spill over, counter IP kernel of the present utility model can automatic reloading count parameter, can meet the system requirements of One's name is legion rolling counters forward and tally control.

3.FPGA parallel processing counts, and counter IP kernel cost performance is high

The utility model except 8-bit microprocessor function setting, count parameter transmission are carried out to counter, software counts overflow indicator clearly, reads counting currency, and outside the operation needing clear counting currency, will not take the program execution time of 8-bit microprocessor; The counter IP kernel of application FPGA design Hard link circuit composition can reconstruct and become 7 16 digit counters, can arrange composition 3 32 digit counters; A kind of counter IP kernel be connected with 8-bit microprocessor application system of the present utility model can select four kinds of filtering parameters counting filtering reference clock pulse, realize the filtering to counting input pulse, automatic reloading count parameter, the time that the program taking 8-bit microprocessor performs greatly reduces, use it for the system of exploitation One's name is legion rolling counters forward and tally control, very high cost performance can be obtained.

Be further described below in conjunction with the technical characteristic of drawings and Examples to the counter IP kernel that a kind of of the utility model is connected with 8-bit microprocessor application system.

Accompanying drawing explanation

Fig. 1: the circuit structure block diagram of the counter IP kernel that a kind of and 8-bit microprocessor application system of the utility model is connected;

Fig. 2: the encapsulation figure of the counter IP kernel that a kind of and 8-bit microprocessor application system of the utility model embodiment one is connected;

Fig. 3: the data input and output of the counter IP kernel that a kind of and 8-bit microprocessor application system of the utility model embodiment one is connected and command word decompose the circuit block diagram of storage control module;

Fig. 4: the circuit block diagram of the counting processing and control module of the counter IP kernel that a kind of and 8-bit microprocessor application system of the utility model embodiment one is connected;

Fig. 5: the circuit block diagram of the counter overflow mark control module of the counter IP kernel that a kind of and 8-bit microprocessor application system of the utility model embodiment one is connected;

Fig. 6: the encapsulation figure of the counter IP kernel that a kind of and 8-bit microprocessor application system of the utility model embodiment two is connected;

Fig. 7: the data input and output of the counter IP kernel that a kind of and 8-bit microprocessor application system of the utility model embodiment two is connected and command word decompose the circuit block diagram of storage control module;

Fig. 8: the circuit block diagram of the counter overflow mark control module of the counter IP kernel that a kind of and 8-bit microprocessor application system of the utility model embodiment two is connected.

In figure:

I-8-bit microprocessor application system, the input and output of II-data and command word decompose storage control module, III-pulse 12 frequency divider, IV-counting processing and control module, V-counter overflow mark control module, and VI-input gate selects control module;

1-8 bi-directional data strobe triple gate groups, 2-read-write control module, 3-count parameter register, 4-counter numbered register, 5-mode of operation filtering code register, 6-mode control register, 7-not gate, 8-M0 mode of operation bit register group, 9-overflow quenching pulse controller, 10-Sheffer stroke gate I, 11-d type flip flop I, 12-with door I, 13-Sheffer stroke gate II, 14-d type flip flop II, 15-Sheffer stroke gate III, 16-d type flip flop III, 17-with door II, 18-Sheffer stroke gate IV, 19-d type flip flop IV, 20-Sheffer stroke gate V, 21-d type flip flop V, 22-with door III, 23-Sheffer stroke gate VI, 24-d type flip flop VI, 25-Sheffer stroke gate VII, 26-d type flip flop VII, 27-Sheffer stroke gate VIII, 28-d type flip flop VIII, 29-with door IV, 30-Sheffer stroke gate Ⅸ, 31-d type flip flop Ⅸ, 32-Sheffer stroke gate Ⅹ, 33-d type flip flop Ⅹ, 34-with door V, 35-Sheffer stroke gate Ⅺ, 36-d type flip flop Ⅺ, 37-Sheffer stroke gate Ⅻ, 38-d type flip flop Ⅻ, 39-with door VI, 40-Sheffer stroke gate Ⅹ III, 41-d type flip flop Ⅹ III, 42-Sheffer stroke gate Ⅹ IV, 43-d type flip flop Ⅹ IV, 44-rolling counters forward control operation module, 45-address strobe controls I, 46-8 count parameter dual-ported memories, 47-address strobe controls II, 48-8 counting real-time parameter dual-ported memories, 49-address strobe controls III, 50-4 mode of operation frequency division times number encoder dual-ported memories, 51-address strobe controls IV, 52-3 states control dual-ported memory, 53-4 counting filtering parameter shift memories.

In literary composition, abbreviation illustrates:

FPGA-FieldProgrammableGateArray, field programmable gate array;

RD-Read signal, read signal;

CS-ChipSelect signal, chip selection signal;

WR-Write, write signal;

RST-Reset, reset signal;

AB-AddressBus, address bus;

DB-DataBus, data bus;

CLK-Clockpulse, time clock;

TF-count value overflow indicator outputs signal;

GATE-gate input signal;

M0-16/32 digit counter is encoded, and M0 is " 0 ", 16 digit counters; M0 is " 1 ", 32 digit counters;

M1-gate mode is encoded, and M1 is " 0 ", without gate input signal control counter; M1 is " 1 ", gate input signal control counter;

The inner input data bus of DB_1-counter IP kernel;

The inner output data bus of DB_2-counter IP kernel;

RD_1-8 position bi-directional data strobe triple gate group read signal;

RD_2-real-time counting value read signal;

WR_1-8 position bi-directional data strobe triple gate group write signal;

WR_2-writes mode of operation filtering code command word signal;

WR_3-writes STATUS control commands word signal;

WR_4-writes counter parameter signal;

WR_5-writes counter numbering signal;

CLK I-time clock;

The processing controls of CLK II-counting runs time clock;

The counting input signal of 14 16 digit counters of C0 ~ C13-counter IP kernel, wherein the counting input signal of corresponding 32 digit counters 0 ~ 5 of C0, C2, C4, C7, C9, C11 difference;

S0, S1, S2-the 0th, the 1st, the 2nd digit counter number value;

S3-the 3rd digit counter number value;

The gate input signal of GATE0 ~ 13-16 digit counter 0 ~ 13, wherein the gate input signal of corresponding 32 digit counters 0 ~ 5 of GATE1, GATE3, GATE5, GATE8, GATE10, GATE12 difference;

The count value overflow indicator output signal of TF0 ~ 13-16 digit counter 0 ~ 13, wherein the count value overflow indicator output signal of corresponding 32 digit counters 0 ~ 5 of TF1, TF3, TF5, TF8, TF10, TF12 difference;

D type flip flop-Dataflip-flop;

D-Datainput, d type flip flop data input pin;

Q-Dataoutput, d type flip flop data output end;

CP-ClockPulseinput, clock signal input terminal.

Embodiment

A kind of counter IP kernel be connected with 8-bit microprocessor application system:

As shown in Figure 1, this counter IP kernel comprises data input and output and command word decomposes storage control module II, pulse 12 frequency divider III, counting processing and control module IV, counter overflow mark control module V, and input gate selects control module VI;

Described data input and output and command word decompose storage control module II with 8-bit microprocessor application system I, count processing and control module IV, counter overflow mark control module V and input gate and select control module VI to be connected;

Described pulse 12 frequency divider III is also with 8-bit microprocessor application system I with count processing and control module IV and be connected;

Described counting processing and control module IV is also with 8-bit microprocessor application system I, counter overflow mark control module V with input gate and select control module VI to be connected;

Described data input and output and command word decompose storage control module II under the chip selection signal inputted is low level condition, if write signal is effective, the address of the counter given according to 8-bit microprocessor application system I or counter command word, obtain the mode of operation frequency division multiple coded command word that counter runs, STATUS control commands word, the count parameter of 16 digit counters or 32 digit counters, and according to count parameter, counter is numbered, mode of operation frequency division times number encoder and state control stored respectively and export, also export and write mode of operation frequency division multiple coded command word signal, write STATUS control commands word signal and write counter parameter signal, if read signal effectively transmits counter real-time counting value to 8-bit microprocessor application system I,

The time clock of described pulse 12 frequency divider III pair of 8-bit microprocessor application system I carries out frequency division, and it exports the filtering reference clock pulse of the rolling counters forward control operation as counting processing and control module IV;

Described counting processing and control module IV, under the effect writing mode of operation frequency division multiple coded command word signal, stores the mode of operation of this counter, the encoded radio of filtering reference clock frequency division multiple according to counter numbering, under the effect writing STATUS control commands word signal, store the state control signal of this counter according to counter numbering, under the effect writing counter parameter signal, store the count parameter of this counter according to counter numbering, described counting processing and control module IV is under the counting processing controls of counter IP kernel outside input runs the effect of time clock CLK II, control the operation of counting processing and control module IV, the filtering reference clock pulse cycle exported according to pulse 12 frequency divider III completes all single treatments having started counter, comprise the state control treatment of each counter, the judgement process of mode of operation, when the number of filtering reference clock reaches the filtering reference clock multiple value set by 16/32 digit counters, the counting input signal of this counter is read in from counter IP kernel outside, carry out a filtering process, if judge it is once count pulse effectively, then 1 operation is added to the real-time counting parameter value of this counter, when producing spilling, to the automatic heavy cartridges count parameter of real-time counting parameter value, and export overflow indicator signal, under in data input and output and command word, to decompose chip selection signal that storage control module II inputs be low level condition, if read signal is effective, according to the address of the given counter of 8-bit microprocessor application system I, the real-time counting parameter value of direct this counter of reading decomposes through data input and output and command word the data bus that storage control module II is transferred to 8-bit microprocessor application system I, the real-time counting parameter of 16 digit counters needs timesharing to be read for twice, and the real-time counting parameter of 32 digit counters needs timesharing to be read for four times, under the reset signal effect that 8-bit microprocessor application system I exports, stop the counting operation of all counters,

The high level that described counter overflow mark control module V exports 16/32 digit counters is effective spill over; When the spill over of 16 digit counters that counting processing and control module IV exports is transformed to high level by low level, stores this counter overflow and be masked as high level; If this counter overflow is masked as high level, clear overflow indicator is converted to low level by high level, stores this counter overflow and is masked as low level; Under the effect writing mode of operation frequency division multiple coded command word signal, counter overflow mark control module V stores the information of 32 digit counter mode of operations according to register number, and the flooding information blocking low 16 of this 32 digit counter remains low level;

Described input gate selects control module VI writing under mode of operation frequency division multiple coded command word signal function, the mode of operation of this counter is stored according to counter numbering, according to the gate level that the determined gate control function of this counter works pattern requires and inputs, the gate-control signal that control inputs gate selects control module VI to export.

In order to the system requirements of applicable One's name is legion rolling counters forward and tally control, according to the needs of different countings application, the counter IP kernel of the figure place that setting command word encapsulation composition is different, therefore, there are following several embodiments: such as 2 16 digit counters can be formed 32 digit counters, composition 6 32 digit counters can be set at most, frequency division multiple of selection four kinds of baseline time clock etc. can also be set; Below be described below.

Embodiment one:

A kind of counter IP kernel A(be connected with 8-bit microprocessor application system that composition 6 32 digit counters can be set hereinafter referred to as: counter IP kernel A):

As mentioned above, as shown in Figure 1, this counter IP kernel A comprises data input and output and command word decomposes storage control module II, pulse 12 frequency divider III, counting processing and control module IV, counter overflow mark control module V, and input gate selects control module VI; This counter IP kernel A has 48 pins, and figure is see Fig. 2 in its encapsulation;

As shown in Figure 3, described data input and output and command word are decomposed storage control module II and are comprised 8 bi-directional data strobe triple gate groups 1, read-write control module 2, count parameter register 3, counter numbered register 4, mode of operation filtering code register 5, mode control register 6;

Described 8 bi-directional data strobe triple gate groups 1 respectively with 8-bit microprocessor application system I, read-write control module 2, count parameter register 3, counter numbered register 4, mode of operation filtering code register 5, mode control register 6 is connected with counting processing and control module IV;

Described read-write control module 2 also with 8-bit microprocessor application system I, count parameter register 3, counter numbered register 4, mode of operation filtering code register 5, mode control register 6, counting processing and control module IV, counter overflow mark control module V select control module VI to be connected with input gate;

Described count parameter register 3 is also connected with counting processing and control module IV;

Described counter numbered register 4 also with 8-bit microprocessor application system I, count processing and control module IV, counter overflow mark control module V and input gate and select control module VI to be connected;

Described mode of operation filtering code register 5 also with 8-bit microprocessor application system I, count processing and control module IV, counter overflow mark control module V and input gate and select control module VI to be connected;

Described mode control register 6 also with 8-bit microprocessor application system I, count processing and control module IV sum counter overflow indicator control module V and be connected;

Described data input and output and command word decompose the read-write control module 2 of storage control module II under chip selection signal is low level condition, if write signal is effective, send 8 bi-directional data strobe triple gate group 1 write signals, the data input of gating 8-bit microprocessor application system I data bus; Counter numbering signal is write in generation, and judge the address value that 8-bit microprocessor application system I address bus inputs, if the address value of counter parameter, by this address value write counter numbered register 4, counter parameter signal is write in generation, by 8 bit data write count parameter registers 3 of data bus; If counter command word address, by the 2nd of data bus the ~ the 5th bit data write counter numbered register 4, command word address is 0EH or 0FH, and arranging the 3rd digit counter number value S3 is 0, otherwise is set to 1; If command word least-significant byte address, then command word is mode of operation frequency division multiple coded command word, mode of operation frequency division multiple coded command word signal is write in generation, by the 0th of data bus the, the 1st, the 6th and the 7th write mode of operation frequency division multiple code registers 5; If command word most-significant byte address, then command word is STATUS control commands word, produces and writes STATUS control commands word signal, by the 0th of data bus the, the 1st and the 7th write state control register 6; If read signal is effective, send 8 bi-directional data strobe triple gate group 1 read signals, the data of inner for the counter IP kernel of counting processing and control module IV output data bus are transferred to the data bus of 8-bit microprocessor application system I.

As shown in Figure 4, described counting processing and control module IV comprises rolling counters forward control operation module 44, address strobe controls I 45,8 count parameter dual-ported memories 46, and address strobe controls II 47,8 counting real-time parameter dual-ported memories 48, address strobe controls III 49,4 mode of operation frequency division times number encoder dual-ported memories 50, and address strobe controls IV 51,3 states control dual-ported memory 52,4 counting filtering parameter shift memory 53;

Described rolling counters forward control operation module 44 respectively with pulse 12 frequency divider III, counter overflow mark control module V, input gate selects control module VI, address strobe controls I 45, 8 count parameter dual-ported memories 46, address strobe controls II 47, 8 counting real-time parameter dual-ported memories 48, address strobe controls III 49, 4 mode of operation frequency division times number encoder dual-ported memories 50, address strobe controls IV 51, 3 states control dual-ported memory 52, 4 counting filtering parameter shift memories 53, the counting input signal of counter IP kernel outside input runs time clock CLK II with counting processing controls and is connected,

Described address strobe control I 45 also decomposes storage control module II with data input and output and command word and 8 count parameter dual-ported memories 46 are connected;

Described 8 count parameter dual-ported memories 46 also decompose storage control module II and 8 and count real-time parameter dual-ported memory 48 and be connected with data input and output and command word;

Described address strobe controls II 47 and also decomposes storage control module II and 8 with 8-bit microprocessor application system I, data input and output and command word and count real-time parameter dual-ported memory 48 and be connected;

Described 8 counting real-time parameter dual-ported memories 48 also decompose storage control module II with data input and output and command word and are connected;

Described address strobe control III 49 also decomposes storage control module II with data input and output and command word and 4 mode of operation frequency division times number encoder dual-ported memories 50 are connected;

Described 4 mode of operation frequency divisions times number encoder dual-ported memory 50 also decomposes storage control module II with data input and output and command word and is connected;

Described address strobe controls IV 51 and also decomposes storage control module II and 3 states with data input and output and command word and control dual-ported memory 52 and be connected;

Described 3 states control dual-ported memory 52 also decomposes storage control module II with data input and output and command word, the reset signal of 8-bit microprocessor application system I is connected; If the reset signal of input is effective reset signal, 3 states that reset control dual-ported memory 52, stop the counting of all counters.

As shown in Figure 5, described counter overflow mark control module V comprises not gate 7, M0 mode of operation bit register group 8, overflow quenching pulse controller 9, Sheffer stroke gate I 10, d type flip flop I 11, with door I 12, Sheffer stroke gate II 13, d type flip flop II 14, Sheffer stroke gate III 15, d type flip flop III 16, with door II 17, Sheffer stroke gate IV 18, d type flip flop IV 19, Sheffer stroke gate V 20, d type flip flop V 21, with door III 22, Sheffer stroke gate VI 23, d type flip flop VI 24, Sheffer stroke gate VII 25, d type flip flop VII 26, Sheffer stroke gate VIII 27, d type flip flop VIII 28, with door IV 29, Sheffer stroke gate Ⅸ 30, d type flip flop Ⅸ 31, Sheffer stroke gate Ⅹ 32, d type flip flop Ⅹ 33, with door V 34, Sheffer stroke gate Ⅺ 35, d type flip flop Ⅺ 36, Sheffer stroke gate Ⅻ 37, d type flip flop Ⅻ 38, with door VI 39, Sheffer stroke gate Ⅹ III 40, d type flip flop Ⅹ III 41, Sheffer stroke gate Ⅹ IV 42, d type flip flop Ⅹ IV 43,

The M0 output terminal that input end and data input and output and the command word of described not gate 7 decompose the mode control register 6 of storage control module II is connected, and output terminal is connected with an input end of M0 mode of operation bit register group 8;

The counter numbering output terminal writing mode of operation filtering code command word signal output part sum counter numbered register 4 that another three input ends of M0 mode of operation bit register group 8 decompose the read-write control module 2 of storage control module II with the reset signal output terminal of 8-bit microprocessor application system I, data input and output with command word is respectively connected, and output terminal is respectively with door I 12, with door II 17, with door III 22, with door IV 29, with door V 34, be connected with an input end of door VI 39;

What three input ends overflowing quenching pulse controller 9 decomposed the read-write control module 2 of storage control module II respectively with data input and output and command word writes STATUS control commands word signal output part, the counter numbering output terminal of the clear overflow indicator output terminal sum counter numbered register 4 of mode control register 6 connects, output terminal is Sheffer stroke gate I 10 respectively, Sheffer stroke gate II 13, Sheffer stroke gate III 15, Sheffer stroke gate IV 18, Sheffer stroke gate V 20, Sheffer stroke gate VI 23, Sheffer stroke gate VII 25, Sheffer stroke gate VIII 27, Sheffer stroke gate Ⅸ 30, Sheffer stroke gate Ⅹ 32, Sheffer stroke gate Ⅺ 35, Sheffer stroke gate Ⅻ 37, Sheffer stroke gate Ⅹ III 40, an input end of Sheffer stroke gate Ⅹ IV 42 connects, output terminal is also connected with the data input pin of d type flip flop I 11, d type flip flop II 14, d type flip flop III 16, d type flip flop IV 19, d type flip flop V 21, d type flip flop VI 24, d type flip flop VII 26, d type flip flop VIII 28, d type flip flop Ⅸ 31, d type flip flop Ⅹ 33, d type flip flop Ⅺ 36, d type flip flop Ⅻ 38, d type flip flop Ⅹ III 41 and d type flip flop Ⅹ IV 43,

Another input end of Sheffer stroke gate I 10 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop I 11;

The data output end of d type flip flop I 11 and being connected with another input end of door I 12;

To output signal as the overflow indicator of 16 digit counters 0 with the output terminal of door I 12 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate II 13 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop II 14;

The data output end of d type flip flop II 14 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 digit counter 1/32 digit counters 0;

Another input end of Sheffer stroke gate III 15 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop III 16;

The data output end of d type flip flop III 16 and being connected with another input end of door II 17;

To output signal as the overflow indicator of 16 digit counters 2 with the output terminal of door II 17 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate IV 18 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop IV 19;

The data output end of d type flip flop IV 19 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 digit counter 3/32 digit counters 1;

Another input end of Sheffer stroke gate V 20 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop V 21;

The data output end of d type flip flop V 21 and being connected with another input end of door III 22;

To output signal as the overflow indicator of 16 digit counters 4 with the output terminal of door III 22 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate VI 23 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop VI 24;

The data output end of d type flip flop VI 24 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 digit counter 5/32 digit counters 2;

Another input end of Sheffer stroke gate VII 25 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop VII 26;

The data output end of d type flip flop VII 26 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 digit counters 6;

Another input end of Sheffer stroke gate VIII 27 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop VIII 28;

The data output end of d type flip flop VIII 28 and being connected with another input end of door IV 29;

To output signal as the overflow indicator of 16 digit counters 7 with the output terminal of door IV 29 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate Ⅸ 30 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅸ 31;

The data output end of d type flip flop Ⅸ 31 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 digit counter 8/32 digit counters 3;

Another input end of Sheffer stroke gate Ⅹ 32 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ 33;

The data output end of d type flip flop Ⅹ 33 and being connected with another input end of door V 34;

To output signal as the overflow indicator of 16 digit counters 9 with the output terminal of door V 34 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate Ⅺ 35 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅺ 36;

The data output end of d type flip flop Ⅺ 36 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 digit counter 10/32 digit counters 4;

Another input end of Sheffer stroke gate Ⅻ 37 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅻ 38;

The data output end of d type flip flop Ⅻ 38 and being connected with an input end of door VI 39;

To output signal as the overflow indicator of 16 digit counters 11 with the output terminal of door VI 39 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate Ⅹ III 40 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ III 41;

The data output end of d type flip flop Ⅹ III 41 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 digit counter 12/32 digit counters 5;

Another input end of Sheffer stroke gate Ⅹ IV 42 is connected with the overflow indicator output terminal of counting processing and control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ IV 43;

The data output end of d type flip flop Ⅹ IV 43 is connected with 8-bit microprocessor application system I as 16 digit counter 13 overflow indicator output signal output terminals.

The counter of this counter IP kernel A with command address coding schedule see subordinate list one " counter of the counter IP kernel A be connected with 8-bit microprocessor application system and command address coding schedule "; Mode of operation frequency division multiple coded command word is see subordinate list two " the mode of operation frequency division multiple coded command word complete list of counter IP kernel A "; STATUS control commands word is see subordinate list three " the STATUS control commands word complete list of counter IP kernel A ".

Embodiment two:

The counter IP kernel B be connected with 8-bit microprocessor application system of composition 3 32 digit counters can be set, (hereinafter referred to as: counter IP kernel B):

This counter IP kernel has 7 16 digit counters, and wherein 6 can form 3 32 digit counters; Overflow indicator output signal TF0 ~ 13 of described counter overflow mark control module V are transformed to overflow indicator output signal TF0 ~ 7, described input gate selects gate input signal GATE0 ~ 13 of control module VI to be transformed to gate input signal GATE0 ~ 7, see Fig. 1; The encapsulation figure of the counter IP kernel of Fig. 2 is transformed to the encapsulation figure of the counter IP kernel of Fig. 6, and 62 pins of counter IP kernel are transformed to 42 pins; The connecting line of the 4th digit counter number value S3 and counter numbered register 4 that described data input and output and command word decompose the read-write control module 2 of storage control module II is deleted, see Fig. 7; The circuit block diagram of the counter overflow mark control module V of Fig. 5 is transformed to the circuit block diagram of the counter overflow mark control module V of Fig. 8.

The counter of the counter IP kernel of subordinate list one and command address code pattern are transformed to counter and the command address code pattern of the counter IP kernel of subordinate list four; The D5 position S3 of the mode of operation filtering code command word of subordinate list two is transformed to and retains position (see subordinate list five); The D5 position S3 of the mode of operation filtering code command word of subordinate list three is transformed to and retains position (see subordinate list six).

Embodiment three:

A kind of counter IP kernel be connected with 8-bit microprocessor application system, pulse 12 frequency divider III in Fig. 1 determines the filtering reference clock of each counter input count pulse of counter IP kernel, pulse 12 frequency divider III is transformed to 50 frequency dividers III, and the clock frequency adapting to 8-bit microprocessor is greater than the situation of 12MHz.

Embodiment four:

A kind of counter IP kernel be connected with 8-bit microprocessor application system, pulse 12 frequency divider III in Fig. 1 determines the filtering reference clock of each counter input count pulse of counter IP kernel, pulse 12 frequency divider III is transformed to 100 frequency dividers III, and the clock frequency adapting to 8-bit microprocessor is greater than the situation of 12MHz greatly.

Subordinate list one: embodiment one " counter of the counter IP kernel A be connected with 8-bit microprocessor application system and command address coding schedule "

Subordinate list two: embodiment one " the mode of operation frequency division multiple coded command word complete list of counter IP kernel A ":

Subordinate list three: embodiment one " the STATUS control commands word complete list of counter IP kernel A "

Subordinate list four: embodiment two " counter of the counter IP kernel B be connected with 8-bit microprocessor application system and command address coding schedule "

Subordinate list five: embodiment two " the mode of operation frequency division multiple coded command word complete list of counter IP kernel B "

Subordinate list six: embodiment two " the STATUS control commands word complete list of counter IP kernel B "

Claims

1. the counter IP kernel be connected with 8-bit microprocessor application system, it is characterized in that: this counter IP kernel comprises data input and output and command word decomposes storage control module (II), pulse 12 frequency divider (III), counting processing and control module (IV), counter overflow mark control module (V), input gate selects control module (VI);

Described data input and output and command word decompose storage control module (II) with 8-bit microprocessor application system (I), count processing and control module (IV), counter overflow mark control module (V) and input gate and select control module (VI) to be connected;

Described pulse 12 frequency divider (III) is also with 8-bit microprocessor application system (I) with count processing and control module (IV) and be connected;

Described counting processing and control module (IV) is also with 8-bit microprocessor application system (I), counter overflow mark control module (V) with input gate and select control module (VI) to be connected;

Described data input and output and command word decompose storage control module (II) under the chip selection signal inputted is low level condition, if write signal is effective, the counter given according to 8-bit microprocessor application system (I) or the address of counter command word, obtain the mode of operation frequency division multiple coded command word that counter runs, STATUS control commands word, the count parameter of 16 digit counters or 32 digit counters, and according to count parameter, counter is numbered, mode of operation frequency division times number encoder and state control stored respectively and export, also export and write mode of operation frequency division multiple coded command word signal, write STATUS control commands word signal and write counter parameter signal, if read signal is effectively to 8-bit microprocessor application system (I) transmission counter real-time counting value,

The time clock of described pulse 12 frequency divider (III) to 8-bit microprocessor application system (I) carries out frequency division, and it exports the filtering reference clock pulse of the rolling counters forward control operation as counting processing and control module (IV);

Described counting processing and control module (IV), under the effect writing mode of operation frequency division multiple coded command word signal, stores the mode of operation of this counter, the encoded radio of filtering reference clock frequency division multiple according to counter numbering, under the effect writing STATUS control commands word signal, store the state control signal of this counter according to counter numbering, under the effect writing counter parameter signal, store the count parameter of this counter according to counter numbering, described counting processing and control module (IV) is under the counting processing controls of counter IP kernel outside input runs the effect of time clock CLK II, control the operation of counting processing and control module (IV), the filtering reference clock pulse cycle exported according to pulse 12 frequency divider (III) completes all single treatments having started counter, comprise the state control treatment of each counter, the judgement process of mode of operation, when the number of filtering reference clock reaches the filtering reference clock multiple value set by 16/32 digit counters, the counting input signal of this counter is read in from counter IP kernel outside, carry out a filtering process, if judge it is once count pulse effectively, then 1 operation is added to the real-time counting parameter value of this counter, when producing spilling, to the automatic heavy cartridges count parameter of real-time counting parameter value, and export overflow indicator signal, under in data input and output and command word, to decompose chip selection signal that storage control module (II) inputs be low level condition, if read signal is effective, according to the address of the given counter of 8-bit microprocessor application system (I), the real-time counting parameter value of direct this counter of reading decomposes through data input and output and command word the data bus that storage control module (II) is transferred to 8-bit microprocessor application system (I), the real-time counting parameter of 16 digit counters needs timesharing to be read for twice, the real-time counting parameter of 32 digit counters needs timesharing to be read for four times, under the reset signal effect that 8-bit microprocessor application system (I) exports, stop the counting operation of all counters,

The high level that described counter overflow mark control module (V) exports 16/32 digit counters is effective spill over; When the spill over of 16 digit counters that counting processing and control module (IV) exports is transformed to high level by low level, stores this counter overflow and be masked as high level; If this counter overflow is masked as high level, clear overflow indicator is converted to low level by high level, stores this counter overflow and is masked as low level; Under the effect writing mode of operation frequency division multiple coded command word signal, counter overflow mark control module (V) stores the information of 32 digit counter mode of operations according to register number, and the flooding information blocking low 16 of this 32 digit counter remains low level;

Described input gate selects control module (VI) writing under mode of operation frequency division multiple coded command word signal function, the mode of operation of this counter is stored according to counter numbering, according to the gate level that the determined gate control function of this counter works pattern requires and inputs, the gate-control signal that control inputs gate selects control module (VI) to export.

2. a kind of counter IP kernel be connected with 8-bit microprocessor application system as claimed in claim 1, it is characterized in that: described data input and output and command word are decomposed storage control module (II) and comprised 8 bi-directional data strobe triple gate groups (1), read-write control module (2), count parameter register (3), counter numbered register (4), mode of operation filtering code register (5), mode control register (6);

Described 8 bi-directional data strobe triple gate groups (1) respectively with 8-bit microprocessor application system (I), read-write control module (2), count parameter register (3), counter numbered register (4), mode of operation filtering code register (5), mode control register (6) is connected with counting processing and control module (IV);

Described read-write control module (2) also with 8-bit microprocessor application system (I), count parameter register (3), counter numbered register (4), mode of operation filtering code register (5), mode control register (6), counting processing and control module (IV), counter overflow mark control module (V) select control module (VI) to be connected with input gate;

Described count parameter register (3) is also connected with counting processing and control module (IV);

Described counter numbered register (4) also with 8-bit microprocessor application system (I), count processing and control module (IV), counter overflow mark control module (V) and input gate and select control module (VI) to be connected;

Described mode of operation filtering code register (5) also with 8-bit microprocessor application system (I), count processing and control module (IV), counter overflow mark control module (V) and input gate and select control module (VI) to be connected;

Described mode control register (6) also with 8-bit microprocessor application system (I), count processing and control module (IV) sum counter overflow indicator control module (V) and be connected;

Described data input and output and command word decompose the read-write control module (2) of storage control module (II) under chip selection signal is low level condition, if write signal is effective, send 8 bi-directional data strobe triple gate group (1) write signals, the data input of gating 8-bit microprocessor application system (I) data bus; Counter numbering signal is write in generation, and judge the address value that 8-bit microprocessor application system (I) address bus inputs, if the address value of counter parameter, by this address value write counter numbered register (4), counter parameter signal is write in generation, by 8 bit data write count parameter register (3) of data bus; If counter command word address, by the 2nd of data bus the ~ the 5th bit data write counter numbered register (4), command word address is 0EH or 0FH, and arranging the 3rd digit counter number value S3 is 0, otherwise is set to 1; If command word least-significant byte address, then command word is mode of operation frequency division multiple coded command word, mode of operation frequency division multiple coded command word signal is write in generation, by the 0th of data bus the, the 1st, the 6th and the 7th write mode of operation frequency division multiple code registers (5); If command word most-significant byte address, then command word is STATUS control commands word, produces and writes STATUS control commands word signal, by the 0th of data bus the, the 1st and the 7th write state control register (6); If read signal is effective, send 8 bi-directional data strobe triple gate group (1) read signals, the data of inner for the counter IP kernel counting processing and control module (IV) output data bus are transferred to the data bus of 8-bit microprocessor application system (I).

3. a kind of counter IP kernel be connected with 8-bit microprocessor application system as claimed in claim 2, it is characterized in that: described counting processing and control module (IV) comprises rolling counters forward control operation module (44), address strobe controls I (45), 8 count parameter dual-ported memories (46), address strobe controls II (47), 8 countings real-time parameter dual-ported memory (48), address strobe controls III (49), 4 mode of operation frequency division times number encoder dual-ported memories (50), address strobe controls IV (51), 3 states control dual-ported memory (52), 4 countings filtering parameter shift memory (53),

Described rolling counters forward control operation module (44) respectively with pulse 12 frequency divider (III), counter overflow mark control module (V), input gate selects control module (VI), address strobe controls I (45), 8 count parameter dual-ported memories (46), address strobe controls II (47), 8 countings real-time parameter dual-ported memory (48), address strobe controls III (49), 4 mode of operation frequency division times number encoder dual-ported memories (50), address strobe controls IV (51), 3 states control dual-ported memory (52), 4 countings filtering parameter shift memory (53), the counting input signal of counter IP kernel outside input runs time clock CLK II with counting processing controls and is connected,

Described address strobe control I (45) also decomposes storage control module (II) with data input and output and command word and 8 count parameter dual-ported memories (46) are connected;

Described 8 count parameter dual-ported memories (46) are also decomposed storage control module (II) and 8 and are counted real-time parameter dual-ported memory (48) and be connected with data input and output and command word;

Described address strobe controls II (47) and also decomposes storage control module (II) and 8 with 8-bit microprocessor application system (I), data input and output and command word and count real-time parameter dual-ported memory (48) and be connected;

Described 8 countings real-time parameter dual-ported memory (48) are also decomposed storage control module (II) with data input and output and command word and are connected;

Storage control module (II) is also decomposed in described address strobe control III (49) with data input and output and command word and 4 mode of operation frequency division times number encoder dual-ported memories (50) are connected;

Described 4 mode of operation frequency divisions times number encoder dual-ported memory (50) also decomposes storage control module (II) with data input and output and command word and is connected;

Described address strobe controls IV (51) and also decomposes storage control module (II) and 3 states with data input and output and command word and control dual-ported memory (52) and be connected;

Described 3 states control dual-ported memory (52) also decompose storage control module (II) with data input and output and command word, the reset signal of 8-bit microprocessor application system (I) is connected; If the reset signal of input is effective reset signal, 3 states that reset control dual-ported memory (52), stop the counting of all counters.

4. a kind of counter IP kernel be connected with 8-bit microprocessor application system as claimed in claim 3, it is characterized in that: described counter overflow mark control module (V) comprises not gate (7), M0 mode of operation bit register group (8), overflow quenching pulse controller (9), Sheffer stroke gate I (10), d type flip flop I (11), with door I (12), Sheffer stroke gate II (13), d type flip flop II (14), Sheffer stroke gate III (15), d type flip flop III (16), with door II (17), Sheffer stroke gate IV (18), d type flip flop IV (19), Sheffer stroke gate V (20), d type flip flop V (21), with door III (22), Sheffer stroke gate VI (23), d type flip flop VI (24), Sheffer stroke gate VII (25), d type flip flop VII (26), Sheffer stroke gate VIII (27), d type flip flop VIII (28), with door IV (29), Sheffer stroke gate Ⅸ (30), d type flip flop Ⅸ (31), Sheffer stroke gate Ⅹ (32), d type flip flop Ⅹ (33), with door V (34), Sheffer stroke gate Ⅺ (35), d type flip flop Ⅺ (36), Sheffer stroke gate Ⅻ (37), d type flip flop Ⅻ (38), with door VI (39), Sheffer stroke gate Ⅹ III (40), d type flip flop Ⅹ III (41), Sheffer stroke gate Ⅹ IV (42), d type flip flop Ⅹ IV (43),

The M0 output terminal that input end and data input and output and the command word of described not gate (7) decompose the mode control register (6) of storage control module (II) is connected, and output terminal is connected with an input end of M0 mode of operation bit register group (8);

The counter numbering output terminal writing mode of operation filtering code command word signal output part sum counter numbered register (4) that another three input ends of M0 mode of operation bit register group (8) decompose the read-write control module (2) of storage control module (II) with the reset signal output terminal of 8-bit microprocessor application system (I), data input and output with command word is respectively connected, and output terminal is respectively with door I (12), with door II (17), with door III (22), with door IV (29), with door V (34), be connected with an input end of door VI (39);

What three input ends overflowing quenching pulse controller (9) decomposed the read-write control module (2) of storage control module (II) respectively with data input and output and command word writes STATUS control commands word signal output part, the counter numbering output terminal of clear overflow indicator output terminal sum counter numbered register (4) of mode control register (6) connects, output terminal is Sheffer stroke gate I (10) respectively, Sheffer stroke gate II (13), Sheffer stroke gate III (15), Sheffer stroke gate IV (18), Sheffer stroke gate V (20), Sheffer stroke gate VI (23), Sheffer stroke gate VII (25), Sheffer stroke gate VIII (27), Sheffer stroke gate Ⅸ (30), Sheffer stroke gate Ⅹ (32), Sheffer stroke gate Ⅺ (35), Sheffer stroke gate Ⅻ (37), Sheffer stroke gate Ⅹ III (40), an input end of Sheffer stroke gate Ⅹ IV (42) connects, output terminal is also connected with the data input pin of d type flip flop I (11), d type flip flop II (14), d type flip flop III (16), d type flip flop IV (19), d type flip flop V (21), d type flip flop VI (24), d type flip flop VII (26), d type flip flop VIII (28), d type flip flop Ⅸ (31), d type flip flop Ⅹ (33), d type flip flop Ⅺ (36), d type flip flop Ⅻ (38), d type flip flop Ⅹ III (41) and d type flip flop Ⅹ IV (43),

Another input end of Sheffer stroke gate I (10) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop I (11);

The data output end of d type flip flop I (11) and being connected with another input end of door I (12);

To output signal as the overflow indicator of 16 digit counters 0 with the output terminal of door I (12) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate II (13) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop II (14);

The data output end of d type flip flop II (14) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 digit counter 1/32 digit counters 0;

Another input end of Sheffer stroke gate III (15) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop III (16);

The data output end of d type flip flop III (16) and being connected with another input end of door II (17);

To output signal as the overflow indicator of 16 digit counters 2 with the output terminal of door II (17) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate IV (18) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop IV (19);

The data output end of d type flip flop IV (19) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 digit counter 3/32 digit counters 1;

Another input end of Sheffer stroke gate V (20) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop V (21);

The data output end of d type flip flop V (21) and being connected with another input end of door III (22);

To output signal as the overflow indicator of 16 digit counters 4 with the output terminal of door III (22) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate VI (23) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop VI (24);

The data output end of d type flip flop VI (24) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 digit counter 5/32 digit counters 2;

Another input end of Sheffer stroke gate VII (25) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop VII (26);

The data output end of d type flip flop VII (26) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 digit counters 6;

Another input end of Sheffer stroke gate VIII (27) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop VIII (28);

The data output end of d type flip flop VIII (28) and being connected with another input end of door IV (29);

To output signal as the overflow indicator of 16 digit counters 7 with the output terminal of door IV (29) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate Ⅸ (30) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅸ (31);

The data output end of d type flip flop Ⅸ (31) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 digit counter 8/32 digit counters 3;

Another input end of Sheffer stroke gate Ⅹ (32) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ (33);

The data output end of d type flip flop Ⅹ (33) and being connected with another input end of door V (34);

To output signal as the overflow indicator of 16 digit counters 9 with the output terminal of door V (34) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate Ⅺ (35) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅺ (36);

The data output end of d type flip flop Ⅺ (36) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 digit counter 10/32 digit counters 4;

Another input end of Sheffer stroke gate Ⅻ (37) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅻ (38);

The data output end of d type flip flop Ⅻ (38) and being connected with an input end of door VI (39);

To output signal as the overflow indicator of 16 digit counters 11 with the output terminal of door VI (39) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate Ⅹ III (40) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ III (41);

The data output end of d type flip flop Ⅹ III (41) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 digit counter 12/32 digit counters 5;

Another input end of Sheffer stroke gate Ⅹ IV (42) is connected with the overflow indicator output terminal of counting processing and control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ IV (43);

The data output end of d type flip flop Ⅹ IV (43) is connected with 8-bit microprocessor application system (I) as 16 digit counter 13 overflow indicator output signal output terminals.