CN105117357B - A kind of counter IP kernel being connected with 8-bit microprocessor application system and its method for realizing rolling counters forward control - Google Patents
A kind of counter IP kernel being connected with 8-bit microprocessor application system and its method for realizing rolling counters forward control Download PDFInfo
- Publication number
- CN105117357B CN105117357B CN201510376781.9A CN201510376781A CN105117357B CN 105117357 B CN105117357 B CN 105117357B CN 201510376781 A CN201510376781 A CN 201510376781A CN 105117357 B CN105117357 B CN 105117357B
- Authority
- CN
- China
- Prior art keywords
- counter
- control module
- type flip
- flip flop
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005096 rolling process Methods 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims description 23
- 238000012545 processing Methods 0.000 claims abstract description 110
- 238000001914 filtration Methods 0.000 claims description 112
- 230000015654 memory Effects 0.000 claims description 70
- 230000006870 function Effects 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 6
- 238000010791 quenching Methods 0.000 claims description 6
- 230000000171 quenching effect Effects 0.000 claims description 6
- 230000005574 cross-species transmission Effects 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000000354 decomposition reaction Methods 0.000 claims description 3
- 238000006073 displacement reaction Methods 0.000 claims description 3
- 230000009131 signaling function Effects 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 3
- 241001269238 Data Species 0.000 claims description 2
- 238000011282 treatment Methods 0.000 claims description 2
- 240000007320 Pinus strobus Species 0.000 claims 14
- 210000001367 artery Anatomy 0.000 claims 1
- 210000003462 vein Anatomy 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 11
- 235000013399 edible fruits Nutrition 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 5
- 241000208340 Araliaceae Species 0.000 description 3
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 3
- 235000003140 Panax quinquefolius Nutrition 0.000 description 3
- 235000008434 ginseng Nutrition 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 101000743788 Homo sapiens Zinc finger protein 92 Proteins 0.000 description 1
- 102100039046 Zinc finger protein 92 Human genes 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Complex Calculations (AREA)
Abstract
A kind of counter IP kernel being connected with 8-bit microprocessor application system, including data input output decompose storage control module with command word, the frequency divider of pulse 12, count processing and control module, counter overflow mark control module and input gate selection control module；The present invention applies FPGA design counter IP kernel Hard link control circuit, counter IP kernel has 14 16 digit counters, wherein 12 can make up 6 32 digit counters, a command word sets mode of operation, filter the parameter setting of reference clock pulse multiple, another command word control working condition；The present invention is in addition to 8-bit microprocessor carries out function to counter and state is set, count parameter is transmitted, reading counts the operation of currency, each 16/32 digit counter also has automatic reloading count parameter function, is not take up 8-bit microprocessor program execution time；It disclosure satisfy that large number of rolling counters forward and the demand of counting control system.
Description
Technical field
The present invention relates to a kind of counter IP kernel being connected with 8-bit microprocessor application system and its realize rolling counters forward
The method of control, more particularly to a kind of the characteristics of being based on FPGA parallel processings, the energy formed using FPGA design hardware circuitry
Enough counter IP kernels being connected with 8-bit microprocessor application system and its method for realizing rolling counters forward control.
Background technology
In extensive tally control or other 8-bit microprocessor application systems needed using numerous counters, it will make
With substantial amounts of counter, extension counter number has three kinds of implementations：First way is to apply one in microprocessor
The count value of counter is programmed using counting interrupt mode as reference count value, sets times number variable of reference count value, be somebody's turn to do
Count value times number variable is also the marking variable of extension counter, and programmed method mainly has 2 kinds, and the 1st kind of method is to perform once
Counter interrupts service function count value times number variable and adds 1, and compared with the multiple value of the reference count value of setting, if counted
Value times number variable has reached the multiple value of the reference count value of setting, and clear to count value times number variable 0, then perform the extension meter
The program that counter count value overflows；Or the marking variable of an extension counter is specially set, when count value times number variable has reached
To the reference count value of setting multiple value when, clear to count value times number variable 0, the marking variable of 1 counter is put, in principal function
Program in judge whether the marking variable of the counter is " 1 ", if it is, the marking variable of clear 0 counter, performs one
The processing function that the secondary extension counter count value is overflowed；The second way is that microprocessor is connected with counter extension chip,
Counter chip mainly has 82C54 at present, can extend 3 16 digit counters；
Following weak point be present in two kinds of implementations of the above：
1. the counting interrupt method of application reference counter, CPU are responded and are exited reference counter interrupt service routine and account for
With CPU run times；Reference count value is smaller, and the counter that counter system needs extend is more, will take CPU run times
Longer, the execution speed to other program modules produces serious influence；
2. the second way extends out private counter chip using microprocessor, required counter is more, extends out special
Counter chip is more, and the circuit scale of 8-bit microprocessor application system is bigger；
The third mode is counted using non-programmable hardware, and each of which counter is realized with independent hardware circuit；
Tally function is realized in this way, and required counter is more, and circuit scale is bigger, and maintenance workload is big.
The content of the invention
It is an object of the invention to fully apply FPGA parallel processing function, there is provided a kind of micro- based on FPGA and 8
The counter IP kernel and its realize the method that rolling counters forward controls that processor application system connects, have 14 inside counter IP kernel
Individual 16 digit counter, can be set to 6 32 digit counters using 12 16 digit counters, each 16 digit counter or 32
Counter can export counting spill over, can program the work for setting gate-control signal control counter, the work of counter
Pattern, selects the filtering parameter of four kinds of counting input pulses, and the counter IP kernel only needs two by initial program to order
Order sets the working operating mode of each counter, being capable of automatic reloading counting ginseng when each counter overflows
Number, counting process are not take up the time of 8-bit microprocessor program execution, can realize to quantity up to 14 16 digit counters or
The advantages that counting of 6 32 digit counters and tally control, to overcome the shortcomings of that existing counting mode is realized present in technology.
In order to solve the above technical problems, the present invention adopts the technical scheme that：It is a kind of to connect with 8-bit microprocessor application system
The counter IP kernel connect, it is characterised in that：The counter IP kernel includes data input output and decomposes storage control mould with command word
Block, the frequency divider of pulse 12, count processing and control module, counter overflow mark control module, input gate selection control module；
The data input output is decomposed at storage control module and 8-bit microprocessor application system, counting with command word
Reason control module, counter overflow mark control module and input gate selection control module and connected；
The frequency divider of pulse 12 is also connected with 8-bit microprocessor application system and counting processing and control module；
It is described counting processing and control module also with 8-bit microprocessor application system, counter overflow mark control module and
Input gate selection control module connection；
It is low level bar that the data input output decomposes storage control module in the chip selection signal of input with command word
The counter given under part if write signal is effective according to 8-bit microprocessor application system or the address of counter command word,
Obtain the mode of operation frequency dividing multiple coded command word of counter operation, STATUS control commands word, 16 digit counters or 32 meters
The count parameter of number device, and given respectively according to count parameter, counter numbering, mode of operation frequency dividing times number encoder and state control
To store and export, also output is write mode of operation frequency dividing multiple coded command word signal, write state control command word signal and write
Counter parameter signal；If read signal effectively transmits counter real-time counting value to 8-bit microprocessor application system；
The frequency divider of pulse 12 is divided to the clock pulses of 8-bit microprocessor application system, and it is exported as meter
The filtering reference clock pulse of the rolling counters forward control operation of number processing and control module；
The counting processing and control module is in the presence of mode of operation frequency dividing multiple coded command word signal is write, according to meter
Number device numbering stores the mode of operation of the counter, the encoded radio of filtering reference clock frequency dividing multiple；In write state control command
In the presence of word signal, the state control signal for storing the counter is numbered according to counter；Writing counter parameter signal
Under effect, the count parameter for storing the counter is numbered according to counter；The counting processing and control module is in counter IP kernel
In the presence of the counting processing control operation clock pulses CLK II of outside input, control counts the operation of processing and control module, presses
All single treatments for having been turned on counter, bag are completed according to a filtering reference clock pulse cycle of the frequency divider of pulse 12 output
Include the state control process of each counter, the judgement processing of mode of operation, when the number of filtering reference clock reaches one 16
During filtering reference clock multiple value of position/32 set by digit counter, from counter IP kernel outside read in the counting of the counter
Input signal, a filtering process is carried out, if it is determined that being once effectively count pulse, then to the real-time counting of the counter
Parameter value carries out plus 1 operation, when producing spilling, count parameter is reloaded automatically to real-time counting parameter value, and export spilling mark
Will signal；Under the conditions of the chip selection signal of data input output and command word decomposition storage control module input is low level,
If read signal is effective, the address of the counter given according to 8-bit microprocessor application system, the reality of the counter is directly read
When count parameter value through data input output with command word decompose storage control module be transferred to 8-bit microprocessor application system
Data/address bus, the real-time counting parameter of 16 digit counters need timesharing to be read twice, the real-time counting ginseng of 32 digit counters
Number needs timesharing to be read for four times；Under the reset signal effect of 8-bit microprocessor application system output, stop all countings
The counting operation of device；
The high level that the counter overflow mark control module exports 16/32 digit counters is believed for effective overflow
Number；When the spill over of 16 digit counters of counting processing and control module output is transformed to high level by low level, the meter is stored
Number device overflow indicator is high level；If the counter overflow is masked as high level, clear overflow indicator is converted to low by high level
Level, store the counter overflow and be masked as low level；In the presence of mode of operation frequency dividing multiple coded command word signal is write,
Counter overflow mark control module stores the information of 32 digit counter mode of operations according to register number, blocks this 32 meters
The flooding information of low 16 of device of number remains low level；
The input gate selects control module in the case where writing mode of operation frequency dividing multiple coded command word signal function, according to
Counter numbering stores the mode of operation of the counter, is required according to gate control function determined by the counter works pattern and defeated
The gate level entered, the gate-control signal of control input gate selection control module output.
Its further technical scheme is：The data input output decomposes storage control module with command word includes 8 pairs
To data strobe triple gate group, read-write control module, count parameter register, counter numbered register, mode of operation
Filtering code register, mode control register；
8 bi-directional data strobe triple gates group controls mould with 8-bit microprocessor application system, read-write respectively
Block, count parameter register, counter numbered register, mode of operation filtering code register, mode control register and meter
Number processing and control module connection；
The read-write control module is also numbered with 8-bit microprocessor application system, count parameter register, counter
Register, mode of operation filtering code register, mode control register, count processing and control module, counter overflow mark
Control module gates selection control module with input and connected；
The count parameter register is also connected with counting processing and control module；
The counter numbered register also overflows with 8-bit microprocessor application system, counting processing and control module, counter
Go out to indicate that control module gates selection control module with input and connected；
The mode of operation filtering code register also with 8-bit microprocessor application system, count processing and control module, meter
Number device overflow indicator control module gates selection control module with input and connected；
The mode control register also overflows with 8-bit microprocessor application system, counting processing and control module and counter
Go out to indicate that control module connects；
The data input output decomposes the read-write control module of storage control module in chip selection signal with command word
Under the conditions of low level, if write signal is effective, 8 bi-directional data strobe triple gate group write signals are sent, gate 8 micro- places
Manage the data input of device application system data/address bus；Counter numbering signal is write in generation, and judges 8-bit microprocessor application system
The address value of address bus input, if the address value of counter parameter, the address value is write into counter numbered register,
Counter parameter signal is write in generation, and 8 data of data/address bus are write into count parameter register；If counter command word
Address, the 2nd of data/address bus ~ the 5th data being write into counter numbered register, order word address is 0EH or 0FH, if
It is 0 to put the 3rd digit counter number value S3, is otherwise provided as 1；If command word least-significant byte address, then command word is mode of operation
Divide multiple coded command word, generation write mode of operation frequency dividing multiple coded command word signal, by the 0th of data/address bus, the 1st
Position, the 6th and the 7th write-in mode of operation frequency dividing multiple code registers；If command word most-significant byte address, then command word
It is STATUS control commands word, produces write state control command word signal, by the 0th of data/address bus, the 1st and the 7th write-in
Mode control register；If read signal is effective, 8 bi-directional data strobe triple gate group read signals are sent, processing control will be counted
Data/address bus of the data transfer of output data bus to 8-bit microprocessor application system inside the counter IP kernel of molding block.
Its further technical scheme is：The counting processing and control module includes rolling counters forward control operation module,
Address strobe control I, 8 count parameter dual-ported memories, address strobe control II, 8 count real-time parameter dual-port and deposit
Reservoir, address strobe control III, 4 mode of operations divide times number encoder dual-ported memory, address strobe control IV, 3 shapes
State controls dual-ported memory, 4 counting filtering parameter shift memories；
The rolling counters forward control operation module respectively with the frequency divider of pulse 12, counter overflow mark control module,
Input gate selection control module, address strobe control I, 8 count parameter dual-ported memory, address strobe to control II, 8
Count real-time parameter dual-ported memory, address strobe controls III, 4 mode of operation frequency dividing times number encoder dual-ported memory,
Address strobe controls IV, 3 state control dual-ported memory, 4 counting filtering parameter shift memories, counter IP kernel
The counting input signal and counting processing control operation clock pulses CLK II of outside input connect；
The address strobe control I also decomposes storage control module with command word with data input output and 8 countings are joined
Number dual-ported memory connection；
8 count parameter dual-ported memories also with data input output with command word decompose storage control module and
8 count the connection of real-time parameter dual-ported memory；
The address strobe control II is also decomposed with command word and deposited with 8-bit microprocessor application system, data input output
Storage control module counts real-time parameter dual-ported memory with 8 and connected；
Described 8 count real-time parameter dual-ported memory and also decompose storage control mould with data input output and command word
Block connects；
The address strobe control III also decomposes storage control module and 4 Working moulds with data input output with command word
Formula frequency dividing times number encoder dual-ported memory connection；
4 mode of operations frequency dividing times number encoder dual-ported memory also exports to decompose with command word with data input to be deposited
Store up control module connection；
The address strobe control IV also decomposes storage control module and 3 state controls with data input output with command word
Dual-ported memory connection processed；
3 states control dual-ported memory also decomposes storage control module, 8 with data input output with command word
The reset signal connection of bit microprocessor application system；If the reset signal of input is effective reset signal, 3 shapes are resetted
State controls dual-ported memory, stops the counting of all counters.
Further technical scheme is for it：The counter overflow mark control module includes NOT gate, M0 mode of operations position
Register group, overflow quenching pulse controller, NAND gate I, d type flip flop I, with door I, NAND gate II, d type flip flop II, NAND gate
III, d type flip flop III, with door II, NAND gate IV, d type flip flop IV, NAND gate V, d type flip flop V, with door III, NAND gate VI, D is touched
Send out device VI, NAND gate VII, d type flip flop VII, NAND gate VIII, d type flip flop VIII, with door IV, NAND gate Ⅸ, d type flip flop Ⅸ, NAND gate
Ⅹ, d type flip flop Ⅹ, with door V, NAND gate Ⅺ, d type flip flop Ⅺ, NAND gate Ⅻ, d type flip flop Ⅻ, with door VI, NAND gate Ⅹ III, D
Trigger Ⅹ III, NAND gate Ⅹ IV, d type flip flop Ⅹ IV；
The state control that the input of the NOT gate decomposes storage control module with data input output with command word is deposited
The M0 output ends connection of device, output end are connected with an input of M0 mode of operation bit register groups；
The other three input of the M0 mode of operation bit register groups reset signal with 8-bit microprocessor application system respectively
The mode of operation of writing for the read-write control module that output end, data input output decompose storage control module with command word filters
Coded command word signal output part connects with the counter numbering output end of counter numbered register, output end respectively with door I,
It is connected with door II, with door III, with door IV, with door V, with an input of door VI；
Three inputs for overflowing quenching pulse controller decompose storage control with data input output and command word respectively
Write state control command word signal output part, the clear overflow indicator of mode control register of the read-write control module of module
Output end connects with the counter numbering output end of counter numbered register, output end difference NAND gate I, NAND gate II, with
NOT gate III, NAND gate IV, NAND gate V, NAND gate VI, NAND gate VII, NAND gate VIII, NAND gate Ⅸ, NAND gate Ⅹ, NAND gate
Ⅺth, the input connection of NAND gate Ⅻ, NAND gate Ⅹ III, NAND gate Ⅹ IV；Output end also with d type flip flop I, d type flip flop
IIth, d type flip flop III, d type flip flop IV, d type flip flop V, d type flip flop VI, d type flip flop VII, d type flip flop VIII, d type flip flop Ⅸ, D are touched
Hair device Ⅹ, d type flip flop Ⅺ, d type flip flop Ⅻ, d type flip flop Ⅹ III connect with the data input pin of d type flip flop Ⅹ IV；
Another input of NAND gate I is connected with counting the overflow indicator output end of processing and control module, output end and D
The clock signal input terminal connection of trigger I；
The data output end of d type flip flop I and it is connected with another input of door I；
Connect with the output end of door I as the overflow indicator output signal of 16 digit counters 0 with 8-bit microprocessor application system
Connect；
Another input of NAND gate II with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop II；
The data output end of d type flip flop II is defeated as the overflow indicator output signal of the digit counter 0 of 16 digit counter 1/32
Go out end to be connected with 8-bit microprocessor application system；
Another input of NAND gate III with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop III；
The data output end of d type flip flop III and it is connected with another input of door II；
With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door II as 16 digit counters 2
Connection；
Another input of NAND gate IV with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop IV；
The data output end of d type flip flop IV is defeated as the overflow indicator output signal of the digit counter 1 of 16 digit counter 3/32
Go out end to be connected with 8-bit microprocessor application system；
Another input of NAND gate V with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop V；
The data output end of d type flip flop V and it is connected with another input of door III；
With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door III as 16 digit counters 4
Connection；
Another input of NAND gate VI with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop VI；
The data output end of d type flip flop VI is defeated as the overflow indicator output signal of the digit counter 2 of 16 digit counter 5/32
Go out end to be connected with 8-bit microprocessor application system；
Another input of NAND gate VII with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop VII；
Overflow indicator output signal output end and 8 micro- places of the data output end of d type flip flop VII as 16 digit counters 6
Manage the connection of device application system；
Another input of NAND gate VIII with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop VIII；
The data output end of d type flip flop VIII and it is connected with another input of door IV；
With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door IV as 16 digit counters 7
Connection；
Another input of NAND gate Ⅸ with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop Ⅸ；
The data output end of d type flip flop Ⅸ is defeated as the overflow indicator output signal of the digit counter 3 of 16 digit counter 8/32
Go out end to be connected with 8-bit microprocessor application system；
Another input of NAND gate Ⅹ with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop Ⅹ；
The data output end of d type flip flop Ⅹ and it is connected with another input of door V；
With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door V as 16 digit counters 9
Connection；
Another input of NAND gate Ⅺ with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop Ⅺ；
The data output end of d type flip flop Ⅺ is defeated as the overflow indicator output signal of the digit counter 4 of 16 digit counter 10/32
Go out end to be connected with 8-bit microprocessor application system；
Another input of NAND gate Ⅻ with count processing and control module overflow indicator output end be connected, output end and
The clock signal input terminal connection of d type flip flop Ⅻ；
The data output end of d type flip flop Ⅻ and it is connected with an input of door VI；
With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door VI as 16 digit counters 11
Connection；
Another input of NAND gate Ⅹ III is connected with counting the overflow indicator output end of processing and control module, output end
It is connected with the clock signal input terminal of d type flip flop Ⅹ III；
Overflow indicator output signal of the data output end of d type flip flop Ⅹ III as the digit counter 5 of 16 digit counter 12/32
Output end is connected with 8-bit microprocessor application system；
Another input of NAND gate Ⅹ IV is connected with counting the overflow indicator output end of processing and control module, output end
It is connected with the clock signal input terminal of d type flip flop Ⅹ IV；
The data output end of d type flip flop Ⅹ IV is micro- as the overflow indicator output signal output end of 16 digit counter 13 and 8
Processor application system connects.
Related another technical scheme is：A kind of counter IP kernel being connected with 8-bit microprocessor application system is based on
The method of rolling counters forward control, it is with a kind of above-mentioned counter being connected with 8-bit microprocessor application system of the present invention
IP kernel realizes the method for rolling counters forward control operation；
The rolling counters forward control operation concretely comprises the following steps：
s101：Multiple u storage of array unit, the displacement v storage of array units of clear filtering reference clock pulse, counter are compiled
Number value j；
s102：Reference clock pulse trailing edge trigger is filtered to perform 1 time；
s103：Judge whether counter number value j is equal to or more than 1EH, if j value is equal to or more than 1EH, enter
Step s104, otherwise into s105；
s104：Counter number value j=00H, return to step s102 are set；
s105：Judge whether counter number value j is equal to 0EH or 0FH, if j value is equal to 0EH or 0FH, enter
Enter step s106, otherwise into step s107；
s106：Counter number value j=10H is set, into step s107；
s107：Judgement opens/stopped whether signal is equal to 0, if open/stopping signal=0, the counter stops Counts, enters
Step s108, otherwise into step s111；
s108：Judge it is clear count whether currency is equal to 0, if counting currency=0 clearly, into step s109, otherwise
Into step s110；
s109：The value of the clear rolling counters forward currency memory cell, into step s110；
s110：Counter number value j adds 2, return to step s103；
s111：The multiple of the filtering reference clock pulse of the counter adds 1：U (j)=u (j)+1, into step s112；
s112：Judge the counter works pattern, if mode of operation M1M0=10,16 digit counters are gated, into step
s113；If mode of operation M1M0=00,16 digit counters of no gate, into step s118；If mode of operation M1M0=01,
32 digit counters without gate, into step s114；If mode of operation M1M0=11,32 digit counters of gate are selected, are entered
Enter step s115；
s113：Whether the gate-control signal for judging 16 digit counter is 0, the return to step if gate-control signal is equal to 0
S110, otherwise into step s118；
s114：Judge whether low 2 of 32 digit counter number value j be equal to 00, if equal to 00 enters step
S131, otherwise return to step s110；
s115：Judge whether low 2 of 32 digit counter number value j be equal to 00, if equal to 00 enters step
S116, otherwise return to step s110；
s116：Whether the gate-control signal for judging 32 digit counter is 0, enters step if gate-control signal is equal to 0
S117, otherwise into step s131；
s117：Counter number value j adds 4, return to step s103；
s118：Judge the coding of the filtering parameter of 16 digit counter, if filtering parameter is encoded to F2F1=00, enter
Enter step s122；If filtering parameter is encoded to F2F1=01, into step s119；If filtering parameter is encoded to
F2F1=10, then into step s120；If filtering parameter is encoded to F2F1=11, into step s121；
s119：Judge whether the multiple u (j) of the filtering reference clock pulse of 16 digit counter value is equal to 100, if
U (j)=100, then into step s122, otherwise return to step s110；
s120：Judge whether the multiple u (j) of the filtering reference clock pulse of 16 digit counter value is equal to 1000, such as
Fruit u (j)=1000, then into step s122, otherwise return to step s110；
s121：Judge whether the multiple u (j) of the filtering reference clock pulse of 16 digit counter value is equal to 10000, such as
Fruit u (j)=10000, then into step s122, otherwise return to step s110；
s122：The multiple u (j) of the filtering reference clock pulse of 16 digit counter value is set to be equal to 0, into step
s123；
s123：The value of the counting input end of 16 digit counter is read in, v (j) moves to left one, counts input value and enters v (j)
The 0th, into step s124；
s124：Judge the 0th of the 16 digit counter v (j) it is whether equal with the 1st data, if equal, into step
S125, otherwise return to step s110；
s125：Judge the 2nd of the 16 digit counter v (j) it is whether equal with the 3rd data, if equal, into step
S126, otherwise return to step s110；
s126：Judge the 0th of the 16 digit counter v (j) it is whether equal with the 3rd data, if unequal, into step
Rapid s127, otherwise return to step s110；
s127：Judge whether the 0th of the 16 digit counter v (j) be equal to 0, if equal to 0, represent 16 digit counter
Counting input end generate an effectively count pulse, into step s128, otherwise return to step s110；
s128：Read 16 of 16 digit counter to count currencys and add 1, be as a result stored in 16 digit counter 16
Currency memory cell is counted, into step s129；
s129：Judge whether the count value of 16 digit counter produces spilling, enter step s130 if spilling is produced,
Otherwise return to step s110 is entered；
s130：Reload 16 count parameters of 16 digit counter, return to step s110；
s131：Judge the coding of the filtering parameter of 32 digit counter, if filtering parameter is encoded to F2F1=00, enter
Enter step s135；If filtering parameter is encoded to F2F1=01, into step s132；If filtering parameter is encoded to
F2F1=10, then into step s133；If filtering parameter is encoded to F2F1=10, into step s134；
s132:Judge whether the multiple u (j) of the filtering reference clock pulse of 32 digit counter value is equal to 100, such as
Fruit u (j)=100, then into step s135, otherwise return to step s117；
s133:Judge whether the multiple u (j) of the filtering reference clock pulse of 32 digit counter value is equal to 1000, such as
Fruit u (j)=1000, then into step s135, otherwise into step s117；
s134:Judge whether the multiple u (j) of the filtering reference clock pulse of 32 digit counter value is equal to 10000,
If u (j)=10000, into step s135, otherwise into step s117；
s135:The multiple u (j) of the filtering reference clock pulse of 32 digit counter value is set to be equal to 0, into step
s136；
s136：The value of the counting input end of 32 digit counter is read in, v (j) moves to left one, counts input value and enters v (j)
The 0th, into step s137；
s137：Judge the 0th of the 32 digit counter v (j) it is whether equal with the 1st data, if equal, into step
S138, otherwise return to step s117；
s138：Judge the 2nd of the 32 digit counter v (j) it is whether equal with the 3rd data, if equal, into step
S139, otherwise return to step s117；
s139：Judge the 0th of the 32 digit counter v (j) it is whether equal with the 3rd data, if unequal, into step
Rapid s140, otherwise return to step s117；
s140：Judge whether the 0th of the 32 digit counter v (j) be equal to 0, if equal to 0, represent 32 digit counter
Counting input end generate an effectively count pulse, into step s141, otherwise return to step s117；
s141：Read 32 of 32 digit counter to count currencys and add 1, be as a result stored in the 32 of 32 digit counter
Position counts currency memory cell, into step s142；
s142:Judge whether the count value of 32 digit counter produces spilling, enter step if spilling is produced
S143, otherwise return to step s117；
s143：Reload 32 count parameters of 32 digit counter, return to step s117.
Due to use above structure, a kind of counter IP kernel being connected with 8-bit microprocessor application system of the present invention and
It realizes that the method for rolling counters forward control has the advantages that：
1. it is connected with 8-bit microprocessor application system, programming Control facility
The counter IP kernel of the present invention directly can be connected with 8-bit microprocessor application system, in counter IP kernel
When each counter carries out function setting, 8-bit microprocessor only needs to can determine that this to 1 command word of counter IP kernel transmission
The mode of operation of counter, count the filtering parameter of filtering reference clock pulse；Send another command word and start the counter
Counts, and whether the overflow indicator and whether clearly counting currency of the clear counter；For 16 digit counters,
Time sharing transmissions most-significant byte and least-significant byte count parameter；For 32 digit counters, 32 count parameters are transmitted in four times；8 micro-
Processor can also directly read the real-time counting value of the counter, programming Control counter facility according to the address of counter.
2. it is adapted to the system requirements of large number of rolling counters forward and tally control
There are 14 16 digit counters inside the counter IP kernel of the present invention, need setting command word can according to counting application
So that 2 16 digit counters are formed into 32 digit counters, 6 32 digit counters of composition can be set, additionally it is possible to set four kinds of selection
Count the filtering parameter of filtering reference clock pulse；When counting generation counting spill over, counter IP kernel of the invention can
Automatic reloading count parameter, it disclosure satisfy that the system requirements of large number of rolling counters forward and tally control.
3.FPGA parallel processings count, and counter IP kernel is cost-effective
The present invention is except 8-bit microprocessor carries out function setting to counter, count parameter is transmitted, software counts clearly spilling mark
Will, read and count currency, and need outside the clear operation for counting currency, the program for being not take up 8-bit microprocessor is held
The row time；The counter IP kernel formed using FPGA design hardware circuitry can be reconstructed as 7 16 digit counters, Neng Goushe
Put 3 32 digit counters of composition；A kind of counter IP kernel being connected with 8-bit microprocessor application system of the present invention and its realization
The method of rolling counters forward control can select four kinds of filtering parameters for counting filtering reference clock pulse, realize and inputted to counting
The filtering of pulse, automatic reloading count parameter, the time for taking the program execution of 8-bit microprocessor is greatly reduced, by it
System for developing large number of rolling counters forward and tally control, very high cost performance can be obtained.
With reference to the accompanying drawings and examples to a kind of counter IP being connected with 8-bit microprocessor application system of the present invention
Core and its realize that the technical characteristic of method of rolling counters forward control is further described.
Brief description of the drawings
Fig. 1：A kind of circuit structure block diagram of counter IP kernel being connected with 8-bit microprocessor application system of the present invention；
Fig. 2：A kind of encapsulation of counter IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention one
Figure；
Fig. 3：A kind of data of counter IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention one are defeated
Enter the circuit block diagram that storage control module is decomposed in output with command word；
Fig. 4：At a kind of counting of counter IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention one
Manage the circuit block diagram of control module；
Fig. 5：A kind of counter of counter IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention one
The circuit block diagram of overflow indicator control module；
Fig. 6：A kind of encapsulation of counter IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention two
Figure；
Fig. 7：A kind of data of counter IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention two are defeated
Enter the circuit block diagram that storage control module is decomposed in output with command word；
Fig. 8：A kind of counter of counter IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention two
The circuit block diagram of overflow indicator control module；
Fig. 9-1~Fig. 9-3：A kind of counter IP being connected with 8-bit microprocessor application system of the embodiment of the present invention one
The rolling counters forward control operation program flow diagram of core.
Figure 10-1：A kind of meter of counter IP kernel being connected with 8-bit microprocessor application system of the embodiment of the present invention two
Rolling counters forward control operation program flow diagram（With the different piece of embodiment one）.
In figure：
I -8-bit microprocessor application system, the output of II-data input decompose storage control module with command word,
The frequency divider of III-pulse 12, IV-counting processing and control module, V-counter overflow mark control module, VI-
Input gate selection control module；
1-8 bi-directional data strobe triple gate groups, 2-read-write control module, 3-count parameter register, 4-
Counter numbered register, 5-mode of operation filtering code register, 6-mode control register, 7-NOT gate, 8-M0 works
Operation mode bit register group, 9-overflow quenching pulse controller, 10-NAND gate I, 11-d type flip flop I, 12-with door I,
13-NAND gate II, 14-d type flip flop II, 15-NAND gate III, 16-d type flip flop III, 17-with door II, 18-NAND gate
IV, 19-d type flip flop IV, 20-NAND gate V, 21-d type flip flop V, 22-triggered with door III, 23-NAND gate VI, 24-D
Device VI, 25-NAND gate VII, 26-d type flip flop VII, 27-NAND gate VIII, 28-d type flip flop VIII, 29-with door IV, 30-with
NOT gate Ⅸ, 31-d type flip flop Ⅸ, 32-NAND gate Ⅹ, 33-d type flip flop Ⅹ, 34-with door V, 35-NAND gate Ⅺ, 36-D
Trigger Ⅺ, 37-NAND gate Ⅻ, 38-d type flip flop Ⅻ, 39-with door VI, 40-NAND gate Ⅹ III, 41-d type flip flop Ⅹ
III, 42-NAND gate Ⅹ IV, 43-d type flip flop Ⅹ IV, 44-rolling counters forward control operation module, the control of 45-address strobe
I, 46-8 count parameter dual-ported memories, 47-address strobe control II, 48-8 count real-time parameter dual-port and deposit
Reservoir, 49-address strobe control III, 50-4 mode of operations divide times number encoder dual-ported memory, 51-address strobe
Control IV, 52-3 states control dual-ported memory；53-4 counting filtering parameter shift memories.
Abbreviation explanation in text：
FPGA-Field Programmable Gate Array, field programmable gate array；
RD-Read signals, read signal；
CS-Chip Select signals, chip selection signal；
WR-Write, write signal；
RST-Reset, reset signal；
AB-Address Bus, address bus；
DB-Data Bus, data/address bus；
CLK-Clock pulse, clock pulses；
TF- count value overflow indicator output signals；
GATE- gates input signal；
M0-16/32 digit counters encode, and M0 is " 0 ", 16 digit counters；M0 is " 1 ", 32 digit counters；
M1- gate modes encode, and M1 is " 0 ", no gate input signal control counter；M1 is " 1 ", gate input letter
Number control counter；
Input data bus inside DB_1- counters IP kernel；
Output data bus inside DB_2- counters IP kernel；
RD_1-8 positions bi-directional data strobe triple gate group read signal；
RD_2- real-time counting value read signals；
WR_1-8 positions bi-directional data strobe triple gate group write signal；
WR_2- writes mode of operation filtering code command word signal；
WR_3- write state control command word signals；
WR_4- writes counter parameter signal；
WR_5- writes counter numbering signal；
I-clock pulses of CLK；
CLK II-counting processing control operation clock pulses；
The counting input signal of 14 16 digit counters of C0 ~ C13- counter IP kernels, wherein C0, C2, C4, C7, C9,
C11 corresponds to the counting input signal of 32 digit counters 0 ~ 5 respectively；
S0, S1, S2- the 0th, the 1st, the 2nd digit counter number value；
The digit counter number values of S3- the 3rd；
The gate input signal of GATE0 ~ 13-16 digit counters 0 ~ 13, wherein GATE1, GATE3, GATE5, GATE8,
GATE10, GATE12 correspond to the gate input signal of 32 digit counters 0 ~ 5 respectively；
The count value overflow indicator output signal of TF0 ~ 13-16 digit counters 0 ~ 13, wherein TF1, TF3, TF5, TF8,
TF10, TF12 correspond to the count value overflow indicator output signal of 32 digit counters 0 ~ 5 respectively；
D type flip flop-Data flip-flop；
D-Data input, d type flip flop data input pin；
Q-Data output, d type flip flop data output end；
CP-Clock Pulse input, clock signal input terminal.
Embodiment
A kind of counter IP kernel being connected with 8-bit microprocessor application system：
As shown in figure 1, the counter IP kernel includes data input output decomposes storage control module II, pulse with command word
12 frequency dividers III, count processing and control module IV, counter overflow mark control module V, input gate selection control module
Ⅵ；
The data input output decomposes storage control module II and 8-bit microprocessor application system I, counting with command word
Processing and control module IV, counter overflow mark control module V and input gate selection control module VI connect；
The frequency divider III of pulse 12 is also connected with 8-bit microprocessor application system I and counting processing and control module IV；
It is described counting processing and control module IV also with 8-bit microprocessor application system I, counter overflow mark control module
V connects with input gate selection control module VI；
It is low level that the data input output decomposes storage control module II in the chip selection signal of input with command word
Under the conditions of, if write signal is effective, the counter or the ground of counter command word that are given according to 8-bit microprocessor application system I
Location, obtain the mode of operation frequency dividing multiple coded command word of counter operation, STATUS control commands word, 16 digit counters or 32
The count parameter of counter, and divide times number encoder and state control difference according to count parameter, counter numbering, mode of operation
Stored and exported, also output write mode of operation frequency dividing multiple coded command word signal, write state control command word signal and
Write counter parameter signal；If read signal effectively transmits counter real-time counting value to 8-bit microprocessor application system I；
The frequency divider III of pulse 12 divides to the clock pulses of 8-bit microprocessor application system I, and it exports conduct
Count the filtering reference clock pulse of the rolling counters forward control operation of processing and control module IV；
It is described counting processing and control module IV write mode of operation frequency dividing multiple coded command word signal in the presence of, according to
Counter numbering stores the mode of operation of the counter, the encoded radio of filtering reference clock frequency dividing multiple；Control and order in write state
In the presence of making word signal, the state control signal for storing the counter is numbered according to counter；Writing counter parameter signal
In the presence of, the count parameter for storing the counter is numbered according to counter；The counting processing and control module IV is in counter
In the presence of the counting processing control operation clock pulses CLK II of IP kernel outside input, control counts processing and control module IV
Operation, the one of counter is had been turned on according to a filtering reference clock pulse cycle completion of the frequency divider III of pulse 12 output is all
Secondary processing, include the state control process of each counter, the judgement processing of mode of operation, when the number of filtering reference clock reaches
During to filtering reference clock multiple value set by 16/32 digit counters, from counter IP kernel outside read in the counting
The counting input signal of device, a filtering process is carried out, if it is determined that being once effectively count pulse, then to the counter
Real-time counting parameter value carries out plus 1 operation, and when producing spilling, count parameter is reloaded automatically to real-time counting parameter value, and defeated
Go out overflow indicator signal；It is low level in the chip selection signal that data input output decomposes the input of storage control module II with command word
Under conditions of, if read signal is effective, the address of the counter given according to 8-bit microprocessor application system I, directly reading should
The real-time counting parameter value of counter decomposes storage control module II with command word through data input output and is transferred to 8 microprocessors
The data/address bus of device application system I, the real-time counting parameter of 16 digit counters need timesharing to be read twice, 32 digit counters
Real-time counting parameter need timesharing to be read for four times；In the reset signal effect that 8-bit microprocessor application system I exports
Under, stop the counting operations of all counters；
The high level that the counter overflow mark control module V exports 16/32 digit counters is believed for effective overflow
Number；When the spill over for 16 digit counters that counting processing and control module IV exports is transformed to high level by low level, storage should
Counter overflow is masked as high level；If the counter overflow is masked as high level, clear overflow indicator is converted to by high level
Low level, store the counter overflow and be masked as low level；Writing the effect of mode of operation frequency dividing multiple coded command word signal
Under, counter overflow mark control module V stores the information of 32 digit counter mode of operations according to register number, and block should
The flooding information that 32 digit counters are low 16 remains low level；
The input gate selection control module VI is pressed in the case where writing mode of operation frequency dividing multiple coded command word signal function
According to counter number store the counter mode of operation, according to determined by the counter works pattern gate control function requirement and
The gate level of input, the gate-control signal that control input gate selection control module VI exports.
In order to be adapted to the system requirements of large number of rolling counters forward and tally control, according to the need of different counting applications
Will, the encapsulation of setting command word forms the counter IP kernel of different digits, therefore, there is following several embodiments：Such as can
So that 2 16 digit counters are formed into 32 digit counters, it is at best able to set 6 32 digit counters of composition, additionally it is possible to set selection
Frequency dividing multiple of four kinds of baseline clock pulses etc.；It is described below below.
Embodiment one：
A kind of counter IP kernel being connected with 8-bit microprocessor application system that 6 32 digit counters of composition can be set
A,（Hereinafter referred to as：Counter IP kernel A）：
As described above, as shown in figure 1, counter IP kernel A includes data input output decomposes storage control with command word
Module II, the frequency divider III of pulse 12, count processing and control module IV, counter overflow mark control module V, input gate choosing
Select control module VI；Counter IP kernel A has 48 pins, and it encapsulates figure referring to Fig. 2；
As shown in figure 3, the data input output decomposes storage control module II with command word includes 8 bi-directional datas choosings
Logical triple gate group 1, read-write control module 2, count parameter register 3, counter numbered register 4, mode of operation filtering
Code registers 5, mode control register 6；
8 bi-directional data strobe triple gates group 1 controls mould with 8-bit microprocessor application system I, read-write respectively
Block 2, count parameter register 3, counter numbered register 4, mode of operation filtering code register 5, mode control register 6
Connected with processing and control module IV is counted；
The read-write control module 2 also with 8-bit microprocessor application system I, count parameter register 3, counter
Numbered register 4, mode of operation filtering code register 5, mode control register 6, count processing and control module IV, counter
Overflow indicator control module V and input gate selection control module VI connect；
The count parameter register 3 is also connected with counting processing and control module IV；
The counter numbered register 4 also with 8-bit microprocessor application system I, count processing and control module IV, count
Device overflow indicator control module V and input gate selection control module VI connect；
The mode of operation filtering code register 5 also with 8-bit microprocessor application system I, count processing and control module
IVth, counter overflow mark control module V and input gate selection control module VI connect；
The mode control register 6 also with 8-bit microprocessor application system I, count processing and control module IV and count
Device overflow indicator control module V connects；
The read-write control module 2 that storage control module II is decomposed in the data input output with command word selects letter in piece
Number under the conditions of low level, if write signal is effective, to send 8 write signals of bi-directional data strobe triple gate group 1, gate 8
The data input of the data/address bus of microprocessor application system I；Counter numbering signal is write in generation, and judges that 8-bit microprocessor should
The address value inputted with system I address bus, if the address value of counter parameter, by address value write-in counter numbering
Counter parameter signal is write in register 4, generation, and 8 data of data/address bus are write into count parameter register 3；If meter
Number device order word address, the 2nd of data/address bus ~ the 5th data are write into counter numbered register 4, order word address is
0EH or 0FH, it is 0 to set the 3rd digit counter number value S3, is otherwise provided as 1；If command word least-significant byte address, then order
Word is mode of operation frequency dividing multiple coded command word, and mode of operation frequency dividing multiple coded command word signal is write in generation, and data are total
0th, the 1st, the 6th and the 7th write-in mode of operation frequency dividing multiple code registers 5 of line；If command word most-significant byte
Address, then command word is STATUS control commands word, produce write state control command word signal, by the 0th of data/address bus, the 1st
Position and the 7th write state control register 6；If read signal is effective, sends 8 bi-directional data strobe triple gate groups 1 and read letter
Number, should to 8-bit microprocessor by the data transfer of output data bus inside the counter IP kernel for counting processing and control module IV
With the data/address bus of system I.
As shown in figure 4, the counting processing and control module IV includes rolling counters forward control operation module 44, address strobe
I 45,8 count parameter dual-ported memories 46 are controlled, address strobe controls II 47,8 to count the storage of real-time parameter dual-port
Device 48, address strobe control III 49,4 mode of operation frequency dividing times number encoder dual-ported memories 50, and address strobe controls IV 51,
3 state control dual-ported memories 52,4 count filtering parameter shift memory 53；
The rolling counters forward control operation module 44 controls mould with the frequency divider III of pulse 12, counter overflow mark respectively
Block V, input gate selection control module VI, address strobe control I 45,8 count parameter dual-ported memories 46, address choosing
Logical control II 47,8 counts real-time parameter dual-ported memory 48, address strobe controls III 49,4 mode of operation frequency dividing multiples
Encode dual-ported memory 50, address strobe controls IV 51,3 state control dual-ported memories, 52,4 counting filtering parameters
Shift memory 53, the counting input signal and counting processing control operation clock pulses CLK II of counter IP kernel outside input
Connection；
The address strobe control I 45 also decomposes storage control module II and 8 meters with data input output and command word
Number parameter dual-ported memory 46 connects；
8 count parameter dual-ported memories 46 also decompose storage control module with data input output with command word
II and 8 count real-time parameter dual-ported memories 48 and connect；
The address strobe control II 47 is also decomposed with 8-bit microprocessor application system I, data input output with command word
Storage control module II and 8 counting real-time parameter dual-ported memories 48 connect；
Described 8 count real-time parameter dual-ported memory 48 and also decompose storage control with data input output and command word
Module II connects；
The address strobe control III 49 also decomposes storage control module II and 4 works with data input output with command word
An operation mode frequency dividing times number encoder dual-ported memory 50 connects；
4 mode of operations frequency dividing times number encoder dual-ported memory 50 also decomposes with data input output with command word
Storage control module II connects；
The address strobe control IV 51 also decomposes storage control module II and 3 shapes with data input output with command word
State control dual-ported memory 52 connects；
3 states control dual-ported memory 52 also decomposes storage control module with data input output with command word
IIth, the reset signal connection of 8-bit microprocessor application system I；If the reset signal of input is effective reset signal, reset
3 states control dual-ported memory 52, stop the counting of all counters.
As shown in figure 5, the counter overflow mark control module V includes NOT gate 7, M0 mode of operation bit register groups
8, overflow quenching pulse controller 9, NAND gate I 10, d type flip flop I 11, and door I 12, NAND gate II 13, d type flip flop II 14, with
NOT gate III 15, d type flip flop III 16, and door II 17, NAND gate IV 18, d type flip flop IV 19, NAND gate V 20, d type flip flop V 21,
With door III 22, NAND gate VI 23, d type flip flop VI 24, NAND gate VII 25, d type flip flop VII 26, NAND gate VIII 27, d type flip flop VIII
28, with door IV 29, NAND gate Ⅸ 30, d type flip flop Ⅸ 31, NAND gate Ⅹ 32, d type flip flop Ⅹ 33, with door V 34, NAND gate Ⅺ
35, d type flip flop Ⅺ 36, NAND gate Ⅻ 37, d type flip flop Ⅻ 38, and door VI 39, NAND gate Ⅹ III 40, d type flip flop Ⅹ III 41, with
NOT gate Ⅹ IV 42, d type flip flop Ⅹ IV 43；
The input of the NOT gate 7 is exported with data input and posted with the state control of command word decomposition storage control module II
The M0 output ends connection of storage 6, output end are connected with an input of M0 mode of operation bit registers group 8；
The other three input of M0 mode of operation bit registers group 8 is believed with the reset of 8-bit microprocessor application system I respectively
What number output end, data input output and command word decomposed the read-write control module 2 of storage control module II writes Working mould
Formula filtering code command word signal output part connects with the counter numbering output end of counter numbered register 4, output end point
It is connected not with door I 12, with door II 17, with door III 22, with door IV 29, with door V 34, with an input of door VI 39；
Three inputs for overflowing quenching pulse controller 9 decompose storage control with data input output and command word respectively
The write state control command word signal output part of the read-write control module 2 of module II, the clear spilling of mode control register 6
Mark output end connects with the counter numbering output end of counter numbered register 4, output end difference NAND gate I 10, with it is non-
Door II 13, NAND gate III 15, NAND gate IV 18, NAND gate V 20, NAND gate VI 23, NAND gate VII 25, NAND gate VIII 27, with it is non-
Door Ⅸ 30, NAND gate Ⅹ 32, NAND gate Ⅺ 35, NAND gate Ⅻ 37, NAND gate Ⅹ III 40, an input of NAND gate Ⅹ IV 42
Connection；Output end is also touched with d type flip flop I 11, d type flip flop II 14, d type flip flop III 16, d type flip flop IV 19, d type flip flop V 21, D
Send out device VI 24, d type flip flop VII 26, d type flip flop VIII 28, d type flip flop Ⅸ 31, d type flip flop Ⅹ 33, d type flip flop Ⅺ 36, d type flip flop
Ⅻ 38, d type flip flop Ⅹ III 41 connects with the data input pin of d type flip flop Ⅹ IV 43；
Another input of NAND gate I 10 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop I 11；
The data output end of d type flip flop I 11 and it is connected with another input of door I 12；
With the overflow indicator output signal and 8-bit microprocessor application system of the output end of door I 12 as 16 digit counters 0
I connection；
Another input of NAND gate II 13 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop II 14；
Overflow indicator output signal of the data output end of d type flip flop II 14 as the digit counter 0 of 16 digit counter 1/32
Output end is connected with 8-bit microprocessor application system I；
Another input of NAND gate III 15 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop III 16；
The data output end of d type flip flop III 16 and it is connected with another input of door II 17；
Applied with the output end of door II 17 as the overflow indicator output signal of 16 digit counters 2 with 8-bit microprocessor and be
The connection of system I；
Another input of NAND gate IV 18 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop IV 19；
Overflow indicator output signal of the data output end of d type flip flop IV 19 as the digit counter 1 of 16 digit counter 3/32
Output end is connected with 8-bit microprocessor application system I；
Another input of NAND gate V 20 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop V 21；
The data output end of d type flip flop V 21 and it is connected with another input of door III 22；
Applied with the output end of door III 22 as the overflow indicator output signal of 16 digit counters 4 with 8-bit microprocessor and be
The connection of system I；
Another input of NAND gate VI 23 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop VI 24；
Overflow indicator output signal of the data output end of d type flip flop VI 24 as the digit counter 2 of 16 digit counter 5/32
Output end is connected with 8-bit microprocessor application system I；
Another input of NAND gate VII 25 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop VII 26；
The data output end of d type flip flop VII 26 is micro- as the overflow indicator output signal output end of 16 digit counters 6 and 8
Processor application system I connects；
Another input of NAND gate VIII 27 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop VIII 28；
The data output end of d type flip flop VIII 28 and it is connected with another input of door IV 29；
Applied with the output end of door IV 29 as the overflow indicator output signal of 16 digit counters 7 with 8-bit microprocessor and be
The connection of system I；
Another input of NAND gate Ⅸ 30 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop Ⅸ 31；
Overflow indicator output signal of the data output end of d type flip flop Ⅸ 31 as the digit counter 3 of 16 digit counter 8/32
Output end is connected with 8-bit microprocessor application system I；
Another input of NAND gate Ⅹ 32 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop Ⅹ 33；
The data output end of d type flip flop Ⅹ 33 and it is connected with another input of door V 34；
Applied with the output end of door V 34 as the overflow indicator output signal of 16 digit counters 9 with 8-bit microprocessor and be
The connection of system I；
Another input of NAND gate Ⅺ 35 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop Ⅺ 36；
Overflow indicator output signal of the data output end of d type flip flop Ⅺ 36 as the digit counter 4 of 16 digit counter 10/32
Output end is connected with 8-bit microprocessor application system I；
Another input of NAND gate Ⅻ 37 is connected with counting the overflow indicator output end of processing and control module IV, is exported
End is connected with the clock signal input terminal of d type flip flop Ⅻ 38；
The data output end of d type flip flop Ⅻ 38 and it is connected with an input of door VI 39；
Applied with the output end of door VI 39 as the overflow indicator output signal of 16 digit counters 11 with 8-bit microprocessor and be
The connection of system I；
Another input of NAND gate Ⅹ III 40 is connected with counting the overflow indicator output end of processing and control module IV, defeated
Go out end to be connected with the clock signal input terminal of d type flip flop Ⅹ III 41；
The data output end of d type flip flop Ⅹ III 41 exports letter as the overflow indicator of the digit counter 5 of 16 digit counter 12/32
Number output end is connected with 8-bit microprocessor application system I；
Another input of NAND gate Ⅹ IV 42 is connected with counting the overflow indicator output end of processing and control module IV, defeated
Go out end to be connected with the clock signal input terminal of d type flip flop Ⅹ IV 43；
The data output end of d type flip flop Ⅹ IV 43 is as the overflow indicator output signal output end of 16 digit counter 13 and 8
Microprocessor application system I connects.
Counter IP kernel A counter is with command address coding schedule referring to subordinate list one《With 8-bit microprocessor application system
The counter IP kernel A of connection counter and command address coding schedule》；Mode of operation divides multiple coded command word referring to subordinate list
Two《Counter IP kernel A mode of operation frequency dividing multiple coded command word list》；STATUS control commands word is referring to subordinate list three《Meter
Number device IP kernel A STATUS control commands word list》.
The rolling counters forward control operation program circuit of the counter IP kernel A being connected with 8-bit microprocessor application system
Figure is referring to Fig. 9-1~Fig. 9-3；
A kind of described counter IP kernel being connected with 8-bit microprocessor application system is grasped to realize that rolling counters forward controls
In the method for work, the rolling counters forward control operation concretely comprises the following steps：
s101：Multiple u storage of array unit, the displacement v storage of array units of clear filtering reference clock pulse, counter are compiled
Number value j；
s102：Reference clock pulse trailing edge trigger is filtered to perform 1 time；
s103：Judge whether counter number value j is equal to or more than 1EH, if j value is equal to or more than 1EH, enter
Step s104, otherwise into s105；
s104：Counter number value j=00H, return to step s102 are set；
s105：Judge whether counter number value j is equal to 0EH or 0FH, if j value is equal to 0EH or 0FH, enter
Enter step s106, otherwise into step s107；
s106：Counter number value j=10H is set, into step s107；
s107：Judgement opens/stopped whether signal is equal to 0, if open/stopping signal=0, the counter stops Counts, enters
Step s108, otherwise into step s111；
s108：Judge it is clear count whether currency is equal to 0, if counting currency=0 clearly, into step s109, otherwise
Into step s110；
s109：The value of the clear rolling counters forward currency memory cell, into step s110；
s110：Counter number value j adds 2, return to step s103；
s111：The multiple of the filtering reference clock pulse of the counter adds 1：U (j)=u (j)+1, into step s112；
s112：Judge the counter works pattern, if mode of operation M1M0=10,16 digit counters are gated, into step
s113；If mode of operation M1M0=00,16 digit counters of no gate, into step s118；If mode of operation M1M0=01,
32 digit counters without gate, into step s114；If mode of operation M1M0=11,32 digit counters of gate are selected, are entered
Enter step s115；
s113：Whether the gate-control signal for judging 16 digit counter is 0, the return to step if gate-control signal is equal to 0
S110, otherwise into step s118；
s114：Judge whether low 2 of 32 digit counter number value j be equal to 00, if equal to 00 enters step
S131, otherwise return to step s110；
s115：Judge whether low 2 of 32 digit counter number value j be equal to 00, if equal to 00 enters step
S116, otherwise return to step s110；
s116：Whether the gate-control signal for judging 32 digit counter is 0, enters step if gate-control signal is equal to 0
S117, otherwise into step s131；
s117：Counter number value j adds 4, return to step s103；
s118：Judge the coding of the filtering parameter of 16 digit counter, if filtering parameter is encoded to F2F1=00, enter
Enter step s122；If filtering parameter is encoded to F2F1=01, into step s119；If filtering parameter is encoded to
F2F1=10, then into step s120；If filtering parameter is encoded to F2F1=11, into step s121；
s119：Judge whether the multiple u (j) of the filtering reference clock pulse of 16 digit counter value is equal to 100, if
U (j)=100, then into step s122, otherwise return to step s110；
s120：Judge whether the multiple u (j) of the filtering reference clock pulse of 16 digit counter value is equal to 1000, such as
Fruit u (j)=1000, then into step s122, otherwise return to step s110；
s121：Judge whether the multiple u (j) of the filtering reference clock pulse of 16 digit counter value is equal to 10000, such as
Fruit u (j)=10000, then into step s122, otherwise return to step s110；
s122：The multiple u (j) of the filtering reference clock pulse of 16 digit counter value is set to be equal to 0, into step
s123；
s123：The value of the counting input end of 16 digit counter is read in, v (j) moves to left one, counts input value and enters v (j)
The 0th, into step s124；
s124：Judge the 0th of the 16 digit counter v (j) it is whether equal with the 1st data, if equal, into step
S125, otherwise return to step s110；
s125：Judge the 2nd of the 16 digit counter v (j) it is whether equal with the 3rd data, if equal, into step
S126, otherwise return to step s110；
s126：Judge the 0th of the 16 digit counter v (j) it is whether equal with the 3rd data, if unequal, into step
Rapid s127, otherwise return to step s110；
s127：Judge whether the 0th of the 16 digit counter v (j) be equal to 0, if equal to 0, represent 16 digit counter
Counting input end generate an effectively count pulse, into step s128, otherwise return to step s110；
s128：Read 16 of 16 digit counter to count currencys and add 1, be as a result stored in 16 digit counter 16
Currency memory cell is counted, into step s129；
s129：Judge whether the count value of 16 digit counter produces spilling, enter step s130 if spilling is produced,
Otherwise return to step s110 is entered；
s130：Reload 16 count parameters of 16 digit counter, return to step s110；
s131：Judge the coding of the filtering parameter of 32 digit counter, if filtering parameter is encoded to F2F1=00, enter
Enter step s135；If filtering parameter is encoded to F2F1=01, into step s132；If filtering parameter is encoded to
F2F1=10, then into step s133；If filtering parameter is encoded to F2F1=10, into step s134；
s132:Judge whether the multiple u (j) of the filtering reference clock pulse of 32 digit counter value is equal to 100, if
U (j)=100, then into step s135, otherwise return to step s117；
s133:Judge whether the multiple u (j) of the filtering reference clock pulse of 32 digit counter value is equal to 1000, such as
Fruit u (j)=1000, then into step s135, otherwise into step s117；
s134:Judge whether the multiple u (j) of the filtering reference clock pulse of 32 digit counter value is equal to 10000, such as
Fruit u (j)=10000, then into step s135, otherwise into step s117；
s135:The multiple u (j) of the filtering reference clock pulse of 32 digit counter value is set to be equal to 0, into step
s136；
s136：The value of the counting input end of 32 digit counter is read in, v (j) moves to left one, counts input value and enters v (j)
The 0th, into step s137；
s137：Judge the 0th of the 32 digit counter v (j) it is whether equal with the 1st data, if equal, into step
S138, otherwise return to step s117；
s138：Judge the 2nd of the 32 digit counter v (j) it is whether equal with the 3rd data, if equal, into step
S139, otherwise return to step s117；
s139：Judge the 0th of the 32 digit counter v (j) it is whether equal with the 3rd data, if unequal, into step
Rapid s140, otherwise return to step s117；
s140：Judge whether the 0th of the 32 digit counter v (j) be equal to 0, if equal to 0, represent 32 digit counter
Counting input end generate an effectively count pulse, into step s141, otherwise return to step s117；
s141：Read 32 of 32 digit counter to count currencys and add 1, be as a result stored in the 32 of 32 digit counter
Position counts currency memory cell, into step s142；
s142:Judge whether the count value of 32 digit counter produces spilling, enter step s143 if spilling is produced,
Otherwise return to step s117；
s143：Reload 32 count parameters of 32 digit counter, return to step s117.
Embodiment two：
A kind of counter IP kernel being connected with 8-bit microprocessor application system that 3 32 digit counters of composition can be set
B,（Hereinafter referred to as：Counter IP kernel B）：
The counter IP kernel has 7 16 digit counters, wherein 6 can make up 3 32 digit counters；The counter overflows
Go out to indicate that overflow indicator output signal TF0 ~ 13 of control module V are transformed to overflow indicator output signal TF0 ~ 7, the input
Gate input signal GATE0 ~ 13 of gate selection control module VI are transformed to gate input signal GATE0 ~ 7, referring to Fig. 1；Fig. 2
Counter IP kernel encapsulation figure be transformed to Fig. 6 counter IP kernel encapsulation figure, 62 pins of counter IP kernel are transformed to
42 pins；The 4th of the read-write control module 2 of storage control module II is decomposed in the data input output with command word
Counter number value S3 and counter numbered register 4 connecting line are deleted, referring to Fig. 7；Fig. 5 counter overflow mark
The circuit block diagram of control module V is transformed to the circuit block diagram of Fig. 8 counter overflow mark control module V；Fig. 9-1~Fig. 9-
S105 the and s106 operating procedures of 3 rolling counters forward control operation program flow diagram are deleted, and step s103 is transformed to：Sentence
Whether disconnected counter number value j is equal to or more than 1EH, if j value is equal to or more than 1EH, into step s104, otherwise enters
Enter s107；It changes part referring to Figure 10-1；Remainder is no longer listed with Fig. 9-2~Fig. 9-3 of embodiment one.
The counter and command address code pattern of the counter IP kernel of subordinate list one are transformed to the counter IP kernel of subordinate list four
Counter and command address code pattern；The D5 positions S3 of the mode of operation filtering code command word of subordinate list two is transformed to reserved bit（Ginseng
See attached list five）；The D5 positions S3 of the mode of operation filtering code command word of subordinate list three is transformed to reserved bit（Referring to subordinate list six）.
Embodiment three：
A kind of counter IP kernel being connected with 8-bit microprocessor application system, the frequency divider III of pulse 12 in Fig. 1 determine
The filtering reference clock of each counter input count pulse of counter IP kernel, 50 frequency dividings are transformed to by the frequency divider III of pulse 12
Device III, the clock frequency for adapting to 8-bit microprocessor are more than 12MHz situation.
Example IV：
A kind of counter IP kernel being connected with 8-bit microprocessor application system, the frequency divider III of pulse 12 in Fig. 1 determine
The filtering reference clock of each counter input count pulse of counter IP kernel, 100 points are transformed to by the frequency divider III of pulse 12
Frequency device III, the clock frequency for adapting to 8-bit microprocessor are greatly more than 12MHz situation.
Subordinate list one：Embodiment one《The counter for the counter IP kernel A being connected with 8-bit microprocessor application system and order
Geocoding table》
Subordinate list two：Embodiment one《Counter IP kernel A mode of operation frequency dividing multiple coded command word list》：
Subordinate list three：Embodiment one《Counter IP kernel A STATUS control commands word list》
Subordinate list four：Embodiment two《The counter for the counter IP kernel B being connected with 8-bit microprocessor application system and order
Geocoding table》
Subordinate list five：Embodiment two《Counter IP kernel B mode of operation frequency dividing multiple coded command word list》
Subordinate list six：Embodiment two《Counter IP kernel B STATUS control commands word list》
Claims (4)
1. a kind of counter IP kernel being connected with 8-bit microprocessor application system, the counter IP kernel exports including data input
Storage control module is decomposed with command word（Ⅱ）, the frequency divider of pulse 12（Ⅲ）, count processing and control module（Ⅳ）, counter overflow
Indicate control module（Ⅴ）, input gate selection control module（Ⅵ）；
The data input output decomposes storage control module with command word（Ⅱ）With 8-bit microprocessor application system（Ⅰ）, count
Processing and control module（Ⅳ）, counter overflow mark control module（Ⅴ）Selection control module is gated with input（Ⅵ）Connection；
The frequency divider of pulse 12（Ⅲ）Also with 8-bit microprocessor application system（Ⅰ）With counting processing and control module（Ⅳ）Connection；
The counting processing and control module（Ⅳ）Also with 8-bit microprocessor application system（Ⅰ）, counter overflow mark control module
（Ⅴ）Selection control module is gated with input（Ⅵ）Connection；
The data input output decomposes storage control module with command word（Ⅱ）It is low level bar in the chip selection signal of input
Under part, if write signal is effective, according to 8-bit microprocessor application system（Ⅰ）Given counter or the ground of counter command word
Location, obtain the mode of operation frequency dividing multiple coded command word of counter operation, STATUS control commands word, 16 digit counters or 32
The count parameter of counter, and divide times number encoder and state control difference according to count parameter, counter numbering, mode of operation
Stored and exported, also output write mode of operation frequency dividing multiple coded command word signal, write state control command word signal and
Write counter parameter signal；If read signal is effectively to 8-bit microprocessor application system（Ⅰ）Transmit counter real-time counting value；
The frequency divider of pulse 12（Ⅲ）To 8-bit microprocessor application system（Ⅰ）Clock pulses divided, its export conduct
Count processing and control module（Ⅳ）Rolling counters forward control operation filtering reference clock pulse；
The counting processing and control module（Ⅳ）In the presence of mode of operation frequency dividing multiple coded command word signal is write, according to meter
Number device numbering stores the mode of operation of the counter, the encoded radio of filtering reference clock frequency dividing multiple；In write state control command
In the presence of word signal, the state control signal for storing the counter is numbered according to counter；Writing counter parameter signal
Under effect, the count parameter for storing the counter is numbered according to counter；The counting processing and control module（Ⅳ）In counter
In the presence of the counting processing control operation clock pulses CLK II of IP kernel outside input, control counts processing and control module（Ⅳ）
Operation, according to the frequency divider of pulse 12（Ⅲ）One filtering reference clock pulse cycle completion of output is all to have been turned on counter
Single treatment, include the state control process of each counter, the judgement processing of mode of operation, as of filtering reference clock
When number reaches the filtering reference clock multiple value set by 16/32 digit counters, being read in from counter IP kernel outside should
The counting input signal of counter, a filtering process is carried out, if it is determined that being once effectively count pulse, then to the counting
The real-time counting parameter value of device carries out plus 1 operation, and when producing spilling, count parameter is reloaded automatically to real-time counting parameter value,
And export overflow indicator signal；In data input output storage control module is decomposed with command word（Ⅱ）The chip selection signal of input is
Under the conditions of low level, if read signal is effective, according to 8-bit microprocessor application system（Ⅰ）The address of given counter, directly
The real-time counting parameter value for reading the counter is connect through data input output and command word decomposition storage control module（Ⅱ）Transmission
To 8-bit microprocessor application system（Ⅰ）Data/address bus, the real-time counting parameter of 16 digit counters needs timesharing to be read twice
Go out, the real-time counting parameters of 32 digit counters needs timesharing to be read for four times；In 8-bit microprocessor application system（Ⅰ）Output
Reset signal effect under, stop the counting operations of all counters；
The counter overflow mark control module（Ⅴ）The high level for exporting 16/32 digit counters is believed for effective overflow
Number；Count processing and control module（Ⅳ）When the spill over of 16 digit counters of output is transformed to high level by low level, storage
The counter overflow is masked as high level；If the counter overflow is masked as high level, clear overflow indicator is changed by high level
For low level, store the counter overflow and be masked as low level；Writing the work of mode of operation frequency dividing multiple coded command word signal
Under, counter overflow mark control module（Ⅴ）The information of 32 digit counter mode of operations, envelope are stored according to register number
The flooding information for locking low 16 of 32 digit counter remains low level；
The input gate selection control module（Ⅵ）In the case where writing mode of operation frequency dividing multiple coded command word signal function, according to
Counter numbering stores the mode of operation of the counter, is required according to gate control function determined by the counter works pattern and defeated
The gate level entered, control input gate selection control module（Ⅵ）The gate-control signal of output；
It is characterized in that：The data input output decomposes storage control module with command word（Ⅱ）Selected including 8 bi-directional datas
Logical triple gate group（1）, read-write control module（2）, count parameter register（3）, counter numbered register（4）, work
Pattern Filter code registers（5）, mode control register（6）；
8 bi-directional data strobes triple gate group（1）Respectively with 8-bit microprocessor application system（Ⅰ）, read-write control mould
Block（2）, count parameter register（3）, counter numbered register（4）, mode of operation filtering code register（5）, state control
Register processed（6）With counting processing and control module（Ⅳ）Connection；
The read-write control module（2）Also with 8-bit microprocessor application system（Ⅰ）, count parameter register（3）, count
Device numbered register（4）, mode of operation filtering code register（5）, mode control register（6）, count processing and control module
（Ⅳ）, counter overflow mark control module（Ⅴ）Selection control module is gated with input（Ⅵ）Connection；
The count parameter register（3）Also with counting processing and control module（Ⅳ）Connection；
The counter numbered register（4）Also with 8-bit microprocessor application system（Ⅰ）, count processing and control module（Ⅳ）, meter
Number device overflow indicator control module（Ⅴ）Selection control module is gated with input（Ⅵ）Connection；
The mode of operation filtering code register（5）Also with 8-bit microprocessor application system（Ⅰ）, count processing and control module
（Ⅳ）, counter overflow mark control module（Ⅴ）Selection control module is gated with input（Ⅵ）Connection；
The mode control register（6）Also with 8-bit microprocessor application system（Ⅰ）, count processing and control module（Ⅳ）And meter
Number device overflow indicator control module（Ⅴ）Connection；
The data input output decomposes storage control module with command word（Ⅱ）Read-write control module（2）Select and believe in piece
Number under the conditions of low level, if write signal is effective, to send 8 bi-directional data strobe triple gate groups（1）Write signal, gating 8
Bit microprocessor application system（Ⅰ）The data input of data/address bus；Counter numbering signal is write in generation, and judges 8 microprocessors
Device application system（Ⅰ）The address value of address bus input, if the address value of counter parameter, the address value is write and counted
Device numbered register（4）, counter parameter signal is write in generation, by 8 data write-in count parameter register of data/address bus
（3）；If counter command word address, the 2nd of data/address bus ~ the 5th data are write into counter numbered register
（4）, order word address is 0EH or 0FH, and it is 0 to set the 3rd digit counter number value S3, is otherwise provided as 1；If command word
Least-significant byte address, then command word is mode of operation frequency dividing multiple coded command word, and mode of operation frequency dividing multiple coded command is write in generation
Word signal, by the 0th of data/address bus, the 1st, the 6th and the 7th write-in mode of operation frequency dividing multiple code registers（5）；
If command word most-significant byte address, then command word is STATUS control commands word, write state control command word signal is produced, by number
According to the 0th of bus, the 1st and the 7th write state control register（6）；If read signal is effective, 8 two-way numbers are sent
According to gating triple gate group（1）Read signal, processing and control module will be counted（Ⅳ）Counter IP kernel inside output data bus
Data transfer is to 8-bit microprocessor application system（Ⅰ）Data/address bus.
A kind of 2. counter IP kernel being connected with 8-bit microprocessor application system as claimed in claim 1, it is characterised in that：
The counting processing and control module（Ⅳ）Including rolling counters forward control operation module（44）, address strobe control I（45）, 8
Count parameter dual-ported memory（46）, address strobe control II（47）, 8 counting real-time parameter dual-ported memories（48）,
Address strobe control III（49）, 4 mode of operations frequency dividing times number encoder dual-ported memories（50）, address strobe control IV
（51）, 3 states control dual-ported memories（52）, 4 counting filtering parameter shift memories（53）；
The rolling counters forward control operation module（44）Respectively with the frequency divider of pulse 12（Ⅲ）, counter overflow mark control mould
Block（Ⅴ）, input gate selection control module（Ⅵ）, address strobe control I（45）, 8 count parameter dual-ported memories
（46）, address strobe control II（47）, 8 count real-time parameter dual-ported memory（48）, address strobe control III（49）、4
Position mode of operation frequency dividing times number encoder dual-ported memory（50）, address strobe control IV（51）, 3 state control dual-ports deposit
Reservoir（52）, 4 counting filtering parameter shift memories（53）, the counting input signal and meter of counter IP kernel outside input
Number processing control operation clock pulses CLK II is connected；
The address strobe control I（45）Also storage control module is decomposed with data input output with command word（Ⅱ）With 8 meters
Number parameter dual-ported memory（46）Connection；
8 count parameter dual-ported memories（46）Also storage control module is decomposed with data input output with command word
（Ⅱ）With 8 counting real-time parameter dual-ported memories（48）Connection；
The address strobe control II（47）Also with 8-bit microprocessor application system（Ⅰ）, data input output with command word decompose
Storage control module（Ⅱ）With 8 counting real-time parameter dual-ported memories（48）Connection；
8 countings real-time parameter dual-ported memory（48）Also storage control mould is decomposed with data input output and command word
Block（Ⅱ）Connection；
The address strobe control III（49）Also storage control module is decomposed with data input output with command word（Ⅱ）With 4 works
Operation mode divides times number encoder dual-ported memory（50）Connection；
4 mode of operations divide times number encoder dual-ported memory（50）Also export to decompose with command word with data input and deposit
Store up control module（Ⅱ）Connection；
The address strobe control IV（51）Also storage control module is decomposed with data input output with command word（Ⅱ）With 3 shapes
State controls dual-ported memory（52）Connection；
3 states control dual-ported memory（52）Also storage control module is decomposed with data input output with command word
（Ⅱ）, 8-bit microprocessor application system（Ⅰ）Reset signal connection；If the reset signal of input is effective reset signal,
Reset 3 state control dual-ported memories（52）, stop the counting of all counters.
A kind of 3. counter IP kernel being connected with 8-bit microprocessor application system as claimed in claim 2, it is characterised in that：
The counter overflow mark control module（Ⅴ）Including NOT gate（7）, M0 mode of operation bit register groups（8）, overflow and reset arteries and veins
Rush controller（9）, NAND gate I（10）, d type flip flop I（11）, with door I（12）, NAND gate II（13）, d type flip flop II（14）, with
NOT gate III（15）, d type flip flop III（16）, with door II（17）, NAND gate IV（18）, d type flip flop IV（19）, NAND gate V（20）, D
Trigger V（21）, with door III（22）, NAND gate VI（23）, d type flip flop VI（24）, NAND gate VII（25）, d type flip flop VII
（26）, NAND gate VIII（27）, d type flip flop VIII（28）, with door IV（29）, NAND gate Ⅸ（30）, d type flip flop Ⅸ（31）, NAND gate
Ⅹ（32）, d type flip flop Ⅹ（33）, with door V（34）, NAND gate Ⅺ（35）, d type flip flop Ⅺ（36）, NAND gate Ⅻ（37）, D triggerings
Device Ⅻ（38）, with door VI（39）, NAND gate Ⅹ III（40）, d type flip flop Ⅹ III（41）, NAND gate Ⅹ IV（42）, d type flip flop Ⅹ IV
（43）；
The NOT gate（7）The output of input and data input decompose storage control module with command word（Ⅱ）State control post
Storage（6）The connection of M0 output ends, output end and M0 mode of operation bit register groups（8）An input connection；
M0 mode of operation bit register groups（8）The other three input respectively with 8-bit microprocessor application system（Ⅰ）Reset letter
Number output end, data input output decompose storage control module with command word（Ⅱ）Read-write control module（2）Write work
Operation mode filtering code command word signal output part and counter numbered register（4）Counter numbering output end connection, it is defeated
Go out end respectively with door I（12）And door II（17）And door III（22）And door IV（29）And door V（34）And door VI（39）One
Individual input connection；
Overflow quenching pulse controller（9）Three inputs respectively with data input output with command word decompose storage control mould
Block（Ⅱ）Read-write control module（2）Write state control command word signal output part, mode control register（6）It is clear
Overflow indicator output end and counter numbered register（4）Counter numbering output end connection, output end difference NAND gate I
（10）, NAND gate II（13）, NAND gate III（15）, NAND gate IV（18）, NAND gate V（20）, NAND gate VI（23）, NAND gate
Ⅶ（25）, NAND gate VIII（27）, NAND gate Ⅸ（30）, NAND gate Ⅹ（32）, NAND gate Ⅺ（35）, NAND gate Ⅻ（37）, with it is non-
Door Ⅹ III（40）, NAND gate Ⅹ IV（42）An input connection；Output end also with d type flip flop I（11）, d type flip flop II
（14）, d type flip flop III（16）, d type flip flop IV（19）, d type flip flop V（21）, d type flip flop VI（24）, d type flip flop VII（26）、D
Trigger VIII（28）, d type flip flop Ⅸ（31）, d type flip flop Ⅹ（33）, d type flip flop Ⅺ（36）, d type flip flop Ⅻ（38）, d type flip flop
ⅩⅢ（41）With d type flip flop Ⅹ IV（43）Data input pin connection；
NAND gate I（10）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop I（11）Clock signal input terminal connection；
D type flip flop I（11）Data output end and with door I（12）Another input connection；
With door I（12）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 digit counters 0
（Ⅰ）Connection；
NAND gate II（13）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop II（14）Clock signal input terminal connection；
D type flip flop II（14）Data output end it is defeated as the overflow indicator output signal of the digit counter 0 of 16 digit counter 1/32
Go out end and 8-bit microprocessor application system（Ⅰ）Connection；
NAND gate III（15）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop III（16）Clock signal input terminal connection；
D type flip flop III（16）Data output end and with door II（17）Another input connection；
With door II（17）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 digit counters 2
（Ⅰ）Connection；
NAND gate IV（18）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop IV（19）Clock signal input terminal connection；
D type flip flop IV（19）Data output end it is defeated as the overflow indicator output signal of the digit counter 1 of 16 digit counter 3/32
Go out end and 8-bit microprocessor application system（Ⅰ）Connection；
NAND gate V（20）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop V（21）Clock signal input terminal connection；
D type flip flop V（21）Data output end and with door III（22）Another input connection；
With door III（22）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 digit counters 4
（Ⅰ）Connection；
NAND gate VI（23）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop VI（24）Clock signal input terminal connection；
D type flip flop VI（24）Data output end it is defeated as the overflow indicator output signal of the digit counter 2 of 16 digit counter 5/32
Go out end and 8-bit microprocessor application system（Ⅰ）Connection；
NAND gate VII（25）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop VII（26）Clock signal input terminal connection；
D type flip flop VII（26）Overflow indicator output signal output end and 8 micro- places of the data output end as 16 digit counters 6
Manage device application system（Ⅰ）Connection；
NAND gate VIII（27）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop VIII（28）Clock signal input terminal connection；
D type flip flop VIII（28）Data output end and with door IV（29）Another input connection；
With door IV（29）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 digit counters 7
（Ⅰ）Connection；
NAND gate Ⅸ（30）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop Ⅸ（31）Clock signal input terminal connection；
D type flip flop Ⅸ（31）Data output end it is defeated as the overflow indicator output signal of the digit counter 3 of 16 digit counter 8/32
Go out end and 8-bit microprocessor application system（Ⅰ）Connection；
NAND gate Ⅹ（32）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop Ⅹ（33）Clock signal input terminal connection；
D type flip flop Ⅹ（33）Data output end and with door V（34）Another input connection；
With door V（34）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 digit counters 9
（Ⅰ）Connection；
NAND gate Ⅺ（35）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop Ⅺ（36）Clock signal input terminal connection；
D type flip flop Ⅺ（36）Data output end it is defeated as the overflow indicator output signal of the digit counter 4 of 16 digit counter 10/32
Go out end and 8-bit microprocessor application system（Ⅰ）Connection；
NAND gate Ⅻ（37）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, output
End and d type flip flop Ⅻ（38）Clock signal input terminal connection；
D type flip flop Ⅻ（38）Data output end and with door VI（39）An input connection；
With door VI（39）Overflow indicator output signal and 8-bit microprocessor application system of the output end as 16 digit counters 11
（Ⅰ）Connection；
NAND gate Ⅹ III（40）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, it is defeated
Go out end and d type flip flop Ⅹ III（41）Clock signal input terminal connection；
D type flip flop Ⅹ III（41）Overflow indicator output signal of the data output end as the digit counter 5 of 16 digit counter 12/32
Output end and 8-bit microprocessor application system（Ⅰ）Connection；
NAND gate Ⅹ IV（42）Another input with count processing and control module（Ⅳ）Overflow indicator output end connection, it is defeated
Go out end and d type flip flop Ⅹ IV（43）Clock signal input terminal connection；
D type flip flop Ⅹ IV（43）Data output end it is micro- as the overflow indicator output signal output end of 16 digit counter 13 and 8
Processor application system（Ⅰ）Connection.
4. a kind of counter IP kernel being connected with 8-bit microprocessor application system is used for the method for rolling counters forward control, it is special
Sign is：It is realized with a kind of counter IP kernel being connected with 8-bit microprocessor application system described in claim 3
The method of rolling counters forward control operation；
The rolling counters forward control operation concretely comprises the following steps：
s101：Multiple u storage of array unit, the displacement v storage of array units of clear filtering reference clock pulse, counter number value
j；
s102：Reference clock pulse trailing edge trigger is filtered to perform 1 time；
s103：Judge whether counter number value j is equal to or more than 1EH, if j value is equal to or more than 1EH, into step
S104, otherwise into s105；
s104：Counter number value j=00H, return to step s102 are set；
s105：Judge whether counter number value j is equal to 0EH or 0FH, if j value is equal to 0EH or 0FH, enter step
Rapid s106, otherwise into step s107；
s106：Counter number value j=10H is set, into step s107；
s107：Judgement opens/stopped whether signal is equal to 0, if open/stopping signal=0, the counter stops Counts, into step
S108, otherwise into step s111；
s108：Judge that the clear currency that counts whether equal to 0, if counting currency=0 clearly, into step s109, otherwise enters
Step s110；
s109：The value of the clear rolling counters forward currency memory cell, into step s110；
s110：Counter number value j adds 2, return to step s103；
s111：The multiple of the filtering reference clock pulse of the counter adds 1：U (j)=u (j)+1, into step s112；
s112：Judge the counter works pattern, if mode of operation M1M0=10,16 digit counters are gated, into step
s113；If mode of operation M1M0=00,16 digit counters of no gate, into step s118；If mode of operation M1M0=01,
32 digit counters without gate, into step s114；If mode of operation M1M0=11,32 digit counters of gate are selected, are entered
Enter step s115；
s113：Whether the gate-control signal for judging 16 digit counter is 0, and return to step s110, no if gate-control signal is equal to 0
Then enter step s118；
s114：Judge whether low 2 of 32 digit counter number value j be equal to 00, if equal to 00 enters step s131, it is no
Then return to step s110；
s115：Judge whether low 2 of 32 digit counter number value j be equal to 00, if equal to 00 enters step s116, it is no
Then return to step s110；
s116：Whether the gate-control signal for judging 32 digit counter is 0, no into step s117 if gate-control signal is equal to 0
Then enter step s131；
s117：Counter number value j adds 4, return to step s103；
s118：The coding of the filtering parameter of 16 digit counter is judged, if filtering parameter is encoded to F2F1=00, into step
Rapid s122；If filtering parameter is encoded to F2F1=01, into step s119；If filtering parameter be encoded to F2F1=
10, then into step s120；If filtering parameter is encoded to F2F1=11, into step s121；
s119：Judge whether the multiple u (j) of the filtering reference clock pulse of 16 digit counter value is equal to 100, if u (j)
=100, then into step s122, otherwise return to step s110；
s120：Judge whether the multiple u (j) of the filtering reference clock pulse of 16 digit counter value is equal to 1000, if u
(j)=1000, then into step s122, otherwise return to step s110；
s121：Judge whether the multiple u (j) of the filtering reference clock pulse of 16 digit counter value is equal to 10000, if u
(j)=10000, then into step s122, otherwise return to step s110；
s122：The multiple u (j) of the filtering reference clock pulse of 16 digit counter value is set to be equal to 0, into step s123；
s123：Read in the value of the counting input end of 16 digit counter, v (j) moves to left one, counts input value into the of v (j)
0, into step s124；
s124：Judge the 0th of the 16 digit counter v (j) it is whether equal with the 1st data, if equal, into step
S125, otherwise return to step s110；
s125：Judge the 2nd of the 16 digit counter v (j) it is whether equal with the 3rd data, if equal, into step
S126, otherwise return to step s110；
s126：Judge the 0th of the 16 digit counter v (j) it is whether equal with the 3rd data, if unequal, into step
S127, otherwise return to step s110；
s127：Judge whether the 0th of the 16 digit counter v (j) be equal to 0, if equal to 0, represent the meter of 16 digit counter
Number inputs generate an effectively count pulse, into step s128, otherwise return to step s110；
s128：Read 16 of 16 digit counter to count currencys and add 1, be as a result stored in 16 digit counter, 16 countings
Currency memory cell, into step s129；
s129：Judge whether the count value of 16 digit counter produces spilling, enter step s130 if spilling is produced, otherwise
Into return to step s110；
s130：Reload 16 count parameters of 16 digit counter, return to step s110；
s131：The coding of the filtering parameter of 32 digit counter is judged, if filtering parameter is encoded to F2F1=00, into step
Rapid s135；If filtering parameter is encoded to F2F1=01, into step s132；If filtering parameter be encoded to F2F1=
10, then into step s133；If filtering parameter is encoded to F2F1=10, into step s134；
s132:Judge whether the multiple u (j) of the filtering reference clock pulse of 32 digit counter value is equal to 100, if u
(j)=100, then into step s135, otherwise return to step s117；
s133:Judge whether the multiple u (j) of the filtering reference clock pulse of 32 digit counter value is equal to 1000, if u
(j)=1000, then into step s135, otherwise into step s117；
s134:Judge whether the multiple u (j) of the filtering reference clock pulse of 32 digit counter value is equal to 10000, if u
(j)=10000, then into step s135, otherwise into step s117；
s135:The multiple u (j) of the filtering reference clock pulse of 32 digit counter value is set to be equal to 0, into step s136；
s136：Read in the value of the counting input end of 32 digit counter, v (j) moves to left one, counts input value into the of v (j)
0, into step s137；
s137：Judge the 0th of the 32 digit counter v (j) it is whether equal with the 1st data, if equal, into step
S138, otherwise return to step s117；
s138：Judge the 2nd of the 32 digit counter v (j) it is whether equal with the 3rd data, if equal, into step
S139, otherwise return to step s117；
s139：Judge the 0th of the 32 digit counter v (j) it is whether equal with the 3rd data, if unequal, into step
S140, otherwise return to step s117；
s140：Judge whether the 0th of the 32 digit counter v (j) be equal to 0, if equal to 0, represent the meter of 32 digit counter
Number inputs generate an effectively count pulse, into step s141, otherwise return to step s117；
s141：Read 32 of 32 digit counter to count currencys and add 1, be as a result stored in 32 meters of 32 digit counter
Number currency memory cell, into step s142；
s142:Judge whether the count value of 32 digit counter produces spilling, it is no into step s143 if spilling is produced
Then return to step s117；
s143：Reload 32 count parameters of 32 digit counter, return to step s117.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510376781.9A CN105117357B (en) | 2015-06-30 | 2015-06-30 | A kind of counter IP kernel being connected with 8-bit microprocessor application system and its method for realizing rolling counters forward control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510376781.9A CN105117357B (en) | 2015-06-30 | 2015-06-30 | A kind of counter IP kernel being connected with 8-bit microprocessor application system and its method for realizing rolling counters forward control |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105117357A CN105117357A (en) | 2015-12-02 |
| CN105117357B true CN105117357B (en) | 2018-01-16 |
Family
ID=54665354
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510376781.9A Expired - Fee Related CN105117357B (en) | 2015-06-30 | 2015-06-30 | A kind of counter IP kernel being connected with 8-bit microprocessor application system and its method for realizing rolling counters forward control |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105117357B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107370594A (en) * | 2017-08-15 | 2017-11-21 | 广州星海集成电路基地有限公司 | A kind of SM3 hash AES multimode implementation method and external counter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6157209A (en) * | 1998-12-18 | 2000-12-05 | Xilinx, Inc. | Loadable up-down counter with asynchronous reset |
| CN102323786A (en) * | 2011-07-01 | 2012-01-18 | 广西工学院 | Timer device comprising advanced reduced instruction set computer machine (ARM) and field programmable gate array (FPGA) and implementation method thereof |
| CN102681477A (en) * | 2012-03-09 | 2012-09-19 | 深圳市汇川控制技术有限公司 | System and method for controlling high-speed counting of multiple AB phases of PLC (programmable logic controller) |
| CN204790973U (en) * | 2015-06-30 | 2015-11-18 | 广西科技大学 | Counter IP kernel of being connected with 8 microprocessor application system |
-
2015
- 2015-06-30 CN CN201510376781.9A patent/CN105117357B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6157209A (en) * | 1998-12-18 | 2000-12-05 | Xilinx, Inc. | Loadable up-down counter with asynchronous reset |
| CN102323786A (en) * | 2011-07-01 | 2012-01-18 | 广西工学院 | Timer device comprising advanced reduced instruction set computer machine (ARM) and field programmable gate array (FPGA) and implementation method thereof |
| CN102681477A (en) * | 2012-03-09 | 2012-09-19 | 深圳市汇川控制技术有限公司 | System and method for controlling high-speed counting of multiple AB phases of PLC (programmable logic controller) |
| CN204790973U (en) * | 2015-06-30 | 2015-11-18 | 广西科技大学 | Counter IP kernel of being connected with 8 microprocessor application system |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的PLC并行计数器设计;张炜;《计算机测量与控制》;20130430;第21卷;第1045-1046页，第2节计数器设计，图2 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105117357A (en) | 2015-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN207625572U (en) | One kind being used for Ethernet pattern configurations time-sharing multiplex interface circuit | |
| CN103345448B (en) | Addressing reads one with storage integrated two and writes memory controller | |
| CN105117200B (en) | A kind of counter IP kernel being connected with microprocessor of 16 bit application system and its method for realizing rolling counters forward control | |
| CN105117357B (en) | A kind of counter IP kernel being connected with 8-bit microprocessor application system and its method for realizing rolling counters forward control | |
| CN104571263B (en) | Timer on a kind of piece | |
| CN105183430B (en) | A kind of timer IP kernel being connected with 8-bit microprocessor application system and its realize the time-controlled method of timer | |
| CN103336750B (en) | Addressing dual-port memory controller integrated with storage unit | |
| CN201259629Y (en) | Configurable I/O module for multiple bus interface | |
| CN105022608B (en) | A kind of timer IP kernel being connected with microprocessor of 16 bit application system and its realize the time-controlled method of timer | |
| CN204856462U (en) | Counter IP kernel of being connected with 16 microprocessor application system | |
| CN204790973U (en) | Counter IP kernel of being connected with 8 microprocessor application system | |
| CN106571156B (en) | A kind of interface circuit and method of high-speed read-write RAM | |
| US4433379A (en) | Microcomputer system with input/output unit connected to the remainder of the system by a single multibit bus and several sequential data lines | |
| CN204965405U (en) | Timer IP kernel of being connected with 8 microprocessor application system | |
| CN201021996Y (en) | A micro controller for 8-bit complex instrument set computer | |
| CN106484640A (en) | A kind of high speed serialization user interface circuit based on FPGA and DSP | |
| CN102929591B (en) | Parallel operation logic operation and controller thereof | |
| DE69425546T2 (en) | Dynamically programmable time counting | |
| CN103631559B (en) | Double-instruction multi-floating-point operand division operation controller | |
| CN203386204U (en) | Addressing and storage unit integrated dual-port storage controller | |
| CN203689501U (en) | Multi-floating-point operand addition/subtraction operation controller | |
| CN110334042A (en) | The method for being identified four kinds of port status by the I/0 mouth of MCU and being distinguished peripheral hardware type | |
| CN103645878B (en) | Four mixed fixed point arithmetic operation control unit for multiple operands | |
| CN202339226U (en) | Glass volume meter automatic-calibration device based on communication between single-chip microcomputer and pc (Personal Computer) | |
| CN105429835B (en) | A kind of local bus circuit based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180116 |