CN105183430A

CN105183430A - Timer IP (Intellectual Property) core connected with 8-bit microprocessor application system and method thereof for realizing timing control of timer

Info

Publication number: CN105183430A
Application number: CN201510376687.3A
Authority: CN
Inventors: 余玲; 蔡启仲; 谢友慧; 戴永涛
Original assignee: Guangxi University of Science and Technology; Lushan College of Guangxi University of Science and Technology
Current assignee: Guangxi University of Science and Technology; Lushan College of Guangxi University of Science and Technology
Priority date: 2015-06-30
Filing date: 2015-06-30
Publication date: 2015-12-23
Anticipated expiration: 2035-06-30
Also published as: CN105183430B

Abstract

The invention discloses a timer IP (Intellectual Property) core connected with an 8-bit microprocessor application system. The timer IP core comprises a data input/output and command word decomposition storage control module, a pulse 12 frequency divider, a timing processing control module, a timer overflow flag control module and an input gating selection control module. An FPGA (Field Programmable Gate Array) is applied to design the timer IP core formed by a hard connection control circuit, the timer IP core is provided with fourteen 16-bit timers, wherein twelve 16-bit timers can form six 32-bit timers, one command word sets a working mode and selects the reference clock frequency division multiple of the timer, and the other command word controls a working state. The program execution time of the 8-bit microprocessor is not occupied except that the 8-bit microprocessor carries out the operations, including function and state setting, timing parameter transmission and current timing value reading, on the timer. Each 16-bit/32-bit timer has a function of automatically reloading the timing parameter, so that timing precision is improved. The requirements of the timing of a plurality of timers and the timing control of a system can be met.

Description

A kind of timer IP kernel of being connected with 8-bit microprocessor application system and realize the time-controlled method of timer

Technical field

The present invention relates to a kind of timer IP kernel of being connected with 8-bit microprocessor application system and realize the time-controlled method of timer, particularly relate to a kind of feature based on FPGA parallel processing, application FPGA design Hard link circuit composition the timer IP kernel that can be connected with 8-bit microprocessor application system and for realizing the time-controlled method of timer.

Background technology

Need to apply in the 8-bit microprocessor application system of numerous timer at extensive Time sequence control or other, a large amount of timers will be used, expansion timer number has three kinds of implementations: first kind of way is that the timing of the timer applied in microprocessor is as reference time, employing timer interrupt mode is programmed, timing times number variable is set, this timing times number variable is also the marking variable of expansion timer, programmed method mainly contains 2 kinds, 1st kind of method is that an execution one secondary standard timer interrupt service function timing times number variable adds 1, and compare with the benchmark timing multiple value arranged, if timing times number variable has reached the benchmark timing multiple value of setting, to timing times number variable clear 0, then the program that this expansion timer arrives is performed, or the marking variable of an expansion timer is set specially, when timing times number variable has reached the benchmark timing multiple value of setting, to timing times number variable clear 0, put the marking variable of 1 timer, whether the marking variable judging this timer in the program of principal function is " 1 ", if so, then the marking variable of clear 0 this timer, performs once the process function that this expansion timer arrives, the second way is that microprocessor is connected with timer extended chip, and current timer chip mainly contains 82C54, can expand 3 16 bit timing devices,

There is following weak point in above two kinds of implementations:

1. apply the Interruption method of benchmark timer, CPU responds and exits benchmark timer interrupt service program and takies CPU working time; The timing base time is less, such as 1ms, and timer system needs the timer of expansion more, and will take CPU longer for working time, and produce serious influence to the execution speed of other program module, timing accuracy is not high;

2. the second way adopts microprocessor to extend out Special timer chip, and required timer is more, extends out Special timer chip more, and the circuit scale of 8-bit microprocessor application system is larger;

The third mode adopts non-programmable hardware timing, the independently hardware circuit realization of its each timer; Adopt and realize timing function in this way, required timer is more, and circuit scale is larger, and maintenance workload is large.

Summary of the invention

The object of the invention is to the parallel processing function fully applying FPGA, there is provided a kind of timer IP kernel be connected with 8-bit microprocessor application system based on FPGA and for realizing the time-controlled method of timer, there are 14 16 bit timing devices this timer IP kernel inside, also can apply 12 16 bit timing devices and be set to 6 32 bit timing devices, each 16 bit timing devices or 32 bit timing devices export spill over, can programme and the work of gate-control signal control timer is set, the mode of operation of timer, select the frequency division multiple of four kinds of timer counters, it is high that this timer IP kernel has timing accuracy, only need the working operating mode of two each timers of command set through initialization programming, timing process does not take the time that 8-bit microprocessor program performs, the advantage such as timing and timing controlled quantity being reached to 14 16 bit timing devices or 2 16 bit timing devices and 6 32 bit timing devices can be realized, to overcome the deficiency existing for existing timing mode actualizing technology.

For solving the problems of the technologies described above, the technical scheme that the present invention takes is: a kind of timer IP kernel be connected with 8-bit microprocessor application system, it is characterized in that: this timer IP kernel comprises data input and output and command word decomposes storage control module, pulse 12 frequency divider, Timing Processing control module, timer overflow indicator control module, input gate selects control module;

Described data input and output and command word are decomposed storage control module and 8-bit microprocessor application system, Timing Processing control module, timer overflow indicator control module and are inputted gate and select control module to be connected;

Described pulse 12 frequency divider is also connected with 8-bit microprocessor application system and Timing Processing control module;

Described Timing Processing control module is also with 8-bit microprocessor application system, timer overflow indicator control module with input gate and select control module to be connected;

Described data input and output and command word decompose storage control module under the chip selection signal inputted is low level condition, if write signal is effective, the address of the timer given according to 8-bit microprocessor application system or timer instructs word, obtain the mode of operation frequency division multiple coded command word that timer runs, STATUS control commands word, the timing parameters of 16 bit timing devices or 32 bit timing devices, and according to timing parameters, timer is numbered, mode of operation frequency division times number encoder and state control stored respectively and export, also export and write mode of operation frequency division multiple coded command word signal, write STATUS control commands word signal and write timing device parameter signal, if read signal is effectively to the real-time timing value of 8-bit microprocessor application system transmit timing device,

Described pulse 12 frequency divider carries out frequency division to the time clock of 8-bit microprocessor application system, and it exports the reference clock pulse as the timer timing control operation of Timing Processing control module;

Described Timing Processing control module, under the effect writing mode of operation frequency division multiple coded command word signal, stores the mode of operation of this timer, the encoded radio of reference clock frequency division multiple according to timer numbering, under the effect writing STATUS control commands word signal, store the state control signal of this timer according to timer numbering, under the effect of write timing device parameter signal, store the timing parameters of this timer according to timer numbering, the time clock CLK II of described Timing Processing control module timer IP kernel outside input controls the operation of Timing Processing control module, a Timing Processing of all timers is completed according to a reference clock pulse cycle of pulse 12 frequency divider output, comprise the state control treatment of each timer, the judgement process of mode of operation, the real-time timing parameter value of reference clock multiple value to each 16/32 bit timing devices arranged according to each 16/32 bit timing devices adds 1 operation, when producing spilling, to the automatic heavy cartridges timing parameters of real-time timing parameter value, and export overflow indicator signal, under in data input and output and command word, to decompose chip selection signal that storage control module inputs be low level condition, if read signal is effective, according to the address of the given timer of 8-bit microprocessor application system, the real-time timing parameter value of direct this timer of reading decomposes through data input and output and command word the data bus that storage control module is transferred to 8-bit microprocessor application system, the real-time timing parameters of 16 bit timing devices needs timesharing to be read for twice, and the real-time timing parameters of 32 bit timing devices needs timesharing to be read for four times, under the reset signal effect that 8-bit microprocessor application system exports, stop the fixed cycle operator of all timers,

Described timer overflow indicator control module exports the high level spill over effectively of 16/32 bit timing devices; When the spill over of the 16 bit timing devices that Timing Processing control module exports is transformed to high level by low level, storing this timer overflow indicator is high level; If this timer overflow indicator is high level, clear overflow indicator is converted to low level by high level, and storing this timer overflow indicator is low level; Under the effect writing mode of operation frequency division multiple coded command word signal, timer overflow indicator control module stores the information of 32 bit timing device mode of operations according to register number, and the flooding information blocking this low 16 of 32 bit timing device remains low level;

Described input gate selects control module writing under mode of operation frequency division multiple coded command word signal function, the mode of operation of this timer is stored according to timer numbering, according to the gate level that the determined gate control function of this runs pattern requires and inputs, the gate-control signal that control inputs gate selects control module to export.

Its further technical scheme is: described data input and output and command word are decomposed storage control module and comprised 8 bi-directional data strobe triple gate groups, read-write control module, timing parameter register, timer numbered register, mode of operation frequency division multiple code registers, mode control register;

Described 8 bi-directional data strobe triple gate groups respectively with 8-bit microprocessor application system, read-write control module, timing parameter register, timer numbered register, mode of operation frequency division multiple code registers, mode control register is connected with Timing Processing control module;

Described read-write control module also with 8-bit microprocessor application system, timing parameter register, timer numbered register, mode of operation frequency division multiple code registers, mode control register, Timing Processing control module, timer overflow indicator control module select control module to be connected with input gate;

Described timing parameter register is also connected with Timing Processing control module;

Described timer numbered register is also with 8-bit microprocessor application system, Timing Processing control module, timer overflow indicator control module with input gate and select control module to be connected;

Described mode of operation frequency division multiple code registers is also with 8-bit microprocessor application system, Timing Processing control module, timer overflow indicator control module with input gate and select control module to be connected;

Described mode control register is also connected with 8-bit microprocessor application system, Timing Processing control module and timer overflow indicator control module;

Described data input and output and command word decompose the read-write control module of storage control module under chip selection signal is low level condition, if write signal is effective, send 8 bi-directional data strobe triple gate group write signals, the data input of gating 8-bit microprocessor application system data bus; Produce write timing device numbering signal, and judge the address value of input, if the address value of timer parameter, by this address value write timer numbered register, produce write timing device parameter signal, by the data of data bus write timing parameter register; If timer instructs word address, by the 2nd of data bus the ~ the 5th bit data write timer numbered register, command word address is 0EH or 0FH, and arranging the 3rd bit timing device number value S3 is 0, otherwise is set to 1; If command word least-significant byte address, then command word is mode of operation frequency division multiple coded command word, mode of operation frequency division multiple coded command word signal is write in generation, by the 0th of data bus the, the 1st, the 6th and the 7th write mode of operation frequency division multiple code registers; If command word most-significant byte address, then command word is STATUS control commands word, produces and writes STATUS control commands word signal, by the 0th of data bus the, the 1st and the 7th write state control register; If read signal is effective, send 8 bi-directional data strobe triple gate group read signals, the data of inner for the timer IP kernel of Timing Processing control module output data bus are transferred to the data bus of 8-bit microprocessor application system.

Its further technical scheme be: described Timing Processing control module comprises timer timing control operation module, address strobe controls I, 8 Bit Time Parameters dual-ported memories, address strobe controls II, 8 bit timing real-time parameter dual-ported memories, address strobe controls III, 4 mode of operation frequency division times number encoder dual-ported memories, address strobe controls IV, 3 states and controls dual-ported memory;

Described timer timing control operation module respectively with pulse 12 frequency divider, timer overflow indicator control module, timer overflow indicator control module, address strobe controls I, 8 Bit Time Parameters dual-ported memories, address strobe controls II, 8 bit timing real-time parameter dual-ported memories, address strobe controls III, 4 mode of operation frequency division times number encoder dual-ported memories, address strobe controls IV, 3 states control dual-ported memory and are connected with the Timing Processing controlling run time clock CLK II of timer device IP kernel outside input,

Described address strobe control I also decomposes storage control module with data input and output and command word and 8 Bit Time Parameters dual-ported memories are connected;

Described 8 Bit Time Parameters dual-ported memories also decompose storage control module with data input and output and command word and 8 bit timing real-time parameter dual-ported memories are connected;

Described address strobe control II also decomposes storage control module with 8-bit microprocessor application system, data input and output with command word and 8 bit timing real-time parameter dual-ported memories are connected;

Described 8 bit timing real-time parameter dual-ported memories also decompose storage control module with data input and output and command word and are connected;

Described address strobe control III also decomposes storage control module with data input and output and command word and 4 mode of operation frequency division times number encoder dual-ported memories are connected;

Described 4 mode of operation frequency divisions times number encoder dual-ported memory also decomposes storage control module with data input and output and command word and is connected;

Described address strobe controls IV and also decomposes storage control module and 3 states with data input and output and command word and control dual-ported memory and be connected;

Described 3 states control dual-ported memory also decomposes storage control module with data input and output and command word, the reset signal of 8-bit microprocessor application system is connected; If the reset signal of input is effective reset signal, 3 states that reset control dual-ported memory, stop the fixed cycle operator of all timers.

Its more further technical scheme be: described timer overflow indicator control module comprises not gate, M0 mode of operation bit register group, overflow quenching pulse controller, Sheffer stroke gate I, d type flip flop I, with door I, Sheffer stroke gate II, d type flip flop II, Sheffer stroke gate III, d type flip flop III, with door II, Sheffer stroke gate IV, d type flip flop IV, Sheffer stroke gate V, d type flip flop V, with door III, Sheffer stroke gate VI, d type flip flop VI, Sheffer stroke gate VII, d type flip flop VII, Sheffer stroke gate VIII, d type flip flop VIII, with door IV, Sheffer stroke gate Ⅸ, d type flip flop Ⅸ, Sheffer stroke gate Ⅹ, d type flip flop Ⅹ, with door V, Sheffer stroke gate Ⅺ, d type flip flop Ⅺ, Sheffer stroke gate Ⅻ, d type flip flop Ⅻ, with door VI, Sheffer stroke gate Ⅹ III, d type flip flop Ⅹ III, Sheffer stroke gate Ⅹ IV, d type flip flop Ⅹ IV,

The M0 output terminal that input end and data input and output and the command word of described not gate decompose the mode control register of storage control module is connected, and output terminal is connected with an input end of M0 mode of operation bit register group;

The timer numbering output terminal writing mode of operation frequency division multiple coded command word signal output part and timer numbered register that another three input ends of M0 mode of operation bit register group decompose the read-write control module of storage control module with the reset signal output terminal of 8-bit microprocessor application system, data input and output with command word is respectively connected, and output terminal is respectively with door I, with door II, with door III, with door IV, with door V, be connected with an input end of door VI;

What three input ends overflowing quenching pulse controller decomposed the read-write control module of storage control module respectively with data input and output and command word writes STATUS control commands word signal output part, the clear overflow indicator output terminal of mode control register is connected with the timer numbering output terminal of timer numbered register, output terminal is Sheffer stroke gate I respectively, Sheffer stroke gate II, Sheffer stroke gate III, Sheffer stroke gate IV, Sheffer stroke gate V, Sheffer stroke gate VI, Sheffer stroke gate VII, Sheffer stroke gate VIII, Sheffer stroke gate Ⅸ, Sheffer stroke gate Ⅹ, Sheffer stroke gate Ⅺ, Sheffer stroke gate Ⅻ, Sheffer stroke gate Ⅹ III, an input end of Sheffer stroke gate Ⅹ IV connects, output terminal is also connected with the data input pin of d type flip flop I, d type flip flop II, d type flip flop III, d type flip flop IV, d type flip flop V, d type flip flop VI, d type flip flop VII, d type flip flop VIII, d type flip flop Ⅸ, d type flip flop Ⅹ, d type flip flop Ⅺ, d type flip flop Ⅻ, d type flip flop Ⅹ III and d type flip flop Ⅹ IV,

Another input end of Sheffer stroke gate I is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop I;

The data output end of d type flip flop I and being connected with another input end of door I;

To output signal as the overflow indicator of 16 bit timing devices 0 with the output terminal of door I and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate II is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop II;

The data output end of d type flip flop II is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 bit timing device 1/32 bit timing devices 0;

Another input end of Sheffer stroke gate III is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop III;

The data output end of d type flip flop III and being connected with another input end of door II;

To output signal as the overflow indicator of 16 bit timing devices 2 with the output terminal of door II and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate IV is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop IV;

The data output end of d type flip flop IV is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 bit timing device 3/32 bit timing devices 1;

Another input end of Sheffer stroke gate V is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop V;

The data output end of d type flip flop V and being connected with another input end of door III;

To output signal as the overflow indicator of 16 bit timing devices 4 with the output terminal of door III and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate VI is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop VI;

The data output end of d type flip flop VI is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 bit timing device 5/32 bit timing devices 2;

Another input end of Sheffer stroke gate VII is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop VII;

The data output end of d type flip flop VII is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 bit timing devices 6;

Another input end of Sheffer stroke gate VIII is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop VIII;

The data output end of d type flip flop VIII and being connected with another input end of door IV;

To output signal as the overflow indicator of 16 bit timing devices 7 with the output terminal of door IV and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate Ⅸ is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅸ;

The data output end of d type flip flop Ⅸ is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 bit timing device 8/32 bit timing devices 3;

Another input end of Sheffer stroke gate Ⅹ is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ;

The data output end of d type flip flop Ⅹ and being connected with another input end of door V;

To output signal as the overflow indicator of 16 bit timing devices 9 with the output terminal of door V and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate Ⅺ is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅺ;

The data output end of d type flip flop Ⅺ is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 bit timing device 10/32 bit timing devices 4;

Another input end of Sheffer stroke gate Ⅻ is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅻ;

The data output end of d type flip flop Ⅻ and being connected with an input end of door VI;

To output signal as the overflow indicator of 16 bit timing devices 11 with the output terminal of door VI and be connected with 8-bit microprocessor application system;

Another input end of Sheffer stroke gate Ⅹ III is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ III;

The data output end of d type flip flop Ⅹ III is connected with 8-bit microprocessor application system as the overflow indicator output signal output terminal of 16 bit timing device 12/32 bit timing devices 5;

Another input end of Sheffer stroke gate Ⅹ IV is connected with the overflow indicator output terminal of Timing Processing control module, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ IV;

The data output end of d type flip flop Ⅹ IV is connected with 8-bit microprocessor application system as 16 bit timing device 13 overflow indicator output signal output terminals.

Another relevant technical scheme is: a kind of timer IP kernel is connected with 8-bit microprocessor application system is for realizing the method for timer timing control operation, and it is that the timer IP kernel that is connected of the above-mentioned a kind of and 8-bit microprocessor application system of utilization the present invention is to realize the method for timer timing control operation;

Its concrete steps are:

S101: clear reference clock pulse frequency division multiple u storage of array unit, counter number value j;

S102: reference clock pulse negative edge trigger performs 1 time;

S103: judge whether timer number value j is equal to or greater than 1EH, if the value of j is equal to or greater than 1EH, then enter step s104, otherwise enter s105;

S104: timer number value j=00H is set, returns step s102;

S105: judge whether timer number value j equals 0EH or 0FH, if the value of j equals 0EH or 0FH, then enter step s106, otherwise enter step s107;

S106: timer number value j=10H is set, enters step s107;

S107: judge whether open/stop signal equals 0, if open/stop signal=0, this timer stops timing working, enters step s108, otherwise enters step s111;

S108: judge whether clear timing currency equals 0, if clear timing currency=0, then enter step s109, otherwise enter step s110;

S109: the value removing this timer timing storage unit, enters step s110;

S110: timer number value j adds 2, returns step s103;

S111: the reference clock pulse frequency division multiple of this timer adds 1:u (j)=u (j)+1, enters step s112;

S112: judge this runs pattern, if mode of operation M1M0=10, gate 16 bit timing device, enters step s113; If mode of operation M1M0=00, without 16 bit timing devices of gate, enter step s118; If mode of operation M1M0=01, without 32 bit timing devices of gate, enter step s114; If mode of operation M1M0=11, then select 32 bit timing devices of gate, enter step s115;

S113: whether the gate-control signal judging this 16 bit timing device is 0, if gate-control signal equals 0, returns step s110, otherwise enters step s118;

S114: judge that whether low 2 of this 32 bit timing device numbering j equal 00, if equal 00, enters step s126, otherwise return step s110;

S115: judge that whether low 2 of this 32 bit timing device numbering j equal 00, if equal 00, enters step s116, otherwise return step s110;

S116: whether the gate-control signal judging this 32 bit timing device is 0, if gate-control signal equals 0, enters step s117, otherwise enters step s126;

S117: timer numbering j adds 4:j=j+4, returns step s103;

S118: the coding judging the frequency division multiple of this 16 bit timing device, if frequency division multiple be encoded to F2F1=00, enter step s122; If frequency division multiple be encoded to F2F1=01, then enter step s119; If frequency division multiple be encoded to F2F1=10, then enter step s120; If frequency division multiple be encoded to F2F1=11, then enter step s121;

S119: judge whether the value of reference clock pulse frequency division multiple u (j) of this 16 bit timing device equals 10, if u (j)=10, then enters step s122, otherwise returns step s110;

S120: judge whether the value of reference clock pulse frequency division multiple u (j) of this 16 bit timing device equals 100, if u (j)=100, then enters step s122, otherwise returns step s110;

S121: judge whether the value of reference clock pulse frequency division multiple u (j) of this 16 bit timing device equals 1000, if u (j)=1000, then enters step s122, otherwise returns step s110;

S122: the value arranging reference clock pulse frequency division multiple u (j) of this 16 bit timing device equals 0, enters step s123;

S123: read 16 bit timing currencys of this 16 bit timing device and add 1, result is stored in this 16 bit timing device 16 bit timing currency storage unit, enters step s124;

S124: judge whether the timing value of this 16 bit timing device produces spilling, overflows if produced, enters step s125, otherwise return step s110;

S125: 16 Bit Time Parameters of this 16 bit timing device of reloading, return step s110;

S126: the coding judging the frequency division multiple of this 32 bit timing device, if frequency division multiple be encoded to F2F1=00, enter step s130; If frequency division multiple be encoded to F2F1=01, then enter step s127; If frequency division multiple be encoded to F2F1=10, then enter step s128; If frequency division multiple be encoded to F2F1=10, then enter step s129;

S127: judge whether the value of reference clock pulse frequency division multiple u (j) of this 32 bit timing device equals 10, if u (j)=10, then enters step s130, otherwise returns step s117;

S128: judge whether the value of reference clock pulse frequency division multiple u (j) of this 32 bit timing device equals 100, if u (j)=100, then enters step s130, otherwise returns step s117;

S129: judge whether the value of reference clock pulse frequency division multiple u (j) of this 32 bit timing device equals 1000, if u (j)=1000, then enters step s130, otherwise returns step s117;

S130: the value arranging reference clock pulse frequency division multiple u (j) of this 32 bit timing device equals 0, enters step s131;

S131: read 32 bit timing currencys of this 32 bit timing device and add 1, result is stored in 32 bit timing currency storage unit of this 32 bit timing device, enters step s132;

S132: judge whether the timing value of this 32 bit timing device produces spilling, overflows if produced, enters step s133, otherwise return step s117;

S133: 32 Bit Time Parameters of this 32 bit timing device of reloading, return step s117.

Owing to adopting above structure, the timer IP kernel that a kind of and 8-bit microprocessor application system of the present invention is connected and the method realizing timer timing control operation thereof have following beneficial effect:

1. be connected with 8-bit microprocessor application system, programming Control is convenient

Timer IP kernel of the present invention can directly be connected with 8-bit microprocessor application system, when function setting is carried out to each timer in timer IP kernel, 8-bit microprocessor only needs to send to timer IP kernel the mode of operation that 1 command word can determine this timer, timing base time clock frequency division multiple; Send the timing working that another command word starts this timer, and the whether overflow indicator of this timer clear and whether clearly regularly currency; For 16 bit timing devices, time sharing transmissions most-significant byte and least-significant byte timing parameters; For 32 bit timing devices, need point four transmission 32 Bit Time Parameters; 8-bit microprocessor directly can also read the real-time timing value of this timer according to the address of timer, programming Control timer is convenient.

2. improve timing accuracy, be applicable to the timing of One's name is legion timer and time-controlled system requirements

There are 14 16 bit timing devices timer IP kernel inside of the present invention, 2 16 bit timing devices can be formed 32 bit timing devices by the setting command word that needs according to timing application, composition 6 32 bit timing devices can be set at most, the frequency division multiple of selection four kinds of timing base time clock can also be set; When timing is to generation timing spill over, timer IP kernel of the present invention can automatic reloading timing parameters; Owing to can be arranged the frequency division multiple of the timing base time clock of timer by command word, form 32 bit timing devices, the function of automatic reloading timing parameters, improves timing accuracy, can meet again the timing of One's name is legion timer and time-controlled system requirements.

3.FPGA parallel processing timing, timer IP kernel cost performance is high

The present invention removes 8-bit microprocessor and carries out function setting, timing parameters transmission, timer to software clear timing overflow indicator to timer, read timing currency, and outside the operation of needs clear timing currency, will the program execution time of 8-bit microprocessor do not taken; The timer IP kernel of application FPGA design Hard link circuit composition can reconstruct and become 7 16 bit timing devices, 2 16 bit timing devices can be formed 32 bit timing devices, can arrange at most composition 3 32 bit timing devices; A kind of timer IP kernel be connected with 8-bit microprocessor application system of the present invention and the method realizing timer timing control operation thereof no matter timer clock reference time be how many, the frequency division multiple of four kinds of timing base time clock can be selected, automatic reloading timing parameters, the time that the program taking 8-bit microprocessor performs greatly reduces, use it for the timing of exploitation One's name is legion timer and time-controlled system, very high cost performance can be obtained.

The technical characteristic of the timer IP kernel be connected with 8-bit microprocessor application system a kind of of the present invention below in conjunction with drawings and Examples and the method that realizes timer timing control operation thereof is further described.

Accompanying drawing explanation

Fig. 1: the circuit structure block diagram of the timer IP kernel that a kind of and 8-bit microprocessor application system of the present invention is connected;

The encapsulation figure of Fig. 2: the timer IP kernel A that a kind of and 8-bit microprocessor application system of the embodiment of the present invention one is connected;

Fig. 3: the data input and output of the timer IP kernel that a kind of and 8-bit microprocessor application system of the embodiment of the present invention one is connected and command word decompose the circuit block diagram of storage control module;

Fig. 4: the circuit block diagram of " the Timing Processing control module " of the timer IP kernel that a kind of and 8-bit microprocessor application system of the embodiment of the present invention one is connected;

Fig. 5: the circuit block diagram of " the timer overflow indicator control module " of the timer IP kernel that a kind of and 8-bit microprocessor application system of the embodiment of the present invention one is connected;

The encapsulation figure of Fig. 6: the timer IP kernel B that a kind of and 8-bit microprocessor application system of the embodiment of the present invention two is connected;

The circuit block diagram of " the timer overflow indicator control module " of Fig. 7: the timer IP kernel B that a kind of and 8-bit microprocessor application system of the embodiment of the present invention two is connected;

The timer timing control operation program flow diagram of Fig. 8: the timer IP kernel A that a kind of and 8-bit microprocessor application system of the embodiment one of the present invention is connected;

The timer timing control operation program flow diagram of Fig. 9: the timer IP kernel B that a kind of and 8-bit microprocessor application system of the embodiment of the present invention two is connected.

In figure:

I-8-bit microprocessor application system, the input and output of II-data and command word decompose storage control module, III-pulse 12 frequency divider, IV-Timing Processing control module, V a/ V b-timer overflow indicator control module, VI-input gate selects control module;

1-8 bi-directional data strobe triple gate groups, 2-read-write control module, 3-timing parameter register, 4-timer numbered register, 5-mode of operation frequency division multiple code registers, 6-mode control register;

7-not gate, 8-M0 mode of operation bit register group, 9-overflow quenching pulse controller, 10-Sheffer stroke gate I, 11-d type flip flop I, 12-with door I, 13-Sheffer stroke gate II, 14-d type flip flop II, 15-Sheffer stroke gate III, 16-d type flip flop III, 17-with door II, 18-Sheffer stroke gate IV, 19-d type flip flop IV, 20-Sheffer stroke gate V, 21-d type flip flop V, 22-with door III, 23-Sheffer stroke gate VI, 24-d type flip flop VI, 25-Sheffer stroke gate VII, 26-d type flip flop VII, 27-Sheffer stroke gate VIII, 28-d type flip flop VIII, 29-with door IV, 30-Sheffer stroke gate Ⅸ, 31-d type flip flop Ⅸ, 32-Sheffer stroke gate Ⅹ, 33-d type flip flop Ⅹ, 34-with door V, 35-Sheffer stroke gate Ⅺ, 36-d type flip flop Ⅺ, 37-Sheffer stroke gate Ⅻ, 38-d type flip flop Ⅻ, 39-with door VI, 40-Sheffer stroke gate Ⅹ III, 41-d type flip flop Ⅹ III, 42-Sheffer stroke gate Ⅹ IV,

43-d type flip flop Ⅹ IV, 44-timer timing control operation module, 45-address strobe controls I, 46-8 Bit Time Parameters dual-ported memories, 47-address strobe controls II, 48-8 bit timing real-time parameter dual-ported memories, 49-address strobe controls III, 50-4 mode of operation frequency division times number encoder dual-ported memories, 51-address strobe controls IV, and 52-3 states control dual-ported memory.

In literary composition, abbreviation illustrates:

FPGA-FieldProgrammableGateArray, field programmable gate array;

RD-Read signal, read signal;

CS-ChipSelect signal, chip selection signal;

WR-Write, write signal;

RST-Reset, reset signal;

AB-AddressBus, address bus;

DB-DataBus, data bus;

CLK-Clockpulse, time clock;

The overflow indicator output signal that TF-timing arrives;

GATE-gate input signal;

M0-16/32 bit timing device is encoded, and M0 is " 0 ", 16 bit timing devices; M0 is " 1 ", 32 bit timing devices;

M1-gate mode is encoded, and M1 is " 0 ", without gate input signal control timer; M1 is " 1 ", gate input signal control timer;

The inner input data bus of DB_1-timer IP kernel;

The inner output data bus of DB_2-timer IP kernel;

RD_1-8 position bi-directional data strobe triple gate group read signal;

The real-time timing value read signal of RD_2-;

WR_1-8 position bi-directional data strobe triple gate group write signal;

WR_2-writes mode of operation frequency division multiple coded command word signal;

WR_3-writes STATUS control commands word signal;

WR_4-write timing device parameter signal;

WR_5-write timing device numbering signal;

CLK I-reference clock pulse;

CLK II-Timing Processing controlling run time clock;

S0, S1, S2-the 0th, the 1st, the 2nd bit timing device number value;

S3-the 3rd bit timing device number value;

The gate input signal of GATE0 ~ 13-16 bit timing device 0 ~ 13, wherein the gate input signal of the corresponding 32 bit timing devices 0 ~ 5 of GATE1, GATE3, GATE5, GATE8, GATE10, GATE12 difference;

The overflow indicator that the timing of TF0 ~ 13-16 bit timing device 0 ~ 13 arrives outputs signal, and the overflow indicator that wherein timing of the corresponding 32 bit timing devices 0 ~ 5 of TF1, TF3, TF5, TF8, TF10, TF12 difference arrives outputs signal;

D type flip flop-Dataflip-flop;

D-Datainput, d type flip flop data input pin;

Q-Dataoutput, d type flip flop data output end;

CP-ClockPulseinput, clock signal input terminal.

Embodiment

A kind of timer IP kernel be connected with 8-bit microprocessor application system:

As shown in Figure 1, this timer IP kernel comprises data input and output and command word decomposes storage control module II, pulse 12 frequency divider III, Timing Processing control module IV, timer overflow indicator control module V, and input gate selects control module VI;

Described data input and output and command word decompose storage control module II under the chip selection signal inputted is low level condition, if write signal is effective, the address of the timer given according to 8-bit microprocessor application system I or timer instructs word, obtain the mode of operation frequency division multiple coded command word that timer runs, STATUS control commands word, the timing parameters of 16 bit timing devices or 32 bit timing devices, and according to timing parameters, timer is numbered, mode of operation frequency division times number encoder and state control stored respectively and export, also export and write mode of operation frequency division multiple coded command word signal, write STATUS control commands word signal and write timing device parameter signal, if read signal is effectively to the real-time timing value of 8-bit microprocessor application system I transmit timing device,

Described pulse 12 frequency divider III is for carrying out frequency division to the time clock of 8-bit microprocessor application system I, and it exports the reference clock pulse as the timer timing control operation of Timing Processing control module IV;

Described Timing Processing control module IV, under the effect writing mode of operation frequency division multiple coded command word signal, stores the mode of operation of this timer, the encoded radio of reference clock frequency division multiple according to timer numbering, under the effect writing STATUS control commands word signal, store the state control signal of this timer according to timer numbering, under the effect of write timing device parameter signal, store the timing parameters of this timer according to timer numbering, the time clock CLK II of described Timing Processing control module IV timer IP kernel outside input controls the operation of Timing Processing control module, a Timing Processing of all timers is completed according to a reference clock pulse cycle of pulse 12 frequency divider III output, comprise the state control treatment of each timer, the judgement process of mode of operation, the real-time timing parameter value of reference clock multiple value to each 16/32 bit timing devices arranged according to each 16/32 bit timing devices adds 1 operation, when producing spilling, to the automatic heavy cartridges timing parameters of real-time timing parameter value, and export overflow indicator signal, under in data input and output and command word, to decompose chip selection signal that storage control module II inputs be low level condition, if read signal is effective, according to the address of the given timer of 8-bit microprocessor application system I, the real-time timing parameter value of direct this timer of reading decomposes through data input and output and command word the data bus that storage control module II is transferred to 8-bit microprocessor application system I, the real-time timing parameters of 16 bit timing devices needs timesharing to be read for twice, and the real-time timing parameters of 32 bit timing devices needs timesharing to be read for four times, under the reset signal effect that 8-bit microprocessor application system I exports, stop the fixed cycle operator of all timers,

Described timer overflow indicator control module V is for exporting the high level spill over effectively of 16/32 bit timing devices; When the spill over of the 16 bit timing devices that Timing Processing control module IV exports is transformed to high level by low level, storing this timer overflow indicator is high level; If this timer overflow indicator is high level, clear overflow indicator is converted to low level by high level, and storing this timer overflow indicator is low level; Under the effect writing mode of operation frequency division multiple coded command word signal, timer overflow indicator control module V stores the information of 32 bit timing device mode of operations according to register number, and the flooding information blocking this low 16 of 32 bit timing device remains low level;

Described input gate selects control module VI writing under mode of operation frequency division multiple coded command word signal function, the mode of operation of this timer is stored according to timer numbering, according to the gate level that the determined gate control function of this runs pattern requires and inputs, the gate-control signal that control inputs gate selects control module VI to export;

Described data input and output and command word are decomposed storage control module II and 8-bit microprocessor application system I, Timing Processing control module IV, timer overflow indicator control module V and are inputted gate and select control module VI to be connected;

Described pulse 12 frequency divider III is also connected with 8-bit microprocessor application system I and Timing Processing control module IV;

Described Timing Processing control module IV is also with 8-bit microprocessor application system I, timer overflow indicator control module V with input gate and select control module VI to be connected.

In order to applicable One's name is legion timer timing and time-controlled system requirements, according to the needs of different timings application, the timer IP kernel of the figure place that setting command word encapsulation composition is different, therefore, there are following several embodiments: such as 2 16 bit timing devices can be formed 32 bit timing devices, composition 6 32 bit timing devices can be set at most, frequency division multiple of selection four kinds of timing base time clock etc. can also be set; Below be described below.

Embodiment one:

The timer IP kernel A be connected with 8-bit microprocessor application system of composition 6 32 bit timing devices can be set, (hereinafter referred to as: timer IP kernel A):

As mentioned above, the timer IP kernel A that should be connected with 8-bit microprocessor application system comprises data input and output and command word decomposes storage control module II, pulse 12 frequency divider III, Timing Processing control module IV, timer overflow indicator control module V, input gate selects control module VI (see Fig. 1), and this timer IP kernel A has 48 pins, and figure is see Fig. 2 in its encapsulation;

As shown in Figure 3, described data input and output and command word are decomposed storage control module II and are comprised 8 bi-directional data strobe triple gate groups 1, read-write control module 2, timing parameter register 3, timer numbered register 4, mode of operation frequency division multiple code registers 5, mode control register 6;

Described 8 bi-directional data strobe triple gate groups 1 respectively with 8-bit microprocessor application system I, read-write control module 2, timing parameter register 3, timer numbered register 4, mode of operation frequency division multiple code registers 5, mode control register 6 is connected with Timing Processing control module IV;

Described read-write control module 2 also with 8-bit microprocessor application system I, timing parameter register 3, timer numbered register 4, mode of operation frequency division multiple code registers 5, mode control register 6, Timing Processing control module IV, timer overflow indicator control module V select control module VI to be connected with input gate;

Described timing parameter register 3 is also connected with Timing Processing control module IV;

Described timer numbered register 4 is also with 8-bit microprocessor application system I, Timing Processing control module IV, timer overflow indicator control module V with input gate and select control module VI to be connected;

Described mode of operation frequency division multiple code registers 5 is also with 8-bit microprocessor application system I, Timing Processing control module IV, timer overflow indicator control module V with input gate and select control module VI to be connected;

Described mode control register 6 is also connected with 8-bit microprocessor application system I, Timing Processing control module IV and timer overflow indicator control module V.

As shown in Figure 4, described Timing Processing control module IV comprises timer timing control operation module 44, address strobe controls I 45,8 Bit Time Parameters dual-ported memories 46, address strobe controls II 47,8 bit timing real-time parameter dual-ported memories 48, address strobe controls III 49,4 mode of operation frequency division times number encoder dual-ported memories 50, address strobe controls IV 51,3 states and controls dual-ported memory 52;

Described timer timing control operation module 44 respectively with pulse 12 frequency divider III, timer overflow indicator control module V, timer overflow indicator control module V, address strobe controls I 45, 8 Bit Time Parameters dual-ported memories 46, address strobe controls II 47, 8 bit timing real-time parameter dual-ported memories 48, address strobe controls III 49, 4 mode of operation frequency division times number encoder dual-ported memories 50, address strobe controls IV 51 and is connected with the Timing Processing controlling run time clock CLK II of timer device IP kernel outside input with 3 states control dual-ported memories 52,

Described address strobe control I 45 also decomposes storage control module II with data input and output and command word and 8 Bit Time Parameters dual-ported memories 46 are connected;

Described 8 Bit Time Parameters dual-ported memories 46 also decompose storage control module II with data input and output and command word and 8 bit timing real-time parameter dual-ported memories 48 are connected;

Described address strobe control II 47 also decomposes storage control module II with 8-bit microprocessor application system I, data input and output with command word and 8 bit timing real-time parameter dual-ported memories 48 are connected;

Described 8 bit timing real-time parameter dual-ported memories 48 also decompose storage control module II with data input and output and command word and are connected;

Described address strobe control III 49 also decomposes storage control module II with data input and output and command word and 4 mode of operation frequency division times number encoder dual-ported memories 50 are connected;

Described 4 mode of operation frequency divisions times number encoder dual-ported memory 50 also decomposes storage control module II with data input and output and command word and is connected;

Described address strobe controls IV 51 and also decomposes storage control module II and 3 states with data input and output and command word and control dual-ported memory 52 and be connected;

Described 3 states control dual-ported memory 52 also decomposes storage control module II with data input and output and command word, the reset signal of 8-bit microprocessor application system I is connected; If the reset signal of input is effective reset signal, 3 states that reset control dual-ported memory 52, stop the fixed cycle operator of all timers.

As shown in Figure 5, described timer overflow indicator control module V comprises not gate 7, M0 mode of operation bit register group 8, overflow quenching pulse controller 9, Sheffer stroke gate I 10, d type flip flop I 11, with door I 12, Sheffer stroke gate II 13, d type flip flop II 14, Sheffer stroke gate III 15, d type flip flop III 16, with door II 17, Sheffer stroke gate IV 18, d type flip flop IV 19, Sheffer stroke gate V 20, d type flip flop V 21, with door III 22, Sheffer stroke gate VI 23, d type flip flop VI 24, Sheffer stroke gate VII 25, d type flip flop VII 26, Sheffer stroke gate VIII 27, d type flip flop VIII 28, with door IV 29, Sheffer stroke gate Ⅸ 30, d type flip flop Ⅸ 31, Sheffer stroke gate Ⅹ 32, d type flip flop Ⅹ 33, with door V 34, Sheffer stroke gate Ⅺ 35, d type flip flop Ⅺ 36, Sheffer stroke gate Ⅻ 37, d type flip flop Ⅻ 38, with door VI 39, Sheffer stroke gate Ⅹ III 40, d type flip flop Ⅹ III 41, Sheffer stroke gate Ⅹ IV 42, d type flip flop Ⅹ IV 43,

The M0 output terminal that input end and data input and output and the command word of described not gate 7 decompose the mode control register 6 of storage control module II is connected, and output terminal is connected with an input end of M0 mode of operation bit register group 8;

The timer numbering output terminal writing mode of operation frequency division multiple coded command word signal output part and timer numbered register 4 that another three input ends of M0 mode of operation bit register group 8 decompose the read-write control module 2 of storage control module II with the reset signal output terminal of 8-bit microprocessor application system I, data input and output with command word is respectively connected, and output terminal is respectively with door I 12, with door II 17, with door III 22, with door IV 29, with door V 34, be connected with an input end of door VI 39;

What three input ends overflowing quenching pulse controller 9 decomposed the read-write control module 2 of storage control module II respectively with data input and output and command word writes STATUS control commands word signal output part, the clear overflow indicator output terminal of mode control register 6 is connected with the timer numbering output terminal of timer numbered register 4, output terminal is Sheffer stroke gate I 10 respectively, Sheffer stroke gate II 13, Sheffer stroke gate III 15, Sheffer stroke gate IV 18, Sheffer stroke gate V 20, Sheffer stroke gate VI 23, Sheffer stroke gate VII 25, Sheffer stroke gate VIII 27, Sheffer stroke gate Ⅸ 30, Sheffer stroke gate Ⅹ 32, Sheffer stroke gate Ⅺ 35, Sheffer stroke gate Ⅻ 37, Sheffer stroke gate Ⅹ III 40, an input end of Sheffer stroke gate Ⅹ IV 42 connects, output terminal is also connected with the data input pin of d type flip flop I 11, d type flip flop II 14, d type flip flop III 16, d type flip flop IV 19, d type flip flop V 21, d type flip flop VI 24, d type flip flop VII 26, d type flip flop VIII 28, d type flip flop Ⅸ 31, d type flip flop Ⅹ 33, d type flip flop Ⅺ 36, d type flip flop Ⅻ 38, d type flip flop Ⅹ III 41 and d type flip flop Ⅹ IV 43,

Another input end of Sheffer stroke gate I 10 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop I 11;

The data output end of d type flip flop I 11 and being connected with another input end of door I 12;

To output signal as the overflow indicator of 16 bit timing devices 0 with the output terminal of door I 12 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate II 13 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop II 14;

The data output end of d type flip flop II 14 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 bit timing device 1/32 bit timing devices 0;

Another input end of Sheffer stroke gate III 15 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop III 16;

The data output end of d type flip flop III 16 and being connected with another input end of door II 17;

To output signal as the overflow indicator of 16 bit timing devices 2 with the output terminal of door II 17 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate IV 18 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop IV 19;

The data output end of d type flip flop IV 19 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 bit timing device 3/32 bit timing devices 1;

Another input end of Sheffer stroke gate V 20 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop V 21;

The data output end of d type flip flop V 21 and being connected with another input end of door III 22;

To output signal as the overflow indicator of 16 bit timing devices 4 with the output terminal of door III 22 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate VI 23 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop VI 24;

The data output end of d type flip flop VI 24 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 bit timing device 5/32 bit timing devices 2;

Another input end of Sheffer stroke gate VII 25 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop VII 26;

The data output end of d type flip flop VII 26 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 bit timing devices 6;

Another input end of Sheffer stroke gate VIII 27 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop VIII 28;

The data output end of d type flip flop VIII 28 and being connected with another input end of door IV 29;

To output signal as the overflow indicator of 16 bit timing devices 7 with the output terminal of door IV 29 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate Ⅸ 30 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅸ 31;

The data output end of d type flip flop Ⅸ 31 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 bit timing device 8/32 bit timing devices 3;

Another input end of Sheffer stroke gate Ⅹ 32 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ 33;

The data output end of d type flip flop Ⅹ 33 and being connected with another input end of door V 34;

To output signal as the overflow indicator of 16 bit timing devices 9 with the output terminal of door V 34 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate Ⅺ 35 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅺ 36;

The data output end of d type flip flop Ⅺ 36 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 bit timing device 10/32 bit timing devices 4;

Another input end of Sheffer stroke gate Ⅻ 37 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅻ 38;

The data output end of d type flip flop Ⅻ 38 and being connected with an input end of door VI 39;

To output signal as the overflow indicator of 16 bit timing devices 11 with the output terminal of door VI 39 and be connected with 8-bit microprocessor application system I;

Another input end of Sheffer stroke gate Ⅹ III 40 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ III 41;

The data output end of d type flip flop Ⅹ III 41 is connected with 8-bit microprocessor application system I as the overflow indicator output signal output terminal of 16 bit timing device 12/32 bit timing devices 5;

Another input end of Sheffer stroke gate Ⅹ IV 42 is connected with the overflow indicator output terminal of Timing Processing control module IV, and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ IV 43;

The data output end of d type flip flop Ⅹ IV 43 is connected with 8-bit microprocessor application system I as 16 bit timing device 13 overflow indicator output signal output terminals.

The timer of this timer IP kernel A with command address coding schedule see subordinate list one " timer of the timer IP kernel A be connected with 8-bit microprocessor application system and command address coding schedule "; Mode of operation frequency division multiple coded command word is see subordinate list two " the mode of operation frequency division multiple coded command word complete list of timer IP kernel A "; STATUS control commands word is see subordinate list three " the STATUS control commands word complete list of timer IP kernel A ".

The timer IP kernel A that should be connected with 8-bit microprocessor application system is for realizing the program flow diagram of the method for timer timing control operation see Fig. 8;

Its concrete steps are:

S102: reference clock pulse negative edge trigger performs 1 time;

S104: timer number value j=00H is set, returns step s102;

S106: timer number value j=10H is set, enters step s107;

S109: the value removing this timer timing storage unit, enters step s110;

S110: timer number value j adds 2, returns step s103;

S117: timer numbering j adds 4:j=j+4, returns step s103;

Embodiment two:

The timer IP kernel B be connected with 8-bit microprocessor application system of composition 3 32 bit timing devices can be set, (hereinafter referred to as: timer IP kernel B):

This timer IP kernel B has 34 pins, and figure is see Fig. 6 in its encapsulation;

The basic structure of this timer IP kernel B, with embodiment one, is with embodiment one difference: this timer IP kernel B has 7 16 bit timing devices, and wherein 6 can form 3 32 bit timing devices; Overflow indicator output signal TF0 ~ 13 of described timer overflow indicator control module V are transformed to overflow indicator output signal TF0 ~ 7, described input gate selects gate input signal GATE0 ~ 13 of control module VI to be transformed to gate input signal GATE0 ~ 7, see Fig. 1; The connecting line of the 4th bit timing device number value S3 and timer numbered register 4 that described data input and output and command word decompose the read-write control module 2 of storage control module II is deleted; The circuit block diagram of timer overflow indicator control module V b is see Fig. 7.

The timer of timer IP kernel B and command address coding schedule are see subordinate list four " timer of timer IP kernel B and command address coding schedule "; Mode of operation frequency division multiple coded command word is see subordinate list five " the mode of operation frequency division multiple coded command word complete list of timer IP kernel B "; STATUS control commands word is see subordinate list six " the STATUS control commands word complete list of timer IP kernel B ".

This timer IP kernel B is for realizing the program flow diagram of timer timing control operation see Fig. 9; Be with the timer timing control operation program flow diagram difference of timer IP kernel A: timer IP kernel A s105 and s106 operation steps deleted, step s103 is transformed to: judge whether timer number value j is equal to or greater than 1EH, if the value of j is equal to or greater than 1EH, then enter step s104, otherwise enter s107.

Embodiment three:

A kind of timer IP kernel be connected with 8-bit microprocessor application system, pulse 12 frequency divider III in Fig. 1 determines the timing base clock of timer IP kernel, pulse 12 frequency divider III is transformed to 50 frequency dividers III, and the clock frequency adapting to 8-bit microprocessor is greater than the situation of 12MHz.

Embodiment four:

A kind of timer IP kernel be connected with 8-bit microprocessor application system, pulse 12 frequency divider III in Fig. 1 determines the timing base clock of timer IP kernel, pulse 12 frequency divider III is transformed to 100 frequency dividers III, and the clock frequency adapting to 8-bit microprocessor is greater than the situation of 12MHz greatly.

Subordinate list one:

" timer of the timer IP kernel A be connected with 8-bit microprocessor application system and command address coding schedule "

Subordinate list two: " the mode of operation frequency division multiple coded command word complete list of timer IP kernel A "

Subordinate list three: " the STATUS control commands word complete list of timer IP kernel A "

Subordinate list four: " timer of timer IP kernel B and command address coding schedule "

Subordinate list five: " the mode of operation frequency division multiple coded command word complete list of timer IP kernel B "

Subordinate list six: " the STATUS control commands word complete list of timer IP kernel B "

Claims

1. the timer IP kernel be connected with 8-bit microprocessor application system, it is characterized in that: this timer IP kernel comprises data input and output and command word decomposes storage control module (II), pulse 12 frequency divider (III), Timing Processing control module (IV), timer overflow indicator control module (V), input gate selects control module (VI);

Described data input and output and command word are decomposed storage control module (II) and 8-bit microprocessor application system (I), Timing Processing control module (IV), timer overflow indicator control module (V) and are inputted gate and select control module (VI) to be connected;

Described pulse 12 frequency divider (III) is also connected with 8-bit microprocessor application system (I) and Timing Processing control module (IV);

Described Timing Processing control module (IV) is also with 8-bit microprocessor application system (I), timer overflow indicator control module (V) with input gate and select control module (VI) to be connected;

Described data input and output and command word decompose storage control module (II) under the chip selection signal inputted is low level condition, if write signal is effective, the timer given according to 8-bit microprocessor application system (I) or the address of timer instructs word, obtain the mode of operation frequency division multiple coded command word that timer runs, STATUS control commands word, the timing parameters of 16 bit timing devices or 32 bit timing devices, and according to timing parameters, timer is numbered, mode of operation frequency division times number encoder and state control stored respectively and export, also export and write mode of operation frequency division multiple coded command word signal, write STATUS control commands word signal and write timing device parameter signal, if read signal is effectively to the real-time timing value of 8-bit microprocessor application system (I) transmit timing device,

The time clock of described pulse 12 frequency divider (III) to 8-bit microprocessor application system (I) carries out frequency division, and it exports the reference clock pulse as the timer timing control operation of Timing Processing control module (IV);

Described Timing Processing control module (IV), under the effect writing mode of operation frequency division multiple coded command word signal, stores the mode of operation of this timer, the encoded radio of reference clock frequency division multiple according to timer numbering, under the effect writing STATUS control commands word signal, store the state control signal of this timer according to timer numbering, under the effect of write timing device parameter signal, store the timing parameters of this timer according to timer numbering, the time clock CLK II of described Timing Processing control module (IV) timer IP kernel outside input controls the operation of Timing Processing control module, the reference clock pulse cycle exported according to pulse 12 frequency divider (III) completes a Timing Processing of all timers, comprise the state control treatment of each timer, the judgement process of mode of operation, the real-time timing parameter value of reference clock multiple value to each 16/32 bit timing devices arranged according to each 16/32 bit timing devices adds 1 operation, when producing spilling, to the automatic heavy cartridges timing parameters of real-time timing parameter value, and export overflow indicator signal, under in data input and output and command word, to decompose chip selection signal that storage control module (II) inputs be low level condition, if read signal is effective, according to the address of the given timer of 8-bit microprocessor application system (I), the real-time timing parameter value of direct this timer of reading decomposes through data input and output and command word the data bus that storage control module (II) is transferred to 8-bit microprocessor application system (I), the real-time timing parameters of 16 bit timing devices needs timesharing to be read for twice, the real-time timing parameters of 32 bit timing devices needs timesharing to be read for four times, under the reset signal effect that 8-bit microprocessor application system (I) exports, stop the fixed cycle operator of all timers,

Described timer overflow indicator control module (V) exports the high level spill over effectively of 16/32 bit timing devices; When the spill over of the 16 bit timing devices that Timing Processing control module (IV) exports is transformed to high level by low level, storing this timer overflow indicator is high level; If this timer overflow indicator is high level, clear overflow indicator is converted to low level by high level, and storing this timer overflow indicator is low level; Under the effect writing mode of operation frequency division multiple coded command word signal, timer overflow indicator control module (V) stores the information of 32 bit timing device mode of operations according to register number, and the flooding information blocking this low 16 of 32 bit timing device remains low level;

Described input gate selects control module (VI) writing under mode of operation frequency division multiple coded command word signal function, the mode of operation of this timer is stored according to timer numbering, according to the gate level that the determined gate control function of this runs pattern requires and inputs, the gate-control signal that control inputs gate selects control module (VI) to export.

2. a kind of timer IP kernel be connected with 8-bit microprocessor application system as claimed in claim 1, it is characterized in that: described data input and output and command word are decomposed storage control module (II) and comprised 8 bi-directional data strobe triple gate groups (1), read-write control module (2), timing parameter register (3), timer numbered register (4), mode of operation frequency division multiple code registers (5), mode control register (6);

Described 8 bi-directional data strobe triple gate groups (1) respectively with 8-bit microprocessor application system (I), read-write control module (2), timing parameter register (3), timer numbered register (4), mode of operation frequency division multiple code registers (5), mode control register (6) is connected with Timing Processing control module (IV);

Described read-write control module (2) also with 8-bit microprocessor application system (I), timing parameter register (3), timer numbered register (4), mode of operation frequency division multiple code registers (5), mode control register (6), Timing Processing control module (IV), timer overflow indicator control module (V) select control module (VI) to be connected with input gate;

Described timing parameter register (3) is also connected with Timing Processing control module (IV);

Described timer numbered register (4) is also with 8-bit microprocessor application system (I), Timing Processing control module (IV), timer overflow indicator control module (V) with input gate and select control module (VI) to be connected;

Described mode of operation frequency division multiple code registers (5) is also with 8-bit microprocessor application system (I), Timing Processing control module (IV), timer overflow indicator control module (V) with input gate and select control module (VI) to be connected;

Described mode control register (6) is also connected with 8-bit microprocessor application system (I), Timing Processing control module (IV) and timer overflow indicator control module (V);

Described data input and output and command word decompose the read-write control module (2) of storage control module (II) under chip selection signal is low level condition, if write signal is effective, send 8 bi-directional data strobe triple gate group (1) write signals, the data input of gating 8-bit microprocessor application system (I) data bus; Produce write timing device numbering signal, and judge the address value of input, if the address value of timer parameter, by this address value write timer numbered register (4), produce write timing device parameter signal, by the data of data bus write timing parameter register (3); If timer instructs word address, by the 2nd of data bus the ~ the 5th bit data write timer numbered register (4), command word address is 0EH or 0FH, and arranging the 3rd bit timing device number value S3 is 0, otherwise is set to 1; If command word least-significant byte address, then command word is mode of operation frequency division multiple coded command word, mode of operation frequency division multiple coded command word signal is write in generation, by the 0th of data bus the, the 1st, the 6th and the 7th write mode of operation frequency division multiple code registers (5); If command word most-significant byte address, then command word is STATUS control commands word, produces and writes STATUS control commands word signal, by the 0th of data bus the, the 1st and the 7th write state control register (6); If read signal is effective, send 8 bi-directional data strobe triple gate group (1) read signals, the data of inner for the timer IP kernel of Timing Processing control module (IV) output data bus are transferred to the data bus of 8-bit microprocessor application system (I).

3. a kind of timer IP kernel be connected with 8-bit microprocessor application system as claimed in claim 2, it is characterized in that: described Timing Processing control module (IV) comprises timer timing control operation module (44), address strobe controls I (45), 8 Bit Time Parameters dual-ported memories (46), address strobe controls II (47), 8 bit timing real-time parameter dual-ported memories (48), address strobe controls III (49), 4 mode of operation frequency division times number encoder dual-ported memories (50), address strobe controls IV (51), 3 states control dual-ported memory (52),

Described timer timing control operation module (44) respectively with pulse 12 frequency divider (III), timer overflow indicator control module (V), timer overflow indicator control module (V), address strobe controls I (45), 8 Bit Time Parameters dual-ported memories (46), address strobe controls II (47), 8 bit timing real-time parameter dual-ported memories (48), address strobe controls III (49), 4 mode of operation frequency division times number encoder dual-ported memories (50), address strobe controls IV (51), 3 states control dual-ported memory (52) and are connected with the Timing Processing controlling run time clock CLK II of timer device IP kernel outside input,

Described address strobe control I (45) also decomposes storage control module (II) with data input and output and command word and 8 Bit Time Parameters dual-ported memories (46) are connected;

Described 8 Bit Time Parameters dual-ported memories (46) also decompose storage control module (II) with data input and output and command word and 8 bit timing real-time parameter dual-ported memories (48) are connected;

Described address strobe control II (47) also decomposes storage control module (II) with 8-bit microprocessor application system (I), data input and output with command word and 8 bit timing real-time parameter dual-ported memories (48) are connected;

Described 8 bit timing real-time parameter dual-ported memories (48) also decompose storage control module (II) with data input and output and command word and are connected;

Storage control module (II) is also decomposed in described address strobe control III (49) with data input and output and command word and 4 mode of operation frequency division times number encoder dual-ported memories (50) are connected;

Described 4 mode of operation frequency divisions times number encoder dual-ported memory (50) also decomposes storage control module (II) with data input and output and command word and is connected;

Described address strobe controls IV (51) and also decomposes storage control module (II) and 3 states with data input and output and command word and control dual-ported memory (52) and be connected;

Described 3 states control dual-ported memory (52) also decompose storage control module (II) with data input and output and command word, the reset signal of 8-bit microprocessor application system (I) is connected; If the reset signal of input is effective reset signal, 3 states that reset control dual-ported memory (52), stop the fixed cycle operator of all timers.

4. a kind of timer IP kernel be connected with 8-bit microprocessor application system as claimed in claim 3, it is characterized in that: described timer overflow indicator control module (V) comprises not gate (7), M0 mode of operation bit register group (8), overflow quenching pulse controller (9), Sheffer stroke gate I (10), d type flip flop I (11), with door I (12), Sheffer stroke gate II (13), d type flip flop II (14), Sheffer stroke gate III (15), d type flip flop III (16), with door II (17), Sheffer stroke gate IV (18), d type flip flop IV (19), Sheffer stroke gate V (20), d type flip flop V (21), with door III (22), Sheffer stroke gate VI (23), d type flip flop VI (24), Sheffer stroke gate VII (25), d type flip flop VII (26), Sheffer stroke gate VIII (27), d type flip flop VIII (28), with door IV (29), Sheffer stroke gate Ⅸ (30), d type flip flop Ⅸ (31), Sheffer stroke gate Ⅹ (32), d type flip flop Ⅹ (33), with door V (34), Sheffer stroke gate Ⅺ (35), d type flip flop Ⅺ (36), Sheffer stroke gate Ⅻ (37), d type flip flop Ⅻ (38), with door VI (39), Sheffer stroke gate Ⅹ III (40), d type flip flop Ⅹ III (41), Sheffer stroke gate Ⅹ IV (42), d type flip flop Ⅹ IV (43),

The M0 output terminal that input end and data input and output and the command word of described not gate (7) decompose the mode control register (6) of storage control module (II) is connected, and output terminal is connected with an input end of M0 mode of operation bit register group (8);

Another three input ends of M0 mode of operation bit register group (8) respectively with the reset signal output terminal of 8-bit microprocessor application system (I), the timer numbering output terminal writing mode of operation frequency division multiple coded command word signal output part and timer numbered register (4) that data input and output and command word decompose the read-write control module (2) of storage control module (II) is connected, output terminal respectively with door I (12), with door II (17), with door III (22), with door IV (29), with door V (34), be connected with an input end of door VI (39),

What three input ends overflowing quenching pulse controller (9) decomposed the read-write control module (2) of storage control module (II) respectively with data input and output and command word writes STATUS control commands word signal output part, the clear overflow indicator output terminal of mode control register (6) is connected with the timer numbering output terminal of timer numbered register (4), output terminal is Sheffer stroke gate I (10) respectively, Sheffer stroke gate II (13), Sheffer stroke gate III (15), Sheffer stroke gate IV (18), Sheffer stroke gate V (20), Sheffer stroke gate VI (23), Sheffer stroke gate VII (25), Sheffer stroke gate VIII (27), Sheffer stroke gate Ⅸ (30), Sheffer stroke gate Ⅹ (32), Sheffer stroke gate Ⅺ (35), Sheffer stroke gate Ⅻ (37), Sheffer stroke gate Ⅹ III (40), an input end of Sheffer stroke gate Ⅹ IV (42) connects, output terminal is also connected with the data input pin of d type flip flop I (11), d type flip flop II (14), d type flip flop III (16), d type flip flop IV (19), d type flip flop V (21), d type flip flop VI (24), d type flip flop VII (26), d type flip flop VIII (28), d type flip flop Ⅸ (31), d type flip flop Ⅹ (33), d type flip flop Ⅺ (36), d type flip flop Ⅻ (38), d type flip flop Ⅹ III (41) and d type flip flop Ⅹ IV (43),

Another input end of Sheffer stroke gate I (10) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop I (11);

The data output end of d type flip flop I (11) and being connected with another input end of door I (12);

To output signal as the overflow indicator of 16 bit timing devices 0 with the output terminal of door I (12) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate II (13) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop II (14);

The data output end of d type flip flop II (14) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 bit timing device 1/32 bit timing devices 0;

Another input end of Sheffer stroke gate III (15) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop III (16);

The data output end of d type flip flop III (16) and being connected with another input end of door II (17);

To output signal as the overflow indicator of 16 bit timing devices 2 with the output terminal of door II (17) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate IV (18) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop IV (19);

The data output end of d type flip flop IV (19) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 bit timing device 3/32 bit timing devices 1;

Another input end of Sheffer stroke gate V (20) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop V (21);

The data output end of d type flip flop V (21) and being connected with another input end of door III (22);

To output signal as the overflow indicator of 16 bit timing devices 4 with the output terminal of door III (22) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate VI (23) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop VI (24);

The data output end of d type flip flop VI (24) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 bit timing device 5/32 bit timing devices 2;

Another input end of Sheffer stroke gate VII (25) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop VII (26);

The data output end of d type flip flop VII (26) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 bit timing devices 6;

Another input end of Sheffer stroke gate VIII (27) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop VIII (28);

The data output end of d type flip flop VIII (28) and being connected with another input end of door IV (29);

To output signal as the overflow indicator of 16 bit timing devices 7 with the output terminal of door IV (29) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate Ⅸ (30) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅸ (31);

The data output end of d type flip flop Ⅸ (31) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 bit timing device 8/32 bit timing devices 3;

Another input end of Sheffer stroke gate Ⅹ (32) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ (33);

The data output end of d type flip flop Ⅹ (33) and being connected with another input end of door V (34);

To output signal as the overflow indicator of 16 bit timing devices 9 with the output terminal of door V (34) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate Ⅺ (35) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅺ (36);

The data output end of d type flip flop Ⅺ (36) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 bit timing device 10/32 bit timing devices 4;

Another input end of Sheffer stroke gate Ⅻ (37) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅻ (38);

The data output end of d type flip flop Ⅻ (38) and being connected with an input end of door VI (39);

To output signal as the overflow indicator of 16 bit timing devices 11 with the output terminal of door VI (39) and be connected with 8-bit microprocessor application system (I);

Another input end of Sheffer stroke gate Ⅹ III (40) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ III (41);

The data output end of d type flip flop Ⅹ III (41) is connected with 8-bit microprocessor application system (I) as the overflow indicator output signal output terminal of 16 bit timing device 12/32 bit timing devices 5;

Another input end of Sheffer stroke gate Ⅹ IV (42) is connected with the overflow indicator output terminal of Timing Processing control module (IV), and output terminal is connected with the clock signal input terminal of d type flip flop Ⅹ IV (43);

The data output end of d type flip flop Ⅹ IV (43) is connected with 8-bit microprocessor application system (I) as 16 bit timing device 13 overflow indicator output signal output terminals.

5. the timer IP kernel be connected with 8-bit microprocessor application system, for realizing a method for timer timing control operation, is characterized in that: it uses a kind of timer IP kernel be connected with 8-bit microprocessor application system according to claim 4 to realize the method for timer timing control operation;

Its concrete steps are:

S102: reference clock pulse negative edge trigger performs 1 time;

S104: timer number value j=00H is set, returns step s102;

S106: timer number value j=10H is set, enters step s107;

S109: the value removing this timer timing storage unit, enters step s110;

S110: timer number value j adds 2, returns step s103;

S117: timer numbering j adds 4:j=j+4, returns step s103;