CN103345448A

CN103345448A - Two-read-out and one-read-in storage controller integrating addressing and storage

Info

Publication number: CN103345448A
Application number: CN2013102885128A
Authority: CN
Inventors: 蔡启仲; 余玲; 李克俭; 潘绍明; 李静; 黄仕林; 孙培燕
Original assignee: Guangxi University of Science and Technology
Current assignee: Guangxi University of Science and Technology
Priority date: 2013-07-10
Filing date: 2013-07-10
Publication date: 2013-10-09
Anticipated expiration: 2033-07-10
Also published as: CN103345448B

Abstract

A two-read-out and one-read-in storage controller integrating addressing and storage comprises a two-read-out and one-read-in storage unit, a command storage and address temporary storage control module, a combinational logic circuit module, a pulse distributor_1, a data transmission control module, an address channel control module_1, a command storage control module, a pulse distributor_2, a data transmission and read arbitration control module and an address channel control module_2. The integrated storage controller is provided with a read-write port and an independent read-out port having the read operation arbitration function. A hard-wired circuit of an FPGA is applied, commands or addresses or immediate operands needing to be read in are read in from a system bus, under the control of internal temporal pulses, direct and indirect addressing of base addresses and modify addresses of the immediate operands and reading and writing of the storage unit are autonomously finished according to the command requirements, data transmission between storage units is finished, a microprocessor can read out two operands at the same time when executing operate class commands, and execution of a command sequence is accelerated.

Description

Addressing is read one with storage integrated two and is write memory controller

Technical field

The present invention relates to a kind of addressing and read one and write memory controller with storage integrated two, relate in particular to and a kind ofly read operation control circuit and a sequential control thereof that writes memory controller based on the hardwired addressing of FPGA parallel work-flow circuit and storage integrated two.

Background technology

Storer is the prerequisite parts of each microprocessor, no matter be the storer that is embedded in the microprocessor chip, still microprocessor is by the storer that extends out of system bus connection, comprise the register group of microprocessor internal etc., all have the reading and writing operating function, but function singleness, namely according to the microprocessor internal address bus, or the address value of outside system address bus, directly register or the storage unit of this address are carried out read-write operation.The addressing process of these storeies and register is to be finished by microprocessor, adds other comparatively complicated addressing modes such as indexed addressing for indirect addressing, plot, also relates to the calculating of address, the processes such as transmission of address date; And the data transmission each other of the storage unit in the storer, need transfer realization storage unit data transmission each other in the some registers by microprocessor internal, namely need two transfer instructions can finish the data transmission of the some storage unit in the storer to another storage unit; The addressing process of storer and register, the process of the data transmission each other of the storage unit in the storer will spend the clock cycle of microprocessor, increase the burden of microprocessor execution of program instructions stream, be unfavorable for improving the speed of execution command sequence.On the other hand, for the microprocessor computing class instruction that two source operands and a destination operand are arranged, in two source operands one can be counting immediately of arranging of instruction itself, the a certain storage unit that also can come from certain register or storer, another comes from a certain storage unit of register or storer, and destination operand can be a certain storage unit of certain register or storer; Not the situation of same register for destination operand and source operand, need timesharing to carry out two transfer instructions and transmit two source operands; Two kinds of situations are arranged when being same register for destination operand and a source operand, a kind of is that a source operand comes from the operation result of carrying out a last instruction, this source operand itself just directly in the register of a source operand of this operational order, only needs to carry out a transfer instruction; Second kind of situation is that two operands are not to come from the operation result of carrying out a last instruction, also needs timesharing to carry out two transfer instructions and transmits two source operands; The addressing process that two source operand instructions of transmission and every transfer instruction are carried out in timesharing is to influence microprocessor to carry out one of factor of computing class instruction speed.

Summary of the invention

The object of the present invention is to provide a kind of addressing to read one with storage integrated two and write memory controller, this integrated memory controller is chosen by system, read in order from system bus, what the address maybe needed to write counts immediately, under the control of the time sequential pulse of internal pulses divider, independently finish the address computation of order defined, the operating function of addressing and read-write, do not need microprocessor that addressing process and write operation are carried out any processing again, just can realize storage unit data transmission each other, can two read operations of executed in parallel, when carrying out the instruction of computing class, addressing simultaneously and read two source operands; Fully used the parallel processing processing capacity of FPGA, realization two is read one and is write the operation of order and the parallel processing of microprocessor instruction sequence implementation.

The technical scheme that solves the problems of the technologies described above is: a kind of addressing is read one and write memory controller with storage integrated two, it is characterized in that: this integrated two is read one and writes memory controller and comprise that two read a write storage unit, command register and address temporary control module, combinational logic circuit module, pulsqe distributor _ 1, Data Transmission Controlling module, address tunnel control module _ 1, command register control module, pulsqe distributor _ 2, data transmission and read to arbitrate control module and address tunnel control module _ 2;

Described two read the temporary control module of a write storage unit and command register and address, Data Transmission Controlling module, address tunnel control module _ 1, command register control module, data transmission and read to arbitrate control module and are connected with address tunnel control module _ 2;

The temporary control module in described command register and address also is connected with combinational logic circuit module, pulsqe distributor _ 1, Data Transmission Controlling module and address tunnel control module _ 1;

Described combinational logic circuit module also is connected with pulsqe distributor _ 1, Data Transmission Controlling module and address tunnel control module _ 1;

Described pulsqe distributor _ 1 also is connected with address tunnel control module _ 1 with the Data Transmission Controlling module;

Described Data Transmission Controlling module also with address tunnel control module _ 1 and data transmission with read to arbitrate control module and be connected;

Described address tunnel control module _ 1 also with data transmission with read to arbitrate control module and be connected;

Described command register control module also is connected with address tunnel control module _ 2 with pulsqe distributor _ 2;

Described pulsqe distributor _ 2 also with data transmission with read to arbitrate control module and be connected with address tunnel control module _ 2;

Described data transmission with read to arbitrate control module and also be connected with address tunnel control module _ 2;

Described two read a write storage unit a data reading-writing port, one independently data read port; The function of reading and writing data port is identical with normal memory, and independently to read the function of port identical with the data read out function of normal memory for data; Described two read to be provided with in the write storage unit as indirect addressing and plot and add the storage unit R that indexed addressing is used ₀-R ₁₅

Control module is kept in described command register and address, the combinational logic circuit module, and pulsqe distributor _ 1, the Data Transmission Controlling module, address tunnel control module _ 1 realizes that described two read the control function of a data reading-writing port of a write storage unit;

The temporary control module in described command register and address is when CS_1 is " 0 ", under the effect of the WR_1 of system signal, store instruction codes and decoding, storage are indirectly and the address value of base addressing memory unit address value, side-play amount and directly address and being exported, if also have the address value of the 2nd directly address, then under the effect of second WR_1 signal of system, store the address value of the 2nd directly address and exported; Send WR1 or WR2 pulse signal as the starting impulse signal of pulsqe distributor _ 1 work; When carrying out normal memory read-write function command, reset pulse divider _ 1; When the temporary control module in described command register and address was reset, all order output terminals were " 1 "; Read data transfer command between two storage unit in the write storage unit for the order that writes data or two, after the command parameter of this order write the temporary control module of described command register and address, CS_1 was by " 0 " → " 1 ";

The input end of described combinational logic circuit module is connected with 11 order output terminals of the temporary control module of command register and address, and also the pulse output end with pulsqe distributor _ 1 is connected; The output terminal of described combinational logic circuit module is the logical combination of these input signals, comprising: with logic output and or logic output, described and logic output have by with the door XII ~ with 17 and a gate output terminal of door XX VIII formation; The output of described or logic have by or door IX ~ or door XXX 22 or gate output terminal constituting;

Described pulsqe distributor _ 1 is as inner sequence timer, output pulse 1., pulse 2., pulse is 3., pulse 4., pulse 5., pulse 6., pulse is 7., pulse 8., 8 pulses are output as the combinational logic circuit module, the Data Transmission Controlling module, and address tunnel control module _ 1 provides the time sequential pulse signal; And to the temporary control module output of command register and address reset signal;

Described Data Transmission Controlling module is at the WR2 signal of addressing function control _ 1 signal, RD_1, WR_1, the temporary control module output of command register and address, and under the combinational logic circuit module and the effect logic output valve, realize that two read the DB_11 of a write storage unit and the Data Transmission Controlling of DB_1 bus; And under the time sequential pulse and the effect combinational logic circuit module or the logic output valve of pulsqe distributor _ 1 output, realize reading the RD_11 of a write storage unit and the control of WR_11 pulse to two according to performed instruction and order;

Described address tunnel control module _ 1 under the effect of the time sequential pulse of the output logic value of combinational logic circuit module and pulsqe distributor _ 1 output, according to the address value of the temporary control module output of command register and address and performed instruction and order to the two AB_11 transport address values of reading a write storage unit;

Described command register control module; Pulsqe distributor _ 2, data transmission with read to arbitrate control module, address tunnel control module _ 2 realize described two read a write storage unit another independently data read the control function of port and the function of read data arbitration;

Described command register control module when CS_2 is " 0 ", under the effect of WR_2 signal, store instruction codes and decoding, indirectly and base addressing memory unit address value and side-play amount and exported; When described command register control module was reset, 2 order output terminals were " 1 ";

Pulse is exported as inner sequence timer in described pulsqe distributor _ 2 1. _ 2, and pulse 2. _ 2, pulse 3. _ 2, pulse 4. _ 2, pulse is 5. _ 2,5 pulses are output as data transmission and read to arbitrate control module, and address tunnel control module _ 2 provide the time sequential pulse signal; And to command register control module output reset signal;

Described data transmission with read to arbitrate control module under the effect of the time sequential pulse of addressing function control _ 2, RD_2 and pulsqe distributor _ 2 outputs, realize that two read the DB_21 of a write storage unit and the Data Transmission Controlling of DB_2 bus; Described data transmission with read to arbitrate control module at two WR_11 that read a write storage unit during for " 0 ", compare AB_11 address value and AB_21 address value, if two address values equate and described two read a write storage unit this independently data read port and be in the read operation process, then block the generation of RD_21 read pulse, send look-at-me output; If two address values are unequal, under the effect of the time sequential pulse of described pulsqe distributor _ 2 output, realize the normal read operation of instruction and two orders;

Described address tunnel control module _ 2 according to the address value of the time sequential pulse of pulsqe distributor _ 2 output and the output of command register control module and performed instruction and order to the two AB_21 transport address values of reading a write storage unit.

Its further technical scheme is: the temporary control module in described command register and address comprises+1 counter, command register I, command decoder I, address register I, address register II, not gate I, not gate II and with the door I;

The RESET input of described+1 counter is connected with the output terminal of not gate I, Enable Pin is connected with the CS_1 signal wire, counting input end is connected with the WR_1 signal, if the CS_1 signal is " 0 ", the RESET input is " 1 ", and under the effect of WR_1 pulse signal ,+1 counter carries out+1 operation, first+1 operation output WR1, it is worth from " 1 " → " 0 "; Second WR_1 count pulse makes WR1 from " 0 " → " 1 "; WR2 is from " 1 " → " 0 "; If the CS_1 signal is " 1 " ,+1 counter is reset, and WR1 and WR2 are one state; The WR1 pulse output end of+1 counter is connected with pulsqe distributor _ 1 with the write signal input end of command register I, address register I, and the WR2 pulse output end is connected with write signal input end, pulsqe distributor _ 1 and the Data Transmission Controlling module of address register II;

The Enable Pin of described command register I is connected with the CS_1 signal wire; Reset terminal is connected with pulsqe distributor _ _ 1; Data input pin is connected with DB_1; Command code (the D of described command register I ₃₁-D ₂₆) output terminal is connected with the command information input end of command decoder I; The R of the indirect addressing storage unit of described command register I output _i(D ₂₅-D ₂₂) and R _{J_1}(D ₂₁-D ₁₈) address value, side-play amount sft_1 (D ₁₇~ D ₂) be connected with address tunnel control module _ 1 as the OPADD signal; When the command register I is reset, the command code output terminal all is " 1 ";

Shown in the order output terminal of command decoder I be connected with the combinational logic circuit module; 11 command decoder values of command decoder I output when carrying out any order, have only this order output terminal to be " 0 ", and other order output terminal is " 1 "; When the command code output terminal of command register I all is " 1 "; The all order output terminals of command decoder I are " 1 ";

Shown in the input end of address register I be connected with AB_1, the address value output terminal is connected with address tunnel control module _ 1;

Shown in the input end of address register II be connected with AB_1, the address value output terminal is connected with address tunnel control module _ 1;

The input end of not gate I is connected with the CS_1 signal wire;

The input end of not gate II is connected with pulsqe distributor _ 1; Output terminal be connected with an input end of door I;

Be connected with the CS_1 signal wire with another input end of door I; The CS_11 signal input part that output terminal and two is read a write storage unit is connected.

Its further technical scheme is: described pulsqe distributor _ 1 comprise the pulse producer I, with the door II or the door I or the door II and with the door III;

The RESET input of described pulse producer I is connected with output terminal with the door II; The enabling signal pulse input end is connected with output terminal with the door III; Clock pulse input terminal is connected with the system clock line, pulse 9. output terminal be connected with an input end of door II; Pulse 1., pulse 2., pulse 3., pulse 4., pulse 5., pulse 6., pulse 7., pulse 8. output terminal be connected with the combinational logic circuit module; Pulse 1., pulse 2., pulse 4. output terminal also be connected with address tunnel control module _ 1; Pulse 2. output terminal also is connected with the Data Transmission Controlling module;

Is connected with addressing function control _ 1 with input end of door II, other three input ends also respectively and or door XX IX or an XXX or an IX be connected;

Or the door I two input ends respectively with WR1 be connected with door XX VIII, output terminal be connected with an input end of door III;

Or the door II two input ends respectively with WR2 be connected with door XX VII, output terminal be connected with an input end of door III;

The enabling signal pulse input end of described pulse producer I is changed to " 0 " by " 1 ", and the RESET input is when being " 1 ", and the pulse producer I is activated work.

Its further technical scheme is: described Data Transmission Controlling module comprise data working storage triple gate group, 32 triple gate group I, 32 triple gate group II or door III or door IV or door V or door VI or door VII or door VIII, with a door IV, with the door V and with the door VI;

The data input pin of described data working storage triple gate group is connected with DB_1; Data write pulse input end with or the door III output terminal be connected; Output gating input end and or the output terminal of a V be connected; The DB_11 end that data output end and two is read a write storage unit is connected;

The data input pin of 32 triple gate group I is connected with DB_1; Output gating input end and or the output terminal of a VI be connected; The DB_11 end that data output end and two is read a write storage unit is connected;

The DB_11 end that the data input pin and two of 32 triple gate group II is read a write storage unit is connected; Output gating input end is connected with output terminal with the door IV; Data output end is connected with DB_1;

Or two input ends of door III respectively with the WR2 pulse output end of+1 counter be connected with door XX VI;

Or two input ends of door IV respectively with door XX VI, be connected with an XX V; Output terminal with or the door V an input end be connected;

Or the door V another input end be connected with door XX VI;

Or two input ends of door VI are connected with WR_1 with addressing function control _ 1 respectively; Output terminal also with an input end of door V is connected;

Or two input ends of door VII are connected with system RD_1 line with addressing function control _ 1 respectively; Output terminal be connected with an input end of door IV;

Or three input ends of door VIII respectively with RD_1, with XII be connected with door XX V; Output terminal be connected with an input end of door IV;

Also with an input end of door VI be connected with the output terminal of door IV;

With other four input ends of door V also respectively with or door X V or door X IV or door X III with or a door XII be connected; The WR_11 input end that output terminal and two is read a write storage unit is connected;

With other three input ends of door VI also respectively with pulse 2. or the door XI with or a door X be connected; The RD_11 input end that output terminal and two is read a write storage unit is connected.

Its further technical scheme is: described address tunnel control module _ 1 comprise 4 alternative selector switchs, 32 three select a selector switch I, 32 alternative selector switch I, address arithmetic device I, 32 alternative selector switch II, address output latch I, address output latch II, address output latch III, 32 four select a selector switch, with a door VII, with a door VIII, with a door IX, with the door X and with door X I;

The R of described 4 alternative selector switchs _iThe R of address input end and command register I _iAddress output end connects; R _jThe R of _ 1 address input end and command register I _j_ 1 address output end connects; The gating control input end with or a door X VI be connected; Output terminal is connected with low 4 an of input end of 32 alternative selector switch I;

32 three are selected an input end of a selector switch I to be connected with the two DB_11 ends of reading a write storage unit; An input end is connected with the address value output terminal of address register I; An input end is connected with the address value output terminal of address register II; Gating end is connected with output terminal with the door VII; Gating end with or a door X IX be connected; Output terminal is connected with an input end of 32 alternative selector switch I;

High 28 of an input end of 32 alternative selector switch I are connected with " 0 "; The gating end is connected with output terminal with the door VIII; Address output end is connected with an input end of address arithmetic device I and an input end of 32 alternative selector switch II;

Another side-play amount sft_1 input end of address arithmetic device I is connected with the sft_1 output terminal of command register; Address arithmetic output terminal as a result is connected with an input end of 32 alternative selector switch II;

The gating input end of 32 alternative selector switch II is connected with the output terminal with the door IX; Address output end is connected with address output latch I, address output latch II and the address input end of address output latch III;

The latch pulse input end of address output latch I is connected with the output terminal with the door X; Output terminal selects an input end of a selector switch to be connected with 32 four;

2. the latch pulse input end of address output latch II is connected with pulse; Output terminal selects an input end of a selector switch to be connected with 32 four;

4. the latch pulse input end of address output latch III is connected with pulse; Output terminal selects an input end of a selector switch to be connected with 32 four;

32 four are selected an input end of a selector switch also to be connected with AB_1; A gating end is connected with addressing function control _ 1; Gating end is connected with output terminal with door X I; Gating end with or the output terminal of door XX VIII be connected; The AB_11 input end that output terminal and two is read a write storage unit is connected;

With two input ends of door VII respectively with or door X VII or a door X VIII be connected;

With two input ends of door VIII respectively with or door XX or a door X XI be connected;

With two input ends of door IX respectively with or door X XII or a door XX III be connected;

With three input ends of door X respectively with pulse 1. or door XX IV with or a door XX V be connected;

With three input ends of door XI respectively with door X XII or door XX VI with or a door XX VII be connected.

Its further technical scheme is: described command register control module comprise command register II, command decoder II, not gate III and with door XX IX;

The Enable Pin of described command register II is connected with the CS_2 signal wire; Reset terminal is connected with pulsqe distributor _ 2; Data input pin is connected with DB_2; Writing pulse input end is connected with WR_2; The CS_2 signal is " 0 ", and the RESET input is " 1 ", and under the effect of WR_2 pulse signal, the command code that DB_2 is transmitted writes the command register II; Command code (the D of described command register II ₃₁-D ₂₆) output terminal is connected with the command information input end of command decoder II; The indirect addressing storage unit R of output _j_ 2(D ₂₁-D ₁₈) address value, side-play amount sft_2 (D ₁₇~ D ₂) be connected with address tunnel control module _ 2 as the OPADD signal; When the command register II is reset, the command code output terminal all is " 1 ";

Shown in the order output terminal of command decoder II be connected with address tunnel control module _ 2; 2 command decoder values of command decoder II output, when carrying out an order, this order output terminal is " 0 ", another order output terminal is " 1 ";

The input end of not gate III is connected with pulsqe distributor _ 2 reset output terminals; Output terminal be connected with an input end of door XX IX;

Be connected with the CS_2 signal wire with another input end of door XX IX; The CS_21 signal input part that output terminal and two is read a write storage unit is connected.

Its further technical scheme is: described pulsqe distributor _ 2 comprise the pulse producer II, with the door XXX and or door XX XI;

The RESET input of described pulse producer II is connected with output terminal with the door XXX; The enabling signal pulse input end with or the output terminal of door XX XI be connected; Clock pulse input terminal is connected with the system clock line, pulse 6. output terminal be connected with an input end of door XXX; Pulse 2. _ 2, pulse 4. _ 2, pulse 5. _ 2 output terminal and data transmission with read to arbitrate control module and be connected; Pulse 1. _ 2, pulse 2. _ 2 output terminal be connected with address tunnel control module _ 2;

With in addition two input ends of door XXX also respectively with addressing function control _ 2, data transmission and read to arbitrate control module and be connected;

Or two input ends of door XX XI are connected with WR_2 with CS_2 respectively.

Its further technical scheme is: described data transmission with read to arbitrate control module comprise 32 triple gate group III or door XX XII, with door XX XI or door XXX III, with a door XX XII, address comparator, with door XXX III or door XXX IV, not gate IV and Sheffer stroke gate; The DB_21 that the data input pin and two of described 32 triple gate group III is read a write storage unit is connected; Data output end is connected with DB_2; Output gating input end is connected with output terminal with door XX XII;

Or two input ends of door XX XII are connected with RD_2 with addressing function control _ 2 respectively; Output terminal be connected with an input end of door XX XII;

With two input ends of door XX XI respectively with pulse 4. _ 2,5. _ 2 pulse be connected; Output terminal with or an input end of door XXX III be connected;

Or another input end of door XXX III is connected with RD_2; Output terminal be connected with an input end of door XX XII;

Also with an input end of door XXX III be connected with the output terminal of door XX XII;

An address input end of address comparator is connected with AB_11; An address input end is connected with AB_21; Enable Pin is connected with WR_11; The fiducial value output terminal with or an input end of door XXX IV, an input end of Sheffer stroke gate be connected; WR_11 enables when being " 0 ", and unequal if the value of AB_11 equates that with AB_21 the fiducial value output terminal is " 1 ", the fiducial value output terminal is " 0 "; When WR_11 was " 1 ", the fiducial value output terminal was " 0 ";

With in addition two input ends of door XXX III respectively with pulse 2. _ 2,4. _ 2 pulse be connected; Output terminal and or an input end of door XXX IV, the input end of not gate IV connects;

Or the RD_21 that the output terminal and two of door XXX IV is read a write storage unit is connected;

Another input end of not gate IV output terminal and Sheffer stroke gate is connected;

The output terminal of Sheffer stroke gate is connected with the input end door XXX with pulsqe distributor _ 2; The fiducial value output terminal of address comparator is " 1 ", and when being " 0 " with the output terminal of door XXX III, the output terminal of Sheffer stroke gate is " 0 ", and the output of Sheffer stroke gate is as read operation arbitration result output look-at-me, and the reseting pulse generator II.

Its further technical scheme is: described address tunnel control module _ 2 comprise 32 alternative selector switch III, address arithmetic device II, 32 alternative selector switch IV, address output latch IV, address output latch V, 32 three select a selector switch II, with door XXX IV and with door XXX V;

Low 4 R of an address input end of described 32 alternative selector switch III _jThe R of _ 2 address input ends and command register II _j_ 2 address output ends connect, and high 28 bit address input ends all are " 0 "; Another address input end is connected with DB_21; The gating control input end is connected with output terminal with door XXX IV; Output terminal is connected with an address value input end of address arithmetic device II, an input end of 32 alternative selector switch IV;

A side-play amount sft_2 input end of address arithmetic device II is connected with the side-play amount sft_2 output terminal of command register II; Address arithmetic output terminal as a result is connected with another input end of 32 alternative selector switch IV;

The gating control input end of 32 alternative selector switch IV is connected with output terminal with door XXX V; Address output end is connected with the address input end of address output latch IV, address output latch V;

1. _ 2 the latch pulse input end of address output latch IV is connected with pulse; Output terminal selects an input end of a selector switch II to be connected with 32 three;

2. _ 2 the latch pulse input end of address output latch V is connected with pulse; Output terminal selects an input end of a selector switch II to be connected with 32 three;

32 three are selected another input end of a selector switch II to be connected with AB_2; A gating end is connected with addressing function control _ 2; Another gating end is connected with output terminal with door XXX IV;

1. _ 2 2. _ 2 be connected with pulse with pulse respectively with two input ends of door XXX IV;

2. _ 2 be connected with order 4 output terminals of command decoder II with pulse respectively with two input ends of door XXX V.

The present invention's addressing and storage integrated two read one, and to write memory controller be a kind of characteristics based on FPGA parallel work-flow control, use the hard control circuit that connects of FPGA design, and the addressing formed of sequential control circuit reads one with storage integrated two and writes memory controller, has following beneficial effect:

One, can realize addressing, address arithmetic and the read-write operation of autonomous control store

Among the present invention, addressing is read one with storage integrated two and is write memory controller and chosen by system, under the effect of the WR of system signal, order, address and the number immediately that need write are write the temporary control modules in command register and address, pulsqe distributor is activated, under the time sequential pulse effect of pulsqe distributor, integrated memory controller is independently finished address arithmetic, addressing and read-write operation, does not need system that addressing process and write operation are carried out any operation again; In the sense data process, under inner time sequential pulse effect, independently finish the addressing of storage unit, system sends integrated memory controller according to the sequential requirement and reads (RD) signal, the data of this storage unit are sent to the data bus of system, fully used the parallel processing function of FPGA.

Two, the read-write operation function that has general memory

Among the present invention, still the read-write operation function that keeps general memory, be the selected some storage unit of integrated memory controller, under the pulse action of the RD of system or WR, selected memory cell data is transferred to system data bus, or the data of data bus are write selected storage unit.

Three, has the parallel work-flow function of carrying out other instruction sequence processes with microprocessor

Among the present invention, read data transfer command between two storage unit in the write storage unit for the order that writes data or two, after the command parameter of this order writes the temporary control module of command register and address, CS_1 by " 0 " → " 1 " (referring to Fig. 9, Figure 10), the DB_11 of integrated memory controller output is in high-impedance state with being connected of DB_1; Realize that integrated memory controller carries out the parallel work-flow that the addressing operation of this class order, data transmission and ablation process and microprocessor are carried out other instruction sequence processes.

Four, realize two read operations of executed in parallel

Among the present invention, in storer, design one and independently read port, a reading-writing port independently, two ports can carry out read operation simultaneously, the addressing process that needs timesharing to carry out two source operands instructions of transmission and every transfer instruction when carrying out the instruction of computing class has been simplified in the also read operation that can walk abreast to same storage unit.

Five, systemic price ratio height

The present invention is core with the hard connection control circuit of FPGA, the structure addressing is read one with storage integrated two and is write memory controller, the existing storage unit of using as indirect addressing in the storer, common storage unit is also arranged, read-write capability with normal memory, the function that also has multiple indirect addressing mode, have two port read operations of executed in parallel and two port carries out the arbitration of write and read simultaneously to same storage unit functions, the function that also has memory inside storage unit data transmission each other, its address arithmetic and addressing process are controlled by inner time sequential pulse, improve the speed of microprocessor execution command sequence, have high cost performance.

Below in conjunction with drawings and Examples the present invention's addressing being read a technical characterictic that writes memory controller with storage integrated two is further described.

Description of drawings

Fig. 1: the present invention's addressing and storage integrated two are read an addressing that writes memory controller and are read one with storage integrated two and write the memory controller pinouts;

Fig. 2: the present invention's addressing is read a storage unit that writes memory controller with storage integrated two and is distributed synoptic diagram;

Fig. 3: the present invention's addressing is read a system construction drawing that writes memory controller with storage integrated two;

Fig. 4: the present invention's addressing is read one with storage integrated two and is write the command register of memory controller and the circuit connection diagram that control module is kept in the address;

Fig. 5: the present invention's addressing is read a circuit connection diagram that writes pulsqe distributor _ 1 of memory controller with storage integrated two;

Fig. 6: the present invention's addressing is read a circuit connection diagram that writes the Data Transmission Controlling module of memory controller with storage integrated two;

Fig. 7: the present invention's addressing is read a circuit connection diagram that writes address tunnel control module _ 1 of memory controller with storage integrated two;

Fig. 8: the present invention's addressing is read a combinational logic circuit module input and output pin figure who writes memory controller with storage integrated two;

Fig. 9: the present invention's addressing is read an execution MOV R who writes memory controller with storage integrated two _i, R _jThe sequential chart of+sft order;

Figure 10: the present invention's addressing is read an execution MOV M who writes memory controller with storage integrated two _i, M _jThe sequential chart of order;

Figure 11: the present invention's addressing is read a circuit connection diagram that writes the command register control module of memory controller with storage integrated two;

Figure 12: the present invention's addressing is read a circuit connection diagram that writes pulsqe distributor _ 2 of memory controller with storage integrated two;

Figure 13: the present invention's addressing is read one with storage integrated two and is write the data transmission of memory controller and read to arbitrate the circuit connection diagram of control module;

Figure 14: the present invention's addressing is read a circuit connection diagram that writes address tunnel control module _ 2 of memory controller with storage integrated two.

Among the figure:

I-two reads a write storage unit, and control module is kept in II-command register and address, III-combinational logic circuit module, IV-pulsqe distributor _ 1; V-Data Transmission Controlling module, VI-address tunnel control module _ 1; VII-command register control module; VIII-pulsqe distributor _ 2; IX-data transmission with read to arbitrate control module; X-address tunnel control module _ 2;

1.-pulse 1., 2.-pulse 2., 3.-pulse 3., 4.-pulse 4., 5.-pulse 5., 6.-pulse 6., 7.-pulse 7., 8.-pulse is 8.;

1. _ the 2-pulse 1. _ 2,2. _ the 2-pulse 2. _ 2,3. _ the 2-pulse 3. _ 2,4. _ the 2-pulse 4. _ 2,5. _ the 2-pulse is 5. _ 2;

1-+1 counter, 2-command register I, 3-command decoder I, 4-address register I, 5-address register II, 6-not gate I, 7-not gate II, 8-with the door I;

9-pulse producer I, 10-with a door II, 11-or door I, 12-or door II, 13-with III;

14-data working storage triple gate group, 15-32 triple gate group I, 16-32 triple gate group II, 17-or the door III, 18-or the door IV, 19-or the door V, 20-or the door VI, 21-or the door VII, 22-or door VIII, 23-with a door IV, 24-with V, 25-with a VI;

26-4 alternative selector switchs, 27-32 three are selected a selector switch I, 28-32 alternative selector switch I, 29-address arithmetic device I, 30-32 alternative selector switch II, 31-address output latch I, 32-address output latch II, 33-address output latch III, 34-32 four are selected a selector switch, 35-with the door VII, 36-with the door VIII, 37-with a door IX, 38-with a door X, 39-with an X I;

40-command register II, 41-command decoder II, 42-not gate III 39,43-with a door XX IX;

44-pulse producer II, 45-with a door XXX, 46-or door XX XI;

47-32 triple gate group III, 48-or door XX XII, 49-with a door XX XI, 50-or door XXX III, 51-with a door XX XII, 52-address comparator, 53-with an XXX III, a 54-or XXX IV, 55-not gate IV, 56-Sheffer stroke gate;

57-32 alternative selector switch III, 58-address arithmetic device II, 59-32 alternative selector switch IV, 60-address output latch IV, 61-address output latch V, 62-32 three are selected a selector switch II, 63-with a door XXX IV, 64-with an XXX V;

XT-gating end.

Abbreviation implication in the literary composition:

FPGA-Field Programmable Gate Array, field programmable gate array;

RD-Read, read signal; WR-Write, write signal; AB-Address Bus, address bus;

DB-Data Bus, data bus; CS-Chip Selection, chip selection signal; Sft-Shift, side-play amount.

Embodiment

A kind of addressing is read one with storage integrated two and is write memory controller, as shown in Figure 3, this integrated two is read one and writes memory controller and comprise that two read a write storage unit I, command register and address temporary control module II, combinational logic circuit module III, pulsqe distributor _ 1 IV, Data Transmission Controlling module V, address tunnel control module _ 1 VI, command register control module VII, pulsqe distributor _ 2 VIII, data transmission and read to arbitrate the control module IX and address tunnel control module _ 2 X;

Described two read the temporary control module II of a write storage unit I and command register and address, Data Transmission Controlling module V, address tunnel control module _ 1 VI, command register control module VII, data transmission and read to arbitrate the control module IX and be connected with address tunnel control module _ 2 X;

The temporary control module II in described command register and address also with combinational logic circuit module III, pulsqe distributor _ 1 IV, Data Transmission Controlling module V, address tunnel control module _ 1 VI connects;

Described combinational logic circuit module III also with pulsqe distributor _ 1 IV, Data Transmission Controlling module V, address tunnel control module _ 1 VI connects;

Described pulsqe distributor _ 1 IV also with Data Transmission Controlling module V, address tunnel control module _ 1 VI connects;

Described Data Transmission Controlling module V also with address tunnel control module _ 1 VI, data transmission with read to arbitrate the control module IX and be connected;

Described address tunnel control module _ 1 VI also with data transmission with read to arbitrate the control module IX and be connected;

Described command register control module VII also with pulsqe distributor _ 2 VIII, address tunnel control module _ 2 X connects;

Described pulsqe distributor _ 2 VIII also with data transmission with read to arbitrate the control module IX, address tunnel control module _ 2 X connect;

Described data transmission with read to arbitrate the control module IX and also be connected with address tunnel control module _ 2 X;

Described two read a write storage unit I a data reading-writing port, one independently data read port; The function of reading and writing data port is identical with normal memory, and independently to read the function of port identical with the data read out function of normal memory for data; Described two read to be provided with as indirect addressing and plot in the write storage unit I and add the storage unit R that indexed addressing is used ₀-R ₁₅

The control module II is kept in described command register and address, combinational logic circuit module III, pulsqe distributor _ 1 IV, Data Transmission Controlling module V, address tunnel control module _ 1 VI realize that described two read the control function of a data reading-writing port of a write storage unit I;

The temporary control module II in described command register and address is when CS_1 is " 0 ", under the effect of the WR_1 of system signal, store instruction codes and decoding, storage are indirectly and the address value of base addressing memory unit address value, side-play amount and directly address and being exported, if also have the address value of the 2nd directly address, then under the effect of second WR_1 signal of system, store the address value of the 2nd directly address and exported; Send WR1 or WR2 pulse signal as the starting impulse signal of pulsqe distributor _ 1 IV work; When carrying out normal memory read-write function command, reset pulse divider _ 1 IV; When the temporary control module II in described command register and address was reset, all order output terminals were " 1 "; Read data transfer command between two storage unit in the write storage unit I for the order that writes data or two, after the command parameter of this order writes the temporary control module II of described command register and address, CS_1 by " 0 " → " 1 " (referring to Fig. 9, Figure 10);

The input end of described combinational logic circuit module III is connected with 11 order output terminals of the temporary control module II of command register and address, and also the pulse output end with pulsqe distributor _ 1 III is connected; The output terminal of described combinational logic circuit module III is the logical combination of these input signals, comprising: with logic output and or logic output, described and logic output have by with the door XII ~ with 17 and a gate output terminal of door XX VIII formation; The output of described or logic have by or door IX ~ or door XXX 22 or gate output terminal (referring to Fig. 8, subordinate list one, subordinate list three～subordinate list four) constituting;

Described pulsqe distributor _ 1 IV is as inner sequence timer, output pulse 1., pulse 2., pulse is 3., pulse 4., pulse 5., pulse 6., pulse is 7., pulse 8., 8 pulses are output as combinational logic circuit module III, Data Transmission Controlling module V, and address tunnel control module _ 1 VI provides the time sequential pulse signal; And to the temporary control module II output of command register and address reset signal;

Described Data Transmission Controlling module V is at the WR2 signal of addressing function control _ 1 signal, RD_1, WR_1, the temporary control module II output of command register and address, and under combinational logic circuit module III and the effect logic output valve, realize that two read the DB_11 of a write storage unit I and the Data Transmission Controlling of DB_1 bus; And under the time sequential pulse and effect combinational logic circuit module III or the logic output valve of pulsqe distributor _ 1 IV output, realize reading the RD_11 of a write storage unit I and the control of WR_11 pulse to two according to performed instruction and order;

Described address tunnel control module _ 1 VI under the effect of the time sequential pulse of the output logic value of combinational logic circuit module III and pulsqe distributor _ 1 IV output, according to the address value of the temporary control module II output of command register and address and performed instruction and order to the two AB_11 transport address values of reading a write storage unit I;

Described command register control module VII; Pulsqe distributor _ 2 VIII, data transmission with read to arbitrate the control module IX, address tunnel control module _ 2 X realize described two read a write storage unit I another independently data read the control function of port and the function of read data arbitration;

Described command register control module VII when CS_2 is " 0 ", under the effect of WR_2 signal, store instruction codes and decoding, indirectly and base addressing memory unit address value and side-play amount and exported; When described command register control module VII was reset, 2 order output terminals were " 1 ";

1. _ 2 described pulsqe distributor _ 2 VIII export pulse as inner sequence timer, and pulse 2. _ 2, pulse 3. _ 2, pulse 4. _ 2, pulse is 5. _ 2,5 pulses are output as data transmission and read to arbitrate the control module IX, and address tunnel control module _ 2 X provide the time sequential pulse signal; And to command register control module VII output reset signal;

Described data transmission with read to arbitrate the control module IX under the effect of the time sequential pulse of addressing function control _ 2, RD_2 and pulsqe distributor _ 2 VIII output, realize that two read the DB_21 of a write storage unit I and the Data Transmission Controlling of DB_2 bus; Described data transmission with read to arbitrate the control module IX at two WR_11 that read a write storage unit I during for " 0 ", compare AB_11 address value and AB_21 address value, if two address values equate and described two read a write storage unit I this independently data read port and be in the read operation process, then block the generation of RD_21 read pulse, send look-at-me output; If two address values are unequal, under the effect of the time sequential pulse that described pulsqe distributor _ 2 VIII are exported, realize the normal read operation of instruction and two orders;

Described address tunnel control module _ 2 X according to the address value of the time sequential pulse of pulsqe distributor _ 2 VIII output and the output of command register control module VII and performed instruction and order to the two AB_21 transport address values of reading a write storage unit I.

As shown in Figure 4, the temporary control module II in described command register and address comprise+1 counter 1, command register I 2, command decoder I 3, address register I 4, address register II 5, not gate I 6, not gate II 7 and with door I 8;

The RESET input of described+1 counter 1 is connected with the output terminal of not gate I 6, Enable Pin is connected with the CS_1 signal wire, counting input end is connected with the WR_1 signal, if the CS_1 signal is " 0 ", the RESET input is " 1 ", and under the effect of WR_1 pulse signal ,+1 counter 1 carries out+1 operation, first+1 operation output WR1, it is worth from " 1 " → " 0 "; Second WR_1 count pulse makes WR1 from " 0 " → " 1 "; WR2 is from " 1 " → " 0 "; If the CS_1 signal is " 1 " ,+1 counter 1 is reset, and WR1 and WR2 are one state; The WR1 pulse output end of+1 counter 1 is connected with pulsqe distributor _ 1 IV with the write signal input end of command register I 2, address register I 4, and the WR2 pulse output end is connected with write signal input end, pulsqe distributor _ 1 IV and the Data Transmission Controlling module V of address register II 5;

The Enable Pin of described command register I 2 is connected with the CS_1 signal wire; Reset terminal is connected with pulsqe distributor _ 1 IV; Data input pin is connected with DB_1; Command code (the D of described command register I 2 ₃₁-D ₂₆) output terminal is connected with the command information input end of command decoder I 3; The R of the indirect addressing storage unit of described command register I 2 outputs _i(D ₂₅-D ₂₂) and R _{J_1}(D ₂₁-D ₁₈) address value, side-play amount sft_1 (D ₁₇~ D ₂) be connected with address tunnel control module _ 1 VI as the OPADD signal; When command register I 2 is reset, the command code output terminal all is " 1 " (referring to subordinate list two: a command format table that writes memory controller is read in the present invention's addressing and storage integrated two);

The order output terminal of described command decoder I 3 is connected with combinational logic circuit module III; 11 command decoder values of command decoder I 3 output when carrying out any order, have only this order output terminal to be " 0 ", and other order output terminal is " 1 "; When the command code output terminal of command register I 2 all is " 1 "; Command decoder I 3 all order output terminals are " 1 ";

The input end of described address register I 4 is connected with AB_1, and the address value output terminal is connected with address tunnel control module _ 1 VI;

The input end of described address register II 5 is connected with AB_1, and the address value output terminal is connected with address tunnel control module _ 1 VI;

The input end of not gate I 6 is connected with the CS_1 signal wire;

The input end of not gate II 7 is connected with pulsqe distributor _ 1 IV; Output terminal be connected with an input end of door I 8;

Be connected with the CS_1 signal wire with another input end of door I 8; The CS_11 signal input part that output terminal and two is read a write storage unit I is connected.

As shown in Figure 5, described pulsqe distributor _ 1 IV comprise pulse producer I 9, with the door II 10 or the door I 11 or the door II 12 and with door III 13;

The RESET input of described pulse producer I 9 is connected with output terminal with door II 10; The enabling signal pulse input end is connected with output terminal with door III 13; Clock pulse input terminal is connected with the system clock line, pulse 9. output terminal be connected with an input end of door II 10; Pulse 1., pulse 2., pulse 3., pulse 4., pulse 5., pulse 6., pulse 7., pulse 8. output terminal be connected with combinational logic circuit module III; Pulse 1., pulse 2., pulse 4. output terminal also be connected with address tunnel control module _ 1 VI; Pulse 2. output terminal also is connected with Data Transmission Controlling module V;

Is connected with addressing function control _ 1 with input end of door II 10, other three input ends also respectively and or door XX IX or an XXX or an IX be connected;

Or the door I 11 two input ends respectively with WR1 be connected with door XX VIII, output terminal be connected with an input end of door III 13;

Or the door II 12 two input ends respectively with WR2 be connected with door XX VII, output terminal be connected with an input end of door III 13;

The enabling signal pulse input end of described pulse producer I 9 is changed to " 0 " by " 1 ", and the RESET input is when being " 1 ", and pulse producer I (9) is activated work.

As shown in Figure 6, described Data Transmission Controlling module V comprise 15,32 triple gate group II 16 of 14,32 triple gate group I of data working storage triple gate group or the door III 17 the door IV 18 or the door V 19 the door VI 20 or the door VII 2 or the door VIII 22, with the door IV 23, with the door V 24 and with door VI 25;

The data input pin of described data working storage triple gate group 14 is connected with DB_1; Data write pulse input end with or the door III 17 output terminal be connected; Output gating input end and or the output terminal of a V 19 be connected; The DB_11 end that data output end and two is read a write storage unit I is connected;

The data input pin of 32 triple gate group I 15 is connected with DB_1; Output gating input end and or the output terminal of a VI 20 be connected; The DB_11 end that data output end and two is read a write storage unit I is connected;

The DB_11 end that the data input pin and two of 32 triple gate group II 16 is read a write storage unit I is connected; Output gating input end is connected with output terminal with door IV 23; Data output end is connected with DB_1;

Or two input ends of door III 17 respectively with the WR2 pulse output end of+1 counter 1 be connected with door XX VI;

Or two input ends of door IV 18 respectively with door XX VI, be connected with an XX V; Output terminal with or the door V 19 an input end be connected;

Or the door V 19 another input end be connected with door XX VI;

Or two input ends of door VI 20 are connected with WR_1 with addressing function control _ 1 respectively; Output terminal also with an input end of door V 24 is connected;

Or two input ends of door VII 21 are connected with system RD_1 line with addressing function control _ 1 respectively; Output terminal be connected with an input end of door IV 23;

Or three input ends of door VIII 22 respectively with RD_1, with XII be connected with door XX V; Output terminal be connected with an input end of door IV 23;

Also with an input end of door VI 25 be connected with the output terminal of door IV 23;

With other four input ends of door V 24 also respectively with or door X V or door X IV or door X III with or a door XII be connected; The WR_11 input end that output terminal and two is read a write storage unit I is connected;

With other three input ends of door VI 25 also respectively with pulse 2. or the door XI with or a door X be connected; The RD_11 input end that output terminal and two is read a write storage unit I is connected.

As shown in Figure 7, described address tunnel control module _ 1 VI comprise 4 alternative selector switchs 26,32 three select a selector switch I 27,32 alternative selector switch I 28,29,32 alternative selector switch II 30 of address arithmetic device I, address output latch I 31, address output latch II 32,33,32 four of address output latch III select a selector switch 34, with a door VII 35, with a door VIII 36, with a door IX 37, with door X 38 and with door X I 39;

The R of described 4 alternative selector switchs 26 _iThe R of address input end and command register I 2 _iAddress output end connects; R _jThe R of _ 1 address input end and command register I 2 _j_ 1 address output end connects; The gating control input end with or a door X VI be connected; Output terminal is connected with low 4 an of input end of 32 alternative selector switch I 28;

32 three are selected an input end of a selector switch I 27 to be connected with the two DB_11 ends of reading a write storage unit I; An input end is connected with the address value output terminal of address register I 4; An input end is connected with the address value output terminal of address register II 5; Gating end is connected with output terminal with door VII 35; Gating end with or a door X IX be connected; Output terminal is connected with an input end of 32 alternative selector switch I 28;

High 28 of an input end of 32 alternative selector switch I 28 are connected with " 0 "; The gating end is connected with output terminal with door VIII 36; Address output end is connected with an input end of address arithmetic device I 29 and an input end of 32 alternative selector switch II 30;

Another side-play amount sft_1 input end of address arithmetic device I 29 is connected with the sft_1 output terminal of command register 2; Address arithmetic output terminal as a result is connected with an input end of 32 alternative selector switch II 30;

The gating input end of 32 alternative selector switch II 30 is connected with the output terminal with door IX 37; Address output end is connected with address output latch I 31, address output latch II 32 and the address input end of address output latch III 33;

The latch pulse input end of address output latch I 31 is connected with the output terminal with door X 38; Output terminal selects an input end of a selector switch 34 to be connected with 32 four;

2. the latch pulse input end of address output latch II 32 is connected with pulse; Output terminal selects an input end of a selector switch 34 to be connected with 32 four;

4. the latch pulse input end of address output latch III 33 is connected with pulse; Output terminal selects an input end of a selector switch 34 to be connected with 32 four;

32 four are selected an input end of a selector switch 34 also to be connected with AB_1; A gating end is connected with addressing function control _ 1; Gating end is connected with output terminal with door X I 39; Gating end with or the output terminal of door XX VIII be connected; The AB_11 input end that output terminal and two is read a write storage unit I is connected;

With two input ends of door VII 35 respectively with or door X VII or a door X VIII be connected;

With two input ends of door VIII 36 respectively with or door XX or a door X XI be connected;

With two input ends of door IX 37 respectively with or door X XII or a door XX III be connected;

With three input ends of door X 38 respectively with pulse 1. or door XX IV with or a door XX V be connected;

With three input ends of door XI 39 respectively with door X XII or door XX VI with or a door XX VII be connected.

As shown in figure 11, described command register control module VII comprise command register II 40, command decoder II 41, not gate III 42 and with door XX IX 43;

The Enable Pin of described command register II 40 is connected with the CS_2 signal wire; Reset terminal is connected with pulsqe distributor _ 2 IV; Data input pin is connected with DB_2; Writing pulse input end is connected with WR_2; The CS_2 signal is " 0 ", and the RESET input is " 1 ", and under the effect of WR_2 pulse signal, the command code that DB_2 is transmitted writes command register II 40; Command code (the D of described command register II 40 ₃₁-D ₂₆) output terminal is connected with the command information input end of command decoder II 41; The indirect addressing storage unit R of output _j_ 2(D ₂₁-D ₁₈) address value, side-play amount sft_2 (D ₁₇~ D ₂) be connected with address tunnel control module _ 2 X as the OPADD signal; When command register II 40 is reset, the command code output terminal all is " 1 ";

The order output terminal of described command decoder II 41 is connected with address tunnel control module _ 2 X; 2 command decoder values of command decoder II 41 outputs, when carrying out an order, this order output terminal is " 0 ", another order output terminal is " 1 ";

The input end of not gate III 42 is connected with pulsqe distributor _ 2 VIII reset output terminals; Output terminal be connected with an input end of door XX IX 43;

Be connected with the CS_2 signal wire with another input end of door XX IX 43; The CS_21 signal input part that output terminal and two is read a write storage unit I is connected.

As shown in figure 12, described pulsqe distributor _ 2 VIII comprise pulse producer II 44, with door XXX 45 and or door XX XI 46;

The RESET input of described pulse producer II (44) is connected with the output terminal with door XXX 45; The enabling signal pulse input end with or the output terminal of door XX XI 46 be connected; Clock pulse input terminal is connected with the system clock line, pulse 6. output terminal be connected with an input end of door XXX 45; Pulse 2. _ 2, pulse 4. _ 2, pulse 5. _ 2 output terminal and data transmission with read to arbitrate the control module IX and be connected; Pulse 1. _ 2, pulse 2. _ 2 output terminal be connected with address tunnel control module _ 2 X;

With in addition two input ends of door XXX 45 also respectively with addressing function control _ 2, data transmission and read to arbitrate the control module IX and be connected;

Or two input ends of door XX XI 46 are connected with WR_2 with CS_2 respectively.

As shown in figure 13, described data transmission with read to arbitrate the control module IX comprise 32 triple gate group III 47 or door XX XII 48, with door XX XI 49 or door XXX III 50, with a door XX XII 51, address comparator 52, with door XXX III 53 or door XXX IV 54, not gate IV 55 and Sheffer stroke gate 56;

The DB_21 that the data input pin and two of described 32 triple gate group III 47 is read a write storage unit I is connected; Data output end is connected with DB_2; Output gating input end is connected with output terminal with door XX XII 51;

Or two input ends of door XX XII 48 are connected with RD_2 with addressing function control _ 2 respectively; Output terminal be connected with an input end of door XX XII 51;

With two input ends of door XX XI 49 respectively with pulse 4. _ 2,5. _ 2 pulse be connected; Output terminal with or an input end of door XXX III 50 be connected;

Or another input end of door XXX III 50 is connected with RD_2; Output terminal be connected with an input end of door XX XII 51;

Also with an input end of door XXX III 53 be connected with the output terminal of door XX XII 51;

An address input end of address comparator 52 is connected with AB_11; An address input end is connected with AB_21; Enable Pin is connected with WR_11; The fiducial value output terminal with or an input end of door XXX IV 54, an input end of Sheffer stroke gate 56 be connected; WR_11 enables when being " 0 ", and unequal if the value of AB_11 equates that with AB_21 the fiducial value output terminal is " 1 ", the fiducial value output terminal is " 0 "; When WR_11 was " 1 ", the fiducial value output terminal was " 0 ";

With in addition two input ends of door XXX III 53 respectively with pulse 2. _ 2,4. _ 2 pulse be connected; Output terminal and or an input end of door XXX IV 54, the input end of not gate IV 55 connects;

Or the RD_21 that the output terminal and two of door XXX IV 54 is read a write storage unit I is connected;

Another input end of not gate IV 55 output terminals and Sheffer stroke gate 56 is connected;

The output terminal of Sheffer stroke gate 56 is connected with input end door XXX 45 with pulsqe distributor _ 2 VIII; The fiducial value output terminal of address comparator 52 is " 1 ", and when being " 0 " with the output terminal of door XXX III 53, the output terminal of Sheffer stroke gate 56 is " 0 ", and the output of Sheffer stroke gate 56 is as read operation arbitration result output look-at-me, and reseting pulse generator II 44.

As shown in figure 14, described address tunnel control module _ 2 X comprise 32 alternative

selector switch III

57,58,32 alternative selector switch IV 59 of address arithmetic device II, address

output latch IV

60,61,32 three of address output latch V select a selector switch II 62, with door XXX IV 63 and with door XXX V 64;

Low 4 R of an address input end of described 32 alternative selector switch III 57 _jThe R of _ 2 address input ends and command register II 40 _j_ 2 address output ends connect, and high 28 bit address input ends all are " 0 ";

Another address input end is connected with DB_21; The gating control input end is connected with output terminal with door XXX IV 63; Output terminal is connected with an address value input end of address arithmetic device II 58, an input end of 32 alternative selector switch IV 59;

A side-play amount sft_2 input end of address arithmetic device II 58 is connected with the side-play amount sft_2 output terminal of command register II 40; Address arithmetic output terminal as a result is connected with another input end of 32 alternative selector switch IV 59;

The gating control input end of 32 alternative selector switch IV 59 is connected with output terminal with door XXX V 64; Address output end is connected with the address input end of address output latch IV 60, address output latch V 61;

1. _ 2 the latch pulse input end of address output latch IV 60 is connected with pulse; Output terminal selects an input end of a selector switch II 62 to be connected with 32 three;

2. _ 2 the latch pulse input end of address output latch V 61 is connected with pulse; Output terminal selects an input end of a selector switch II 62 to be connected with 32 three;

32 three are selected another input end of a selector switch II 62 to be connected with AB_2; A gating end is connected with addressing function control _ 2; Another gating end is connected with output terminal with door XXX IV 63;

1. _ 2 2. _ 2 be connected with pulse with pulse respectively with two input ends of door XXX IV 63;

2. _ 2 be connected with order 4 output terminals of command decoder II 41 with pulse respectively with two input ends of door XXX V 64.

Subordinate list one: the present invention's addressing is read an instruction that writes memory controller with storage integrated two and is numbered corresponding tables with order

Subordinate list two: the present invention's addressing is read a command format table that writes memory controller with storage integrated two

Subordinate list three: that write memory controller and a logical combination and order numbering, pulse numbering corresponding tables are read in the present invention's addressing and storage integrated two

Subordinate list four: the present invention's addressing and storage integrated two read that write a memory controller or logical combination and with the corresponding tables of logic, order numbering, pulse numbering

。

Claims

1. an addressing is read one with storage integrated two and write memory controller, it is characterized in that: this integrated two is read one and writes memory controller and comprise that two read a write storage unit (I), control module (II) is kept in command register and address, combinational logic circuit module (III), pulsqe distributor _ 1(IV), Data Transmission Controlling module (V), address tunnel control module _ 1(VI), command register control module (VII), pulsqe distributor _ 2(VIII), data transmission with read to arbitrate control module (IX) and address tunnel control module _ 2(X);

Described two read the temporary control module (II) of a write storage unit (I) and command register and address, Data Transmission Controlling module (V), address tunnel control module _ 1(VI), command register control module (VII), data transmission with read to arbitrate control module (IX) and address tunnel control module _ 2(X) be connected;

Described command register and address keep in control module (II) also with combinational logic circuit module (III), pulsqe distributor _ 1(IV), Data Transmission Controlling module (V) and address tunnel control module _ 1(VI) be connected;

Described combinational logic circuit module (III) also with pulsqe distributor _ 1(IV), Data Transmission Controlling module (V) and address tunnel control module _ 1(VI) be connected;

Described pulsqe distributor _ 1(IV) also with Data Transmission Controlling module (V) and address tunnel control module _ 1(VI) be connected;

Described Data Transmission Controlling module (V) also with address tunnel control module _ 1(VI) with data transmission with read to arbitrate control module (IX) and be connected;

Described address tunnel control module _ 1(VI) also with data transmission with read to arbitrate control module (IX) and be connected;

Described command register control module (VII) also with pulsqe distributor _ 2(VIII) with address tunnel control module _ 2(X) be connected;

Described pulsqe distributor _ 2(VIII) also with data transmission with read to arbitrate control module (IX) and address tunnel control module _ 2(X) be connected;

Described data transmission with read to arbitrate control module (IX) also with address tunnel control module _ 2(X) be connected;

Described two read a write storage unit (I) a data reading-writing port, one independently data read port; The function of reading and writing data port is identical with normal memory, and independently to read the function of port identical with the data read out function of normal memory for data; Described two read to be provided with as indirect addressing and plot in the write storage unit (I) and add the storage unit R that indexed addressing is used ₀-R ₁₅

Control module (II), combinational logic circuit module (III), pulsqe distributor _ 1(IV are kept in described command register and address), Data Transmission Controlling module (V) and address tunnel control module _ 1(VI) realize that described two read the control function of a data reading-writing port of a write storage unit (I);

Control module (II) is kept in when CS_1 is " 0 " in described command register and address, under the effect of the WR_1 of system signal, store instruction codes and decoding, storage are indirectly and the address value of base addressing memory unit address value, side-play amount and directly address and being exported, if also have the address value of the 2nd directly address, then under the effect of second WR_1 signal of system, store the address value of the 2nd directly address and exported; Send WR1 or WR2 pulse signal as pulsqe distributor _ 1(IV) work the starting impulse signal; When carrying out normal memory read-write function command, reset pulse divider _ 1(IV); Control module (II) is kept in when being reset in described command register and address, and all order output terminals are " 1 "; Read data transfer command between two storage unit in the write storage unit (I) for the order that writes data or two, after the command parameter of this order write the temporary control module (II) of described command register and address, CS_1 was by " 0 " → " 1 ";

11 order output terminals of the temporary control module (II) in the input end of described combinational logic circuit module (III) and command register and address are connected, also with pulsqe distributor _ 1(IV) pulse output end be connected; The output terminal of described combinational logic circuit module (III) is the logical combination of these input signals, comprising: with logic output and or logic output, described and logic output have by with the door XII ~ with 17 and a gate output terminal of door XX VIII formation; The output of described or logic have by or door IX ~ or door XXX 22 or gate output terminal constituting;

Described pulsqe distributor _ 1(IV) as inner sequence timer, the output pulse 1., pulse 2., pulse 3., pulse 4., pulse is 5., pulse 6., pulse 7., pulse 8., 8 pulses are output as combinational logic circuit module (III), Data Transmission Controlling module (V) and address tunnel control module _ 1(VI) the time sequential pulse signal is provided; And to temporary control module (II) output of command register and address reset signal;

Described Data Transmission Controlling module (V) is at the WR2 signal of addressing function control _ 1 signal, RD_1, WR_1, temporary control module (II) output of command register and address, and under combinational logic circuit module (III) and the effect logic output valve, realize that two read the DB_11 of a write storage unit (I) and the Data Transmission Controlling of DB_1 bus; And in pulsqe distributor _ 1(IV) under the time sequential pulse and effect combinational logic circuit module (III) or the logic output valve of output, realize reading the RD_11 of a write storage unit (I) and the control of WR_11 pulse to two according to performed instruction and order;

Described address tunnel control module _ 1(VI) in output logic value and the pulsqe distributor _ 1(IV of combinational logic circuit module (III)) under the effect of the time sequential pulse of output, according to the address value of temporary control module (II) output of command register and address and performed instruction and order to the two AB_11 transport address values of reading a write storage unit (I);

Described command register control module (VII), pulsqe distributor _ 2(VIII), data transmission with read to arbitrate control module (IX), address tunnel control module _ 2(X) realize described two read a write storage unit (I) another independently data read the control function of port and the function of read data arbitration;

Described command register control module (VII) when CS_2 is " 0 ", under the effect of WR_2 signal, store instruction codes and decoding, indirectly and base addressing memory unit address value and side-play amount and exported; Described command register control module (VII) is when being reset, and 2 order output terminals are " 1 ";

Described pulsqe distributor _ 2(VIII) as inner sequence timer, the output pulse 1. _ 2, pulse 2. _ 2, pulse 3. _ 2, pulse 4. _ 2, pulse 5. _ 2,5 pulse is output as data transmission and reads to arbitrate control module (IX), address tunnel control module _ 2(X) the time sequential pulse signal is provided; And to command register control module (VII) output reset signal;

Described data transmission with read to arbitrate control module (IX) in addressing function control _ 2, RD_2 and pulsqe distributor _ 2(VIII) under the effect of the time sequential pulse of output, realize that two read the DB_21 of a write storage unit (I) and the Data Transmission Controlling of DB_2 bus; Described data transmission with read to arbitrate control module (IX) at two WR_11 that read a write storage unit (I) during for " 0 ", compare AB_11 address value and AB_21 address value, if two address values equate and described two read a write storage unit (I) this independently data read port and be in the read operation process, then block the generation of RD_21 read pulse, send look-at-me output; If two address values are unequal, in described pulsqe distributor _ 2(VIII) under the effect of time sequential pulse of output, realize the normal read operation of instruction and two orders;

Described address tunnel control module _ 2(X) according to pulsqe distributor _ 2(VIII) time sequential pulse of output and the address value of command register control module (VII) output and performed instruction and order be to the two AB_21 transport address values of reading a write storage unit (I).

2. addressing as claimed in claim 1 is read one and is write memory controller with storage integrated two, it is characterized in that: described command register and address keep in control module (II) comprise+1 counter (1), command register I (2), command decoder I (3), address register I (4), address register II (5), not gate I (6), not gate II (7) and with door I (8); The RESET input of described+1 counter (1) is connected with the output terminal of not gate I (6), Enable Pin is connected with the CS_1 signal wire, counting input end is connected with the WR_1 signal, if the CS_1 signal is " 0 ", the RESET input is " 1 ", and under the effect of WR_1 pulse signal ,+1 counter (1) carries out+1 operation, first+1 operation output WR1, it is worth from " 1 " → " 0 "; Second WR_1 count pulse makes WR1 from " 0 " → " 1 "; WR2 is from " 1 " → " 0 "; If the CS_1 signal is " 1 " ,+1 counter (1) is reset, and WR1 and WR2 are one state; The write signal input end and pulsqe distributor _ 1(IV of the WR1 pulse output end of+1 counter (1) and command register I (2), address register I (4)) be connected write signal input end, the pulsqe distributor _ 1(IV of WR2 pulse output end and address register II (5)) be connected with Data Transmission Controlling module (V);

The Enable Pin of described command register I (2) is connected with the CS_1 signal wire; Reset terminal and pulsqe distributor _ 1(IV) be connected; Data input pin is connected with DB_1; Command code (the D of described command register I (2) ₃₁-D ₂₆) output terminal is connected with the command information input end of command decoder I (3); The R of the indirect addressing storage unit of described command register I (2) output _i(D ₂₅-D ₂₂) and R _{J_1}(D ₂₁-D ₁₈) address value, side-play amount sft_1 (D ₁₇~ D ₂) as OPADD signal and address tunnel control module _ 1(VI) be connected; When command register I (2) is reset, the command code output terminal all is " 1 ";

The order output terminal of described command decoder I (3) is connected with combinational logic circuit module (III); 11 command decoder values of command decoder I (3) output when carrying out any order, have only this order output terminal to be " 0 ", and other order output terminal is " 1 "; When the command code output terminal of command register I (2) all is " 1 "; The all order output terminals of command decoder I (3) are " 1 ";

The input end of described address register I (4) is connected with AB_1, address value output terminal and address tunnel control module _ 1(VI) be connected;

The input end of described address register II (5) is connected with AB_1, address value output terminal and address tunnel control module _ 1(VI) be connected;

The input end of not gate I (6) is connected with the CS_1 signal wire;

The input end of not gate II (7) and pulsqe distributor _ 1(IV) be connected; Output terminal be connected with an input end of door I (8);

Be connected with the CS_1 signal wire with another input end of door I (8); The CS_11 signal input part that output terminal and two is read a write storage unit (I) is connected.

3. a kind of addressing as claimed in claim 1 is read one and is write memory controller with storage integrated two, it is characterized in that: described pulsqe distributor _ 1(IV) comprise pulse producer I (9), with door II (10) or door I (11) or door II (12) and with door III (13);

The RESET input of described pulse producer I (9) is connected with output terminal with door II (10); The enabling signal pulse input end is connected with output terminal with door III (13); Clock pulse input terminal is connected with the system clock line, pulse 9. output terminal be connected with an input end of door II (10); Pulse 1., pulse 2., pulse 3., pulse 4., pulse 5., pulse 6., pulse 7., pulse 8. output terminal be connected with combinational logic circuit module (III); Pulse 1., pulse 2., pulse 4. output terminal also with address tunnel control module _ 1(VI) be connected; Pulse 2. output terminal also is connected with Data Transmission Controlling module (V);

Is connected with addressing function control _ 1 with input end of door II (10), other three input ends also respectively and or door XX IX or an XXX or an IX be connected;

Or the door I (11) two input ends respectively with WR1 be connected with door XX VIII, output terminal be connected with an input end of door III (13);

Or the door II (12) two input ends respectively with WR2 be connected with door XX VII, output terminal be connected with an input end of door III (13);

When the enabling signal pulse input end of described pulse producer I (9) is changed to " 0 " by " 1 ", and the RESET input is when being " 1 ", and pulse producer I (9) is activated work.

4. a kind of addressing as claimed in claim 1 is read one and is write memory controller with storage integrated two, it is characterized in that: described Data Transmission Controlling module (V) comprise data working storage triple gate group (14), 32 triple gate group I (15), 32 triple gate group II (16) or door III (17) or door IV (18) or door V (19) or door VI (20) or door VII (21) or door VIII (22), with a door IV (23), with door V (24) and with door VI (25); The data input pin of described data working storage triple gate group (14) is connected with DB_1; Data write pulse input end with or the door III (17) output terminal be connected; Output gating input end and or the output terminal of a V (19) be connected; The DB_11 end that data output end and two is read a write storage unit (I) is connected;

The data input pin of 32 triple gate group I (15) is connected with DB_1; Output gating input end and or the output terminal of a VI (20) be connected; The DB_11 end that data output end and two is read a write storage unit (I) is connected;

The DB_11 end that the data input pin and two of 32 triple gate group II (16) is read a write storage unit (I) is connected; Output gating input end is connected with output terminal with door IV (23); Data output end is connected with DB_1;

Or two input ends of door III (17) respectively with the WR2 pulse output end of+1 counter (1) be connected with door XX VI;

Or two input ends of door IV (18) respectively with door XX VI, be connected with an XX V; Output terminal with or the door V (19) an input end be connected;

Or the door V (19) another input end be connected with door XX VI;

Or two input ends of door VI (20) are connected with WR_1 with addressing function control _ 1 respectively; Output terminal also with an input end of door V (24) is connected;

Or two input ends of door VII (21) are connected with system RD_1 line with addressing function control _ 1 respectively; Output terminal be connected with an input end of door IV (23);

Or three input ends of door VIII (22) respectively with RD_1, with XII be connected with door XX V; Output terminal be connected with an input end of door IV (23);

Also with an input end of door VI (25) be connected with the output terminal of door IV (23);

With other four input ends of door V (24) also respectively with or door X V or door X IV or door X III with or a door XII be connected; The WR_11 input end that output terminal and two is read a write storage unit (I) is connected;

With other three input ends of door VI (25) also respectively with pulse 2. or the door XI with or a door X be connected; The RD_11 input end that output terminal and two is read a write storage unit (I) is connected.

5. a kind of addressing as claimed in claim 1 is read one with storage integrated two and is write memory controller, it is characterized in that: described address tunnel control module _ 1(VI) comprise 4 alternative selector switchs (26), 32 three are selected a selector switch I (27), 32 alternative selector switch I (28), address arithmetic device I (29), 32 alternative selector switch II (30), address output latch I (31), address output latch II (32), address output latch III (33), 32 four are selected a selector switch (34), with door VII (35), with door VIII (36), with door IX (37), with door X (38) and with door X I (39);

The R of described 4 alternative selector switchs (26) _iThe R of address input end and command register I (2) _iAddress output end connects; R _jThe R of _ 1 address input end and command register I (2) _j_ 1 address output end connects; The gating control input end with or a door X VI be connected; Output terminal is connected with low 4 an of input end of 32 alternative selector switch I (28);

32 three are selected an input end of a selector switch I (27) to be connected with the two DB_11 ends of reading a write storage unit (I); An input end is connected with the address value output terminal of address register I (4); An input end is connected with the address value output terminal of address register II (5); Gating end is connected with output terminal with door VII (35); Gating end with or a door X IX be connected; Output terminal is connected with an input end of 32 alternative selector switch I (28);

High 28 of an input end of 32 alternative selector switch I (28) are connected with " 0 "; The gating end is connected with output terminal with door VIII (36); Input end of address output end and address arithmetic device I (29) and an input end of 32 alternative selector switch II (30) are connected;

Another side-play amount sft_1 input end of address arithmetic device I (29) is connected with the sft_1 output terminal of command register (2); Address arithmetic output terminal as a result is connected with an input end of 32 alternative selector switch II (30);

The gating input end of 32 alternative selector switch II (30) is connected with output terminal with door IX (37); Address output end is connected with address output latch I (31), address output latch II (32) and the address input end of address output latch III (33);

The latch pulse input end of address output latch I (31) is connected with output terminal with door X (38); Output terminal selects an input end of a selector switch (34) to be connected with 32 four;

The latch pulse input end of address output latch II (32) 2. is connected with pulse; Output terminal selects an input end of a selector switch (34) to be connected with 32 four;

The latch pulse input end of address output latch III (33) 4. is connected with pulse; Output terminal selects an input end of a selector switch (34) to be connected with 32 four;

32 four are selected an input end of a selector switch (34) also to be connected with AB_1; A gating end is connected with addressing function control _ 1; Gating end is connected with output terminal with door X I (39); Gating end with or the output terminal of door XX VIII be connected; The AB_11 input end that output terminal and two is read a write storage unit (I) is connected;

With two input ends of door VII (35) respectively with or door X VII or a door X VIII be connected;

With two input ends of door VIII (36) respectively with or door XX or a door X XI be connected;

With two input ends of door IX (37) respectively with or door X XII or a door XX III be connected;

With three input ends of door X (38) respectively with pulse 1. or door XX IV with or a door XX V be connected;

With three input ends of door XI (39) respectively with door X XII or door XX VI with or a door XX VII be connected.

6. a kind of addressing as claimed in claim 1 is read one and is write memory controller with storage integrated two, it is characterized in that: described command register control module (VII) comprise command register II (40), command decoder II (41), not gate III (42) and with door XX IX (43);

The Enable Pin of described command register II (40) is connected with the CS_2 signal wire; Reset terminal and pulsqe distributor _ 2(VIII) be connected; Data input pin is connected with DB_2; Writing pulse input end is connected with WR_2; The CS_2 signal is " 0 ", and the RESET input is " 1 ", and under the effect of WR_2 pulse signal, the command code that DB_2 is transmitted writes command register II (40); Command code (the D of described command register II (40) ₃₁-D ₂₆) output terminal is connected with the command information input end of command decoder II (41); The indirect addressing storage unit R of output _j_ 2(D ₂₁-D ₁₈) address value, side-play amount sft_2 (D ₁₇~ D ₂) as OPADD signal and address tunnel control module _ 2(X) be connected; When command register II (40) is reset, the command code output terminal all is " 1 ";

The order output terminal of described command decoder II (41) and address tunnel control module _ 2(X) be connected; 2 command decoder values of command decoder II (41) output, when carrying out an order, this order output terminal is " 0 ", another order output terminal is " 1 ";

The input end of not gate III (42) and pulsqe distributor _ 2(VIII) reset output terminal is connected; Output terminal be connected with an input end of door XX IX (43);

Be connected with the CS_2 signal wire with another input end of door XX IX (43); The CS_21 signal input part that output terminal and two is read a write storage unit (I) is connected.

7. a kind of addressing as claimed in claim 1 is read one and is write memory controller with storage integrated two, it is characterized in that: described pulsqe distributor _ 2(VIII) comprise pulse producer II (44), with door XXX (45) and or an XX XI (46);

The RESET input of described pulse producer II (44) is connected with output terminal with door XXX (45); The enabling signal pulse input end with or the door XX XI (46) output terminal be connected; Clock pulse input terminal is connected with the system clock line, pulse 6. output terminal be connected with an input end of door XXX (45); Pulse 2. _ 2, pulse 4. _ 2 ,Pulse 5. _ 2 output terminal and data transmission with read to arbitrate control module (IX) and be connected; Pulse 1. _ 2, pulse 2. _ 2 output terminal and address tunnel control module _ 2(X) be connected;

With in addition two input ends of door XXX (45) also respectively with addressing function control _ 2, data transmission and read to arbitrate control module (IX) and be connected;

Or two input ends of door XX XI (46) are connected with WR_2 with CS_2 respectively.

8. a kind of addressing as claimed in claim 1 is read one and is write memory controller with storage integrated two, it is characterized in that: described data transmission with read to arbitrate control module (IX) comprise 32 triple gate group III (47) or door XX XII (48), with door XX XI (49) or door XXX III (50), with a door XX XII (51), address comparator (52), with door XXX III (53) or door XXX IV (54), not gate IV (55) and Sheffer stroke gate (56);

The DB_21 that the data input pin and two of described 32 triple gate group III (47) is read a write storage unit (I) is connected; Data output end is connected with DB_2; Output gating input end is connected with output terminal with door XX XII (51);

Or two input ends of door XX XII (48) are connected with RD_2 with addressing function control _ 2 respectively; Output terminal be connected with an input end of door XX XII (51);

With two input ends of door XX XI (49) respectively with pulse 4. _ 2,5. _ 2 pulse be connected; Output terminal with or the door XXX III (50) an input end be connected;

Or another input end of door XXX III (50) is connected with RD_2; Output terminal be connected with an input end of door XX XII (51);

Also with an input end of door XXX III (53) be connected with the output terminal of door XX XII (51);

An address input end of address comparator (52) is connected with AB_11; An address input end is connected with AB_21; Enable Pin is connected with WR_11; The fiducial value output terminal with or an input end, an input end of Sheffer stroke gate (56) of door XXX IV (54) be connected; WR_11 enables when being " 0 ", and unequal if the value of AB_11 equates that with AB_21 the fiducial value output terminal is " 1 ", the fiducial value output terminal is " 0 "; When WR_11 was " 1 ", the fiducial value output terminal was " 0 ";

With in addition two input ends of door XXX III (53) respectively with pulse 2. _ 2,4. _ 2 pulse be connected; Output terminal and or an input end of door XXX IV (54), the input end of not gate IV (55) connects;

Or the RD_21 that the output terminal and two of door XXX IV (54) is read a write storage unit (I) is connected;

Another input end of not gate IV (55) output terminal and Sheffer stroke gate (56) is connected;

The output terminal of Sheffer stroke gate (56) and pulsqe distributor _ 2(VIII) be connected with an input end of door XXX (45); The fiducial value output terminal of address comparator (52) is " 1 ", when being " 0 " with the output terminal of door XXX III (53), the output terminal of Sheffer stroke gate (56) is " 0 ", and the output of Sheffer stroke gate (56) is as read operation arbitration result output look-at-me, and reseting pulse generator II (44).

9. a kind of addressing as claimed in claim 1 is read one and is write memory controller with storage integrated two, it is characterized in that: described address tunnel control module _ 2(X) comprise 32 alternative selector switch III (57), address arithmetic device II (58), 32 alternative selector switch IV (59), address output latch IV (60), address output latch V (61), 32 three select a selector switch II (62), with door XXX IV (63) and with door XXX V (64);

Low 4 R of an address input end of described 32 alternative selector switch III (57) _jThe R of _ 2 address input ends and command register II (40) _j_ 2 address output ends connect, and high 28 bit address input ends all are " 0 "; Another address input end is connected with DB_21; The gating control input end is connected with output terminal with door XXX IV (63); Output terminal is connected with an address value input end of address arithmetic device II (58), an input end of 32 alternative selector switch IV (59);

A side-play amount sft_2 input end of address arithmetic device II (58) is connected with the side-play amount sft_2 output terminal of command register II (40); Address arithmetic output terminal as a result is connected with another input end of 32 alternative selector switch IV (59);

The gating control input end of 32 alternative selector switch IV (59) is connected with output terminal with door XXX V (64); Address output end is connected with the address input end of address output latch IV (60), address output latch V (61);

The latch pulse input end of address output latch IV (60) 1. _ 2 is connected with pulse; Output terminal selects an input end of a selector switch II (62) to be connected with 32 three;

The latch pulse input end of address output latch V (61) 2. _ 2 is connected with pulse; Output terminal selects an input end of a selector switch II (62) to be connected with 32 three;

32 three are selected another input end of a selector switch II (62) to be connected with AB_2; A gating end is connected with addressing function control _ 2; Another gating end is connected with output terminal with door XXX IV (63);

1. _ 2 2. _ 2 be connected with pulse with pulse respectively with two input ends of door XXX IV (63);

2. _ 2 be connected with order 4 output terminals of command decoder II (41) with pulse respectively with two input ends of door XXX V (64).