CN105161433A - Fan-out type wafer grade packaging method - Google Patents
Fan-out type wafer grade packaging method Download PDFInfo
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- CN105161433A CN105161433A CN201510629484.0A CN201510629484A CN105161433A CN 105161433 A CN105161433 A CN 105161433A CN 201510629484 A CN201510629484 A CN 201510629484A CN 105161433 A CN105161433 A CN 105161433A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
- H01L2224/82103—Forming a build-up interconnect by additive methods, e.g. direct writing using laser direct writing
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a fan-out type wafer grade packaging method, comprising steps of providing a carrier, wherein an adhesive layer is formed on the appearance of the carrier, adhering a front surface of at least one semiconductor chip on the surface of an adhesive layer with the front surface facing upwardly, adopting plastic packaging technology to package the semiconductor chip in the plastic packaging material, forming an opening corresponding to a follow-up connection through holes to be formed and a rewiring layer to be formed, and forming the connection through hole and the re-wiring layer inside the opening. The fan-out wafer grade packaging method disclosed by the invention adopts the plastic packaging technology to package the semiconductor chip in the plastic packaging material in a plastic packaging manner while forming the opening corresponding to the connection through hole and the re-wiring layer on the inner side of the plastic packaging material layer, reduces the steps of coating a dielectric layer and the optical etching RDL layer, effectively reduce the product cost, enables the whole technology process to be simple, greatly improve the production quantity and has a wide application prospect in the semiconductor packaging field.
Description
Technical field
The invention belongs to field of semiconductor package, particularly relate to a kind of fan-out-type wafer-level packaging method.
Background technology
Fan-out-type wafer-level packaging (Fan-outWaferLevelpackage, FOWLP) being a kind of embedded chip method for packing of wafer level processing, is one of good Advanced Packaging method of more, the integrated flexibility of current a kind of input/output end port (I/O).Fan-out-type wafer-level packaging has the advantage of its uniqueness compared to the wafer-level packaging of routine: 1. I/O spacing is flexible, does not rely on chip size; 2. only use effective die, product yield improves; 3. there is 3D package path flexibly, namely can form the figure of General Cell at top; 4. there is good electrical property and hot property; 5. frequency applications; 6. easily in re-wiring layer (RDL), high-density wiring is realized.
Existing fan-out-type wafer-level packaging method is generally: provide carrier, forms adhesive layer at carrier surface; Semiconductor chip is faced up and is mounted on adhesive layer surface; Dielectric layer; Photoetching, electroplate out re-wiring layer (RDL); Adopt Shooting Technique by semiconductor chip plastic packaging in capsulation material layer; Plastic packaging grinding, opening; Photoetching, electroplate out ball lower metal layer; Carry out planting ball backflow, form welded ball array; Remove carrier.
The process of repeatedly photoetching is needed in existing fan-out-type wafer-level packaging method.Photoetching process must use specific lithographic equipment just can complete, device structure needed for photoetching process is complicated, expensive, and the process CIMS of whole photoetching process is loaded down with trivial details consuming time, this inherently causes the cost of existing fan-out-type wafer-level packaging method higher, and output is lower.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of fan-out-type wafer-level packaging method, photoetching process is repeatedly used to form rewiring figure, ball lower metal layer and the cost that causes is higher, the problem that output is lower in fan-out-type wafer-level packaging method for solving in prior art.
For achieving the above object and other relevant objects, the invention provides a kind of fan-out-type wafer-level packaging method, described fan-out-type wafer-level packaging method at least comprises:
One carrier is provided, forms adhesive layer at described carrier surface;
At least semiconductor chip front side will be mounted on described adhesive layer surface upward;
Adopt plastic package process by described semiconductor chip plastic packaging in capsulation material layer, and in described capsulation material layer, form the opening corresponding with the follow-up connecting through hole that will be formed and re-wiring layer simultaneously;
Connecting through hole and re-wiring layer is formed in described opening.
As a kind of preferred version of fan-out-type wafer-level packaging method of the present invention, adopt plastic package process by described semiconductor chip plastic packaging in capsulation material layer, and in described capsulation material layer, form the opening corresponding with the follow-up connecting through hole that will be formed and re-wiring layer simultaneously comprise:
There is provided plastic packaging forming panel and lower plastic packaging forming panel, utilize electronics art directly to write exposure association reaction ion etching technology, the lower surface of plastic packaging forming panel prepares connecting through hole and rewiring layer pattern on described;
There is surface mount the described carrier of described semiconductor chip to face up to be placed in the upper surface of described lower plastic packaging forming panel;
Capsulation material is placed on the adhesive layer being pasted with described semiconductor chip;
Under preset temperature condition, compress described upper plastic packaging forming panel and described lower plastic packaging forming panel, namely described semiconductor chip plastic packaging is being formed described opening while capsulation material layer in described capsulation material layer;
Process is cured to described capsulation material layer, and discharges described upper plastic packaging forming panel and described lower plastic packaging forming panel.
As a kind of preferred version of fan-out-type wafer-level packaging method of the present invention, the material of described upper plastic packaging forming panel and described lower plastic packaging forming panel is diamond, stainless steel, silicon dioxide or pottery.
As a kind of preferred version of fan-out-type wafer-level packaging method of the present invention, described preset temperature is 125 DEG C ~ 150 DEG C.
As a kind of preferred version of fan-out-type wafer-level packaging method of the present invention, stripping film is all posted in the described lower surface of upper plastic packaging forming panel and the surface of described connecting through hole and rewiring layer pattern.
As a kind of preferred version of fan-out-type wafer-level packaging method of the present invention, adopt chemical plating process or electroplating technology in described opening, form described connecting through hole and described re-wiring layer.
As a kind of preferred version of fan-out-type wafer-level packaging method of the present invention, the additive containing special organometallic compounds form in described capsulation material, can there is physical-chemical reaction and be activated in described additive under the irradiation of laser beam.
As a kind of preferred version of fan-out-type wafer-level packaging method of the present invention, adopt chemical plating process or electroplating technology forms described connecting through hole in described opening and described re-wiring layer comprises:
In described opening, make described capsulation material layer produce physical-chemical reaction by laser beam activation form metal core;
Based on described metal core, adopt chemical plating process or electroplating technology in described opening, form described connecting through hole and described re-wiring layer.
As a kind of preferred version of fan-out-type wafer-level packaging method of the present invention, also comprise form described connecting through hole and described re-wiring layer in described opening after:
Dielectric layer is formed at described re-wiring layer and described capsulation material layer surface;
Graphical described dielectric layer, to form the perforate exposing described re-wiring layer in described dielectric layer;
Described re-wiring layer forms ubm layer;
Described ubm layer is planted ball backflow, forms solder bumps array;
Remove described carrier and described adhesive layer.
As a kind of preferred version of fan-out-type wafer-level packaging method of the present invention, heating or ultraviolet lighting technique is adopted described adhesive layer to be separated, to remove described carrier and described adhesive layer with described capsulation material layer.
As mentioned above, fan-out-type wafer-level packaging method of the present invention, there is following beneficial effect: the present invention adopts plastic package process by described semiconductor chip plastic packaging in capsulation material layer, and in capsulation material layer, form the opening corresponding with connecting through hole and re-wiring layer simultaneously, electronics art is utilized directly to write exposure association reaction ion etching technology, plastic packaging forming panel is prepared connecting through hole and rewiring layer pattern, after plastic package process process, described semiconductor chip plastic packaging is in capsulation material layer, and simultaneously by the Graphic transitions on upper plastic packaging forming panel in capsulation material layer, namely only need to provide plastic packaging forming panel on, electronics art is utilized directly to write exposure association reaction ion etching technology, connecting through hole and rewiring layer pattern is prepared at upper plastic packaging forming panel lower surface, and between adhesive layer capsulation material being placed in upper plastic packaging forming panel and being pasted with semiconductor chip, under preset temperature condition, make capsulation material soften, plastic packaging forming panel and lower plastic packaging forming panel in compression, by described semiconductor chip plastic packaging in capsulation material layer, and simultaneously by the Graphic transitions on mould in capsulation material, described capsulation material can be made to open to form capsulation material layer along described adhesive layer surface spreading, and the opening corresponding with connecting through hole and re-wiring layer is formed in institute's capsulation material layer, decrease coating dielectric layer, the processing steps such as photoetching RDL layer, significantly reduce production cost, and step is simple in whole technical process, greatly can improve the output of product, be with a wide range of applications in semiconductor packages territory.
Accompanying drawing explanation
Fig. 1 is shown as the flow chart of fan-out-type wafer-level packaging method of the present invention.
Fig. 2 is shown as the structural representation that in fan-out-type wafer-level packaging method of the present invention, S1 step presents.
Fig. 3 is shown as the structural representation that in fan-out-type wafer-level packaging method of the present invention, S2 step presents.
Fig. 4 to Fig. 5 is shown as the structural representation that in fan-out-type wafer-level packaging method of the present invention, S3 step presents.
Fig. 6 is shown as the structural representation that in fan-out-type wafer-level packaging method of the present invention, S4 step presents.
Fig. 7 is shown as the structural representation that in fan-out-type wafer-level packaging method of the present invention, S5 step presents.
Fig. 8 is shown as the structural representation that in fan-out-type wafer-level packaging method of the present invention, S6 step presents.
Fig. 9 is shown as the structural representation that in fan-out-type wafer-level packaging method of the present invention, S7 step presents.
Element numbers explanation
10 carriers
11 adhesive layers
12 semiconductor chips
131 capsulation materials
132 capsulation material layers
14 openings
Plastic packaging forming panel on 15
151 connecting through holes and rewiring layer pattern
16 times plastic packaging forming panels
171 connecting through holes
172 re-wiring layers
18 ubm layers
19 solder bumps
20 dielectric layers
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Fig. 9.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, though only show the assembly relevant with the present invention in diagram but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Refer to Fig. 1, the invention provides a kind of fan-out-type wafer-level packaging method, described fan-out-type wafer-level packaging method comprises the following steps:
S1: provide a carrier, forms adhesive layer at described carrier surface;
S2: at least semiconductor chip front side will be mounted on described adhesive layer surface upward;
S3: adopt plastic package process by described semiconductor chip plastic packaging in capsulation material layer, and in described capsulation material layer, form the opening corresponding with the follow-up connecting through hole that will be formed and re-wiring layer simultaneously;
S4: form connecting through hole and re-wiring layer in described opening.
In step sl, refer to the S1 step in Fig. 1 and Fig. 2, a carrier 10 is provided, form adhesive layer 11 on described carrier 10 surface.
Exemplarily, described carrier 10 can provide structure or the matrix of rigidity for follow-up making adhesive layer 11, and such as, described carrier 10 can select the one in the polymer of glass, semiconductor, metal and rigidity for having suitable shape.Preferably, in the present embodiment, described carrier 10 is selected as glass.
Exemplarily, the shape of described carrier 10 is circular.
Exemplarily, described adhesive layer 11 preferably selects the jointing material with smooth finish surface to make, and at its surface mount semiconductor chip 12 and capsulation material layer 132 can be formed, described adhesive layer 11 must have certain adhesion with described semiconductor chip 12 and described capsulation material layer 132, to ensure that described semiconductor chip 12 and described capsulation material layer 132 can not produce the situations such as Automatic-falling in subsequent technique; In addition, described adhesive layer 11 can have stronger adhesion with carrier 10, in general, described adhesive layer 11 and the adhesion of carrier 10 should be greater than the adhesion with described semiconductor chip 12 and described capsulation material layer 132, so that described adhesive layer 11 and described carrier 10 are separated with described semiconductor chip 12 and described capsulation material layer 132.Exemplarily, described adhesive layer 11 can be selected as the one in adhesive tape, the adhesive glue made by spin coating proceeding or epoxy resin.Preferably, in the present embodiment, described adhesive layer 11 is selected as adhesive tape.
In step s 2, refer to the S2 step in Fig. 1 and Fig. 3, will at least semiconductor chip 12 face up be mounted on described adhesive layer 11 surface.
Exemplarily, in the present embodiment, described semiconductor chip 12 can be fan-out-type semiconductor chip 14.Certainly, in other embodiments, method for packing of the present invention also may be used for installing as devices such as memory device, display device, input module, discrete component, power supply, pressurizers, and is not limited thereto several examples enumerated in place.
Exemplarily, the quantity of the semiconductor chip 12 that the quantity of described semiconductor chip 12 can be able to carry for 1 to 1 carrier, and described semiconductor chip 12 can be dissimilar semiconductor chip, namely described adhesive layer 11 can carry the described semiconductor chip 12 of polytype, multiple quantity.
In step s3, refer to the S3 step in Fig. 1 and Fig. 4 to Fig. 5, adopt plastic package process by described semiconductor chip 12 plastic packaging in capsulation material layer 132, and the opening 14 that simultaneously formation is corresponding with the follow-up connecting through hole 171 that will be formed and re-wiring layer 172 described capsulation material layer 132 in.
Exemplarily, adopt plastic package process by described semiconductor chip 12 plastic packaging in capsulation material layer 132, and the opening 14 that simultaneously formation is corresponding with the follow-up connecting through hole 171 that will be formed and re-wiring layer 172 described capsulation material layer 132 in comprises:
S31: provide plastic packaging forming panel 15 and lower plastic packaging forming panel 16, utilizes electronics art directly to write exposure association reaction ion etching technology, and the lower surface of plastic packaging forming panel 16 prepares connecting through hole and rewiring layer pattern 151 on described;
S32: the upper surface having surface mount the described carrier 10 of described semiconductor chip 12 to face up to be placed in described lower plastic packaging forming panel 16;
S33: capsulation material 131 is placed on the adhesive layer 11 being pasted with described semiconductor chip 12;
S34: under preset temperature condition, compress described upper plastic packaging forming panel 15 and described lower plastic packaging forming panel 16, by described semiconductor chip 12 plastic packaging in capsulation material layer 132, and simultaneously by the Graphic transitions on described upper plastic packaging forming panel 15 in described capsulation material layer 132, namely by described semiconductor chip 12 plastic packaging while capsulation material layer 132 in described capsulation material layer 132 formed described opening 14;
S35: process is cured to described capsulation material layer 132, and discharge described upper plastic packaging forming panel 15 and described lower plastic packaging forming panel 16.
Exemplarily, described capsulation material 131 comprises the polymeric material such as epoxy resin, phenolic resins.Preferably, in the present embodiment, described capsulation material 131 is epoxy resin.
Exemplarily, material and the shape of described upper plastic packaging forming panel 15 and described lower plastic packaging forming panel 16 are identical, preferably, described upper plastic packaging forming panel 15 and described lower plastic packaging forming panel 16 are circle, and the material of described upper plastic packaging forming panel 15 and described lower plastic packaging forming panel 16 is as diamond, stainless steel, silicon dioxide or pottery.
Exemplarily, temperature is increased to described preset temperature, described capsulation material 131 is in soft state and is even in liquid, there is thermal deformation in described capsulation material layer 13, now, compress described upper plastic packaging forming panel 15 and described lower plastic packaging forming panel 16, under the effect of the pressure, described capsulation material 131 is opened along the surface spreading of described adhesive layer 11, at formation coated described semiconductor chip 12 while covering the capsulation material layer 132 of described adhesive layer 11 exposed surface, the described connecting through hole of described upper plastic packaging forming panel 15 lower surface and rewiring layer pattern 151 can be absorbed in the inside of described capsulation material layer 132, and the opening corresponding with described connecting through hole and rewiring layer pattern 151 is formed in described capsulation material layer 132, namely in described capsulation material layer 132, the described opening 14 corresponding with the follow-up described connecting through hole 171 that will be formed and described re-wiring layer 172 is formed.
Exemplarily, described preset temperature can set according to actual needs, as long as the temperature range that described capsulation material 131 can be made softening, preferably, in the present embodiment, described preset temperature is 125 DEG C ~ 150 DEG C.
Exemplarily, the described opening 14 be positioned at above described semiconductor chip 12 runs through described capsulation material layer 132 to expose described semiconductor chip 12, to guarantee the follow-up electrical extraction that can realize described semiconductor chip 12.
Exemplarily, stripping film (not shown) is all posted on the described lower surface of upper plastic packaging forming panel 15 and the surface of described connecting through hole and rewiring layer pattern 151, described stripping film be conducive to making after plastic package process completes described on plastic packaging forming panel 15 peel off with described capsulation material layer 132.
Compared to prior art, the present invention adopts plastic package process by described semiconductor chip 12 plastic packaging in capsulation material layer 132, and the opening 14 that simultaneously formation is corresponding with the follow-up connecting through hole 171 that will be formed and re-wiring layer 172 described capsulation material layer 132 in, only need to provide a lower surface to be formed with the described upper plastic packaging forming panel 15 of the connecting through hole corresponding with connecting through hole 171 and re-wiring layer 172 and rewiring layer pattern 151, and between the adhesive layer 11 capsulation material 131 being placed in described upper plastic packaging forming panel 15 and being pasted with described semiconductor chip 12, under preset temperature condition, make described capsulation material 131 soften, compress described upper plastic packaging forming panel 15 and described lower plastic packaging forming panel 16, described capsulation material 131 can be made to open to form capsulation material layer 132 along the surface spreading of described adhesive layer 11, and the opening 14 corresponding with connecting through hole 171 and re-wiring layer 172 is formed in institute's capsulation material layer 132, decrease coating dielectric layer, the processing steps such as photoetching RDL layer, significantly reduce production cost, and step is simple in whole technical process, greatly can improve the output of product, be with a wide range of applications in semiconductor packages territory.
In step s 4 which, refer to the S4 step in Fig. 1 and Fig. 6, in described opening 14, form connecting through hole 171 and re-wiring layer 172.
Exemplarily, chemical plating process or electroplating technology is adopted to form described connecting through hole 171 and described re-wiring layer 172 in described opening 14.
Exemplarily, the additive containing special organometallic compounds form in described capsulation material 131, can there is physical-chemical reaction and be activated in described additive, and then can discharge metal ion under the irradiation of laser beam.
Exemplarily, chemical plating process or electroplating technology forms described connecting through hole 171 in described opening 14 and described re-wiring layer 172 comprises is adopted:
S41: make described capsulation material layer 132 produce physical-chemical reaction by laser beam activation in described opening and form metal core (not shown);
S42: based on described metal core, adopts chemical plating process or electroplating technology to form described connecting through hole 171 and described re-wiring layer 172 in described opening 14.
Exemplarily, the metal of chemical plating or plating comprises the metal materials such as Cu, Ni, SnAg, and preferably, in the present embodiment, the metal of plating is Cu.
Exemplarily, described connecting through hole 171 runs through described capsulation material layer 132, and one end of described connecting through hole 171 is connected with the front of described semiconductor chip 12, and the other end is connected with described re-wiring layer 172.
Exemplarily, the upper surface of described re-wiring layer 16 can be mutually concordant with the upper surface of described capsulation material layer 132, also can higher than the upper surface of described capsulation material layer 132, can also lower than the upper surface of described capsulation material layer 132.
Consult Fig. 7 to Fig. 9, form described re-wiring layer 16 in described opening 14 after, described fan-out-type wafer-level packaging method is further comprising the steps of:
S5: form dielectric layer 20 at described re-wiring layer 162 and described capsulation material layer 13 surface; Graphical described dielectric layer 20, to form the perforate exposing described re-wiring layer 172 in described dielectric layer 29; On described re-wiring layer 172, ubm layer 18 is formed, as shown in Figure 7 by chemical plating process or electroplating technology;
S6: plant ball backflow on described ubm layer 18, form solder bumps 19 array, as shown in Figure 8;
S7: remove described carrier 10 and described adhesive layer 11, as shown in Figure 9.
Exemplarily, the material of described dielectric layer 20 is low k dielectric, and preferably, in the present embodiment, the material of described dielectric layer 20 can be silica, phosphosilicate glass (PSG) or fluorinated silica glass (FSG) etc.
Exemplarily, described ubm layer 18 being formed as solders such as gold-tin alloys, then by planting ball reflux technique, forming the array that multiple described solder bumps 19 is formed, for realizing being electrically connected and drawing with follow-up supporting construction.
Exemplarily, described adhesive layer 11 can be separated, to remove described carrier 10 and described adhesive layer 11 with described capsulation material layer 132 by heating or ultraviolet lighting technique.In heating process, along with the rising of temperature, the endocorpuscular volumetric expansion of described adhesive layer 11, makes described adhesive layer 11 reduce with the contact area of described capsulation material layer 132 and described semiconductor chip 12, finally realizes being separated; In ultraviolet lighting technique, the adhesion of described adhesive layer 11 changes along with the change of ultraviolet lighting, the separation of final both realizations.
In sum, the invention provides a kind of fan-out-type wafer-level packaging method, described fan-out-type wafer-level packaging method comprises the following steps: provide a carrier, forms adhesive layer at described carrier surface; At least semiconductor chip front side will be mounted on described adhesive layer surface upward; Adopt plastic package process by described semiconductor chip plastic packaging in capsulation material layer, and in described capsulation material layer, form the opening corresponding with the follow-up connecting through hole that will be formed and re-wiring layer simultaneously; Connecting through hole and re-wiring layer is formed in described opening.Adopt plastic package process by described semiconductor chip plastic packaging in capsulation material layer, and in capsulation material layer, form the opening corresponding with connecting through hole and re-wiring layer simultaneously, electronics art is utilized directly to write exposure association reaction ion etching technology, plastic packaging forming panel is prepared connecting through hole and rewiring layer pattern, after plastic package process process, described semiconductor chip plastic packaging is in capsulation material layer, and simultaneously by the Graphic transitions on upper plastic packaging forming panel in capsulation material layer, namely only need to provide plastic packaging forming panel on, electronics art is utilized directly to write exposure association reaction ion etching technology, connecting through hole and rewiring layer pattern is prepared at upper plastic packaging forming panel lower surface, and between adhesive layer capsulation material being placed in upper plastic packaging forming panel and being pasted with semiconductor chip, under preset temperature condition, make capsulation material soften, plastic packaging forming panel and lower plastic packaging forming panel in compression, by described semiconductor chip plastic packaging in capsulation material layer, and simultaneously by the Graphic transitions on mould in capsulation material, described capsulation material can be made to open to form capsulation material layer along described adhesive layer surface spreading, and the opening corresponding with connecting through hole and re-wiring layer is formed in institute's capsulation material layer, decrease coating dielectric layer, the processing steps such as photoetching RDL layer, significantly reduce production cost, and step is simple in whole technical process, greatly can improve the output of product, be with a wide range of applications in semiconductor packages territory.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a fan-out-type wafer-level packaging method, is characterized in that, described fan-out-type wafer-level packaging method at least comprises:
One carrier is provided, forms adhesive layer at described carrier surface;
At least semiconductor chip front side will be mounted on described adhesive layer surface upward;
Adopt plastic package process by described semiconductor chip plastic packaging in capsulation material layer, and in described capsulation material layer, form the opening corresponding with the follow-up connecting through hole that will be formed and re-wiring layer simultaneously;
Connecting through hole and re-wiring layer is formed in described opening.
2. fan-out-type wafer-level packaging method according to claim 1, it is characterized in that: adopt plastic package process by described semiconductor chip plastic packaging in capsulation material layer, and in described capsulation material layer, form the opening corresponding with the follow-up connecting through hole that will be formed and re-wiring layer simultaneously comprise:
There is provided plastic packaging forming panel and lower plastic packaging forming panel, utilize electronics art directly to write exposure association reaction ion etching technology, the lower surface of plastic packaging forming panel prepares connecting through hole and rewiring layer pattern on described.；
There is surface mount the described carrier of described semiconductor chip to face up to be placed in the upper surface of described lower plastic packaging forming panel;
Capsulation material is placed on the adhesive layer being pasted with described semiconductor chip;
Under preset temperature condition, compress described upper plastic packaging forming panel and described lower plastic packaging forming panel, namely described semiconductor chip plastic packaging is being formed described opening while capsulation material layer in described capsulation material layer;
Process is cured to described capsulation material layer, and discharges described upper plastic packaging forming panel and described lower plastic packaging forming panel.
3. fan-out-type wafer-level packaging method according to claim 2, is characterized in that: the material of described upper plastic packaging forming panel and described lower plastic packaging forming panel is diamond, stainless steel, silicon dioxide or pottery.
4. fan-out-type wafer-level packaging method according to claim 2, is characterized in that: described preset temperature is 125 DEG C ~ 150 DEG C.
5. fan-out-type wafer-level packaging method according to claim 2, is characterized in that: stripping film is all posted in the described lower surface of upper plastic packaging forming panel and the surface of described connecting through hole and rewiring layer pattern.
6. fan-out-type wafer-level packaging method according to claim 1, is characterized in that: adopt chemical plating process or electroplating technology in described opening, form described connecting through hole and described re-wiring layer.
7. fan-out-type wafer-level packaging method according to claim 6, is characterized in that: the additive containing special organometallic compounds form in described capsulation material, described additive physical-chemical reaction can occur and be activated under the irradiation of laser beam.
8. fan-out-type wafer-level packaging method according to claim 7, is characterized in that: adopt chemical plating process or electroplating technology forms described connecting through hole in described opening and described re-wiring layer comprises:
In described opening, make described capsulation material layer produce physical-chemical reaction by laser beam activation form metal core;
Based on described metal core, adopt chemical plating process or electroplating technology in described opening, form described connecting through hole and described re-wiring layer.
9. fan-out-type wafer-level packaging method according to claim 1, is characterized in that: also comprise form described connecting through hole and described re-wiring layer in described opening after:
Dielectric layer is formed at described re-wiring layer and described capsulation material layer surface;
Graphical described dielectric layer, to form the perforate exposing described re-wiring layer in described dielectric layer;
Described re-wiring layer forms ubm layer;
Described ubm layer is planted ball backflow, forms solder bumps array;
Remove described carrier and described adhesive layer.
10. fan-out-type wafer-level packaging method according to claim 9, is characterized in that: adopt heating or ultraviolet lighting technique described adhesive layer to be separated, to remove described carrier and described adhesive layer with described capsulation material layer.
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| CN201510629484.0A CN105161433A (en) | 2015-09-28 | 2015-09-28 | Fan-out type wafer grade packaging method |
| PCT/CN2016/082777 WO2017054470A1 (en) | 2015-09-28 | 2016-05-20 | Fan-out wafer level packaging method |
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| CN201510629484.0A CN105161433A (en) | 2015-09-28 | 2015-09-28 | Fan-out type wafer grade packaging method |
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| WO2017054470A1 (en) * | 2015-09-28 | 2017-04-06 | 中芯长电半导体（江阴）有限公司 | Fan-out wafer level packaging method |
| WO2017124670A1 (en) * | 2016-01-22 | 2017-07-27 | 中芯长电半导体（江阴）有限公司 | Packaging method and packaging structure for fan-out chip |
| CN107992666A (en) * | 2017-11-28 | 2018-05-04 | 清华大学 | One kind escape wiring method |
| CN108630556A (en) * | 2017-03-23 | 2018-10-09 | 南茂科技股份有限公司 | Fingerprint identification packaging structure and manufacturing method thereof |
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| CN108565235B (en) * | 2018-05-31 | 2024-03-01 | 亚智系统科技(苏州)有限公司 | Surface treatment and packaging system for fan-out type wafer-level chip and operation method |
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| WO2017054470A1 (en) | 2017-04-06 |
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