CN105140120B - 一种igbt的制备方法 - Google Patents

一种igbt的制备方法 Download PDF

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CN105140120B
CN105140120B CN201510428457.7A CN201510428457A CN105140120B CN 105140120 B CN105140120 B CN 105140120B CN 201510428457 A CN201510428457 A CN 201510428457A CN 105140120 B CN105140120 B CN 105140120B
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igbt
acid lanthanum
preparation
nickel acid
transparent oxide
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CN105140120A (zh
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王丕龙
王新强
李向坤
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Qingdao Jiaen Semiconductor Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

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Abstract

本发明涉及一种IGBT芯片,包括背面导电缓冲层,导电缓冲层用镍酸镧透明氧化物制成,采用了镍酸镧透明氧化物制作导电缓冲层,其低电阻率特性降低了电流扩散层的厚度,因此一方面厚度的减少导致材料的减少,因而大大减少材料成本,另一方面,由于镍酸镧原材料的价格远低于钛/镍(Ti/Ni)复合金属缓冲层的价格,因此,使用镍酸镧透明氧化物制作的IGBT芯片与使用(Ti/Ni)复合金属缓冲层制作的IGBT芯片比较,降低了成本,再一方面,厚度的减少及制备方法的改进极大地提高了IGBT芯片的生产效率因而降低了IGBT芯片的生产成本。

Description

一种IGBT的制备方法
技术领域
本发明属于半导体技术领域,特别是涉及一种IGBT的制备方法。
背景技术
随着半导体制造技术的飞速发展,半导体器件为了达到更快的运算速度,更大的数据存储量以及更多的功能,半导体晶片朝向更高的元件密度,高集成度方向发展,对其物理结构和制造工艺的要求越来越高,绝缘栅双极型晶体管(Insulated Gate BipolarTransistor,简称IGBT)模块主要应用在变频器的主回路逆变器及一切逆变电路,即DC/AC变换中。当今以IGBT为代表的新型电力电子器件是高频电力电子线路和控制系统的核心开关器件,现已广泛应用于电力机车、高压输变电、电动汽车、伺服控制器、UPS、开关电源、斩波电源等领域,市场前景非常好。随着电力电子技术的发展,功率IGBT器件的应用越来越广泛。为了达到更好的器件性能,需要实现IGBT结构及性能的突破以实现降低IGBT导通电阻的需求。已有IGBT的铝/钛/镍/银的四层背面金属结构,导通电阻高且制备工艺复杂,使用镍酸镧透明氧化物制作导电缓冲层,可以降低生产成本,并降低产品的导通电阻。
中国专利CN 103165588 A公开了一种IGBT模块,包括DBC基板以及通过焊料与该基板焊接的底板,所述底板的焊接面上定义有焊接区域,所述焊接区域被沟槽分隔成多个区域单元,每个区域单元的面积小于或等于整个焊接区域面积的1/100。此IGBT模块,可以降低模块底板和DBC基板之间焊接层的空洞率,提升焊接质量,保证焊接质量稳定,但是其背面缓冲层结构还是传统工艺,成本很高。日本住友电气工业株式会社在中国申请的专利CN 102859698 A公开了一种IGBT,包括:设置在碳化硅半导体层中的沟槽,设置在碳化硅半导体层中的第一导电类型的体区;和至少覆盖沟槽的侧壁表面的绝缘膜,沟槽的侧壁表面是具有50°或更大65°或更小的偏离角的表面,沟槽的侧壁表面包括体区的表面,绝缘膜与至少沟槽的侧壁表面上的体区的表面接触,并且体区中的第一导电类型杂质浓度为5×1016cm-3或更大,但是这种IGBT的制备工艺更为复杂,成本非常高,不利于市场竞争。
发明内容
为解决IGBT制造工艺复杂,成本较高的问题,我们提出了一种IGBT的制备方法,采用本发明可以达到工艺简化,成本较低的目的。
本发明是通过以下技术方案实现的:
为达到上述目的,我们提出了一种IGBT的制备方法,步骤如下:
(1)选择衬底材料,衬底材料为N+(100)晶向,电阻率为0.001~0.002ohm*cm的硅抛光片;外延层的厚度为4~10um左右,且电阻率控制在0.1~10ohm*cm;
(2)IGBT正面结构制备:
在硅材料上生长氧化层,注入硼,并对其推进;
在氧化层上再淀积一层氮化硅或二氧化硅,涂上光致抗蚀剂,进行光刻构图,以暴露沟槽区域;
刻蚀暴露区域的二氧化硅或氮化硅,并去除光致抗蚀剂,然后再刻蚀硅,形成沟槽。沟槽的深度0.8~2.5um。沟槽宽度0.2~2um;
(3)IGBT背面用镍酸镧透明氧化物制作导电缓冲层,用旋涂法形成镍酸镧透明氧化物电极涂层,在氮气气氛下用150-300℃烘干,完成镍酸镧透明氧化物电极的制备。
优选地,上述的沟槽淀积的多晶硅厚度为0.5-1.5μm。
优选地,上述IGBT的背面结构为衬底材料的背面+Al+镍酸镧透明氧化物电极+Ag。
本发明的有益效果是:
1、简化了工艺流程,降低了制造成本,并降低产品的导通电阻。
附图说明
图1为原始硅片的示意图;
图2为IGBT正面器件元胞剖面示意图;
图3为本发明的IGBT整体结构。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。
实施例1
参阅图1,图2和图3,一种IGBT的制备方法,步骤如下:
一种IGBT的制备方法,步骤如下:
(1)选择衬底材料,衬底材料为N+(100)晶向,电阻率为0.001~
0.002ohm*cm的硅抛光片;外延层的厚度为4~10um左右,且电阻率控制在0.1~10ohm*cm;
(2)IGBT正面结构制备:
在硅材料上生长氧化层,注入硼,并对其推进;
在氧化层上再淀积一层氮化硅或二氧化硅,涂上光致抗蚀剂,进行光刻构图,以暴露沟槽区域;
刻蚀暴露区域的二氧化硅或氮化硅,并去除光致抗蚀剂,然后再刻蚀硅,形成沟槽。沟槽的深度0.8~2.5um。沟槽宽度0.2~2um;
(3)IGBT背面用镍酸镧透明氧化物制作导电缓冲层,用旋涂法形成镍酸镧透明氧化物电极涂层,在氮气气氛下用150-300℃烘干,完成镍酸镧透明氧化物电极的制备。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。

Claims (3)

1.一种IGBT的制备方法,其特征在于,包括如下步骤:
(1)选择衬底材料,衬底材料为N+(100)晶向,电阻率为0.001-0.002ohm*cm的硅抛光片;外延层的厚度为4-10um,且电阻率控制在0.1-10ohm*cm;
(2)IGBT正面结构制备:
在硅材料上生长氧化层,注入硼,并对其推进;
在氧化层上再淀积一层氮化硅或二氧化硅,涂上光致抗蚀剂,进行光刻构图,以暴露沟槽区域;
刻蚀暴露区域的二氧化硅或氮化硅,并去除光致抗蚀剂,然后再刻蚀硅,形成沟槽,沟槽的深度0.8-2.5um,沟槽宽度0.2-2um;
(3)IGBT背面用镍酸镧透明氧化物制作导电缓冲层,用旋涂法形成镍酸镧透明氧化物电极涂层,在氮气气氛下用150-300℃烘干,完成镍酸镧透明氧化物电极的制备。
2.根据权利要求1所述的一种IGBT的制备方法,其特征在于,所述的沟槽淀积的多晶硅厚度为0.5-1.5μm。
3.根据权利要求1所述的一种IGBT的制备方法,其特征在于,所述IGBT的背面结构为:衬底材料的背面+Al+镍酸镧透明氧化物电极+Ag。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184753A (zh) * 2011-03-21 2011-09-14 四川师范大学 全面积Ag/LNO复合电极材料及制备方法
CN104253043A (zh) * 2013-06-28 2014-12-31 无锡华润上华半导体有限公司 制造场截止型绝缘栅双极晶体管的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6537689B2 (en) * 1999-11-18 2003-03-25 American Superconductor Corporation Multi-layer superconductor having buffer layer with oriented termination plane

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184753A (zh) * 2011-03-21 2011-09-14 四川师范大学 全面积Ag/LNO复合电极材料及制备方法
CN104253043A (zh) * 2013-06-28 2014-12-31 无锡华润上华半导体有限公司 制造场截止型绝缘栅双极晶体管的方法

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